Recent questions tagged co-and-architecture

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1

Pipeline speedup
Consider a nonpipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is

asked 1 day ago in CO & Architecture by Kartavya Kothari (123 points) | 33 views

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2

Data Hazards
Find the data hazards(RAW,WAW,WAR) in the given instructions

asked 1 day ago in CO & Architecture by Vishnathan (285 points) | 7 views

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1 answer

3

Made Easy Test Series

asked 2 days ago in CO & Architecture by Gupta731 Active (1.5k points) | 41 views

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0 answers

4

Made Easy Test Series
How they have calculated the memory address part?

asked 2 days ago in CO & Architecture by Gupta731 Active (1.5k points) | 30 views

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1 answer

5

made easy test series
What should I assume as the size of HALT instruction ? HALT instruction comes under which type of instruction

asked 3 days ago in CO & Architecture by amitqy Junior (757 points) | 34 views

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6

Control Dependencies
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asked 3 days ago in CO & Architecture by Lakshmi kittur (61 points) | 82 views

+1 vote

2 answers

7

Set way Associative

asked 3 days ago in CO & Architecture by Na462 Loyal (6.9k points) | 37 views

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8

Data Hazard

asked 3 days ago in CO & Architecture by Na462 Loyal (6.9k points) | 27 views

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0 answers

9

Made Easy Test Series
Consider the following data path of a CPU. The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory ... minimum number of CPU clock cycles needed during the execution cycle of this instruction is: A. 4 B. 2 C. 3 D. 5

asked 3 days ago in CO & Architecture by Gupta731 Active (1.5k points) | 25 views

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1 answer

10

Made Easy Test Series
Suppose int c = 0xdeadbeef, how many of the following statements clears the rightmost two bits in c and leaves the rest of the bits unchanged? c = 0xdeadbeec 1. c &= 0xfffffffc 2. c = (c >> 2) << 2 3. c |= 0xfffffffc 4. c |= 0x00000003

asked 3 days ago in CO & Architecture by Gupta731 Active (1.5k points) | 12 views

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0 answers

11

Control dependencies
Consider a pipelined processor having 5 stages. The stage delays are 2, 3, 2.5, 3.2, 2.5ns and interstage buffer delays are 1ns. The 3rd stage is capable of deciding branch target address. Processor starts fetching new instruction when the conditional branch outcome is known. 20% of instructions are conditional branch, then calculate the execution time for 1000 instructions?

asked 4 days ago in CO & Architecture by Lakshmi kittur (61 points) | 80 views

+1 vote

1 answer

12

Gateforum Test Series

asked 6 days ago in CO & Architecture by Gupta731 Active (1.5k points) | 27 views

+1 vote

1 answer

13

Gateforum Test Series
Isn't the answer 18 ns but 36 ns is provided as a valid answer.

asked 6 days ago in CO & Architecture by Gupta731 Active (1.5k points) | 33 views

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14

What is the difference between Operand storage in Cpu and Operand location .

asked Nov 11 in CO & Architecture by radha gogia Loyal (7.7k points) | 30 views

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15

PIPELINE Doubt
consider a5 stage pipeline processor, 20% load instructions, 25% branches, 20% stores, 20% of all instructions are data dependent on instructions in front of them and branches are taken 75%of time. what would be the expected cpi?

asked Nov 10 in CO & Architecture by rishabhdevsingh1 (83 points) | 45 views

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16

pipeline
consider a5 stage pipeline processor, 20% load instructions, 25% branches, 20% stores, 20% of all instructions are data dependent on instructions in front of them and branches are taken 75%of time. what would be the expected cpi?

asked Nov 10 in CO & Architecture by rishabhdevsingh1 (83 points) | 22 views

+1 vote

1 answer

17

Gateforum Test Series

asked Nov 9 in CO & Architecture by Gupta731 Active (1.5k points) | 50 views

+1 vote

0 answers

18

COA: Cache Accesss Time
Little confusion with these questions. What will be o/p for these two questions one with Write back and the other is Write through. 1.)A 128 word cache and main memory are divided into 8 word blocks. The access time of a cache ... average access time? What will be the default technique ( write-allocate and no write-allocate)followed for Hierarchal and Simultaneous access ?

asked Nov 7 in CO & Architecture by Hemanth_13 Active (3k points) | 38 views

+1 vote

0 answers

19

Gateforum Test Series

asked Nov 7 in CO & Architecture by Gupta731 Active (1.5k points) | 33 views

0 votes

2 answers

20

Pipelining

asked Nov 7 in CO & Architecture by Na462 Loyal (6.9k points) | 69 views

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0 answers

21

Decoder

asked Nov 7 in CO & Architecture by Na462 Loyal (6.9k points) | 37 views

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1 answer

22

Branch Instruction

asked Nov 7 in CO & Architecture by Na462 Loyal (6.9k points) | 24 views

0 votes

1 answer

23

Cache Memory
More than one word is put in one cache block to (a) Exploit temporal locality references in a program (b) Exploit spatial locality references in a program (c) Reduce miss penalty (d) All of these

asked Nov 2 in CO & Architecture by Dhiraj Raj (79 points) | 25 views

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0 answers

24

Gateforum test series

asked Nov 2 in CO & Architecture by Gupta731 Active (1.5k points) | 15 views

0 votes

0 answers

25

Gateforum Test Series

asked Nov 2 in CO & Architecture by Gupta731 Active (1.5k points) | 7 views

+1 vote

0 answers

26

Gateforum Test Series

asked Nov 2 in CO & Architecture by Gupta731 Active (1.5k points) | 10 views

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0 answers

27

Gateforum Test Series

asked Nov 1 in CO & Architecture by Gupta731 Active (1.5k points) | 24 views

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0 answers

28

Design a binary multiply pipeline unit for two 4 bit operands.Use minimum number of CSA's and CPA's.

asked Oct 31 in CO & Architecture by LavTheRawkstar Active (5.2k points) | 10 views

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0 answers

29

Test Series

asked Oct 31 in CO & Architecture by Gupta731 Active (1.5k points) | 12 views

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0 answers

30

Test Series
A two-word instruction "JMP 65" is located from the address 200010. What is the effective address computed if the instruction follows relative addressing mode? My answer is 2065, Why should it be 2067

asked Oct 31 in CO & Architecture by Gupta731 Active (1.5k points) | 17 views

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