Recent questions tagged co-and-architecture

+2 votes

2 answers

1

ISRO2020-16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $ADD, SUB$ and $MOV$. Consider $2$ ... is better in terms of memory accesses and by how many $MOV$ instructions ? Case $2,2$ Case $2,3$ Case $1,2$ Case $1,3$

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 216 views

+1 vote

1 answer

2

ISRO2020-15
A stack organized computer is characterised by instructions with indirect addressing direct addressing zero addressing index addressing

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 171 views

+1 vote

1 answer

3

ISRO2020-6
A non-pipeined CPU has $12$ general purpose registers $(R0,R1,R2 ..,R12)$. Following operations are supported $ADD\ Ra,\ Rb,\ Rr$ Add $Ra$ to $Rb$ and store the result in $Rr$ $MUL\ Ra,\ Rb,\ Rr$ Multiply $Ra$ to $Rb$ and store the result in $Rr$ $MUL$ ... $R0,R1$ and $R2$ and the contents of these registers must not be modified. $5$ $6$ $7$ $8$

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 173 views

+2 votes

1 answer

4

ISRO2020-5
An array of $2$ ...

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 172 views

+3 votes

2 answers

5

ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 218 views

+1 vote

2 answers

6

ISRO2020-46
A magnetic disk has $100$ cylinders, each with $10$ tracks of $10$ sectors. If each sector contains $128$ bytes, what is the maximum capacity of the disk in kilobytes? $1,280,000$ $1280$ $1250$ $128,000$

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 223 views

+1 vote

1 answer

7

ISRO2020-43
Which of the following is an efficient method of cache updating Snoopy writes Write through Write within Buffered write

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 152 views

+2 votes

1 answer

8

ISRO2020-49
One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called True dependency Anti-dependency Output dependency Control Hazard

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 108 views

+1 vote

1 answer

9

ISRO2020-3
Which of the following affects the processing power assuming they do not influence each other Data bus capability Address scheme Clock speed $3$ only $1$ and $3$ only $2$ and $3$ only $1,2$ and $3$

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 116 views

+1 vote

2 answers

10

ISRO2020-2
Statements associated with registers of a CPU are given. Identify the false statement. The program counter holds the memory address of the instruction in execution Only opcode is transferred to the control unit An instruction in the instruction register consists of the ... The value of the program counter is incremented by $1$ once its value has been read to the memory address register

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 161 views

+1 vote

1 answer

11

ISRO2020-1
The immediate addressing mode can be used for Loading internal registers with initial values Perform arithmetic or logical operation on data contained in instructions Which of the following is true? Only $1$ Only $2$ Both $1$ and $2$ Immediate mode refers to data in cache

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 93 views

+2 votes

2 answers

12

ISRO2020-8
Consider a $32$- bit processor which supports $70$ instructions. Each instruction is $32$ bit long and has $4$ fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is $8191$. How many registers does the processor has? $32$ $64$ $128$ $16$

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 117 views

+2 votes

2 answers

13

ISRO2020-7
Consider a $5$- segment pipeline with a clock cycle time $20$ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute $100$ instructions. (if an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline) $5$ $4.03$ $4.81$ $4.17$

asked Jan 13 in CO and Architecture by Satbir Boss (24.2k points) | 213 views

0 votes

2 answers

14

Stallings 6e Exercise-11.10 (page number-539) I/O Management
A 32-bit computer has two selector channels and one multiplexor channel. Each selector channel supports two magnetic disk and two magnetic tape units. The multiplexor channel has two line printers, two card readers, and ten VDT terminals ... reader 1.2 Kbytes/s VDT 1 Kbytes/s Estimate the maximum aggregate I/O transfer rate in this system

asked Jun 5, 2019 in Operating System by aditi19 Loyal (5.2k points) | 86 views

0 votes

1 answer

15

No of bits required to encode instructions
A computer has the following ISA and description - LOAD and STORE instructions capable of storing data from the accumulator to memory locations with indirect mode taking the argument as a register MOV capable of copying data from one register to another ADD ... 5 bit offset Min no of bits required to encode all the instructions above ?? Is it 4 bits ??

asked Jun 4, 2019 in CO and Architecture by s_dr_13 (299 points) | 90 views

0 votes

1 answer

16

Indirect Addressing Mode
Consider an instruction of indirect addressing mode. What are the number of memory references by the processor when instruction is a computation that requires a single operand and when it is an unconditional branch instruction respectively ?? 3,3 3,2 2,2 4,3 I believe the answer is B Correct me

asked Jun 4, 2019 in CO and Architecture by s_dr_13 (299 points) | 66 views

0 votes

2 answers

17

machine instructions and addressing modes
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$

asked May 24, 2019 in CO and Architecture by Gitika Babbar (157 points) | 196 views

+2 votes

1 answer

18

Self Doubt: CO Syllabus
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

asked May 23, 2019 in CO and Architecture by Hirak Active (3.6k points) | 104 views

0 votes

0 answers

19

PIPELINING.
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?

asked May 21, 2019 in CO and Architecture by Ritabrata Dey (53 points) | 58 views

+1 vote

1 answer

20

Made Easy Test Series:Microprogramming
A hypothetical cpu supports $300$ instructions.each instruction takes $5$ cycle to accomplish the execution. the control unit is designed using vertical programming which has $130$ control signals $,64$ flags and $12$ branch conditions .$X$ and ... register$(CDR)$ respectively.value of $X+Y$ is ______? How to work with branch condition in micro programming :(

asked May 20, 2019 in CO and Architecture by srestha Veteran (119k points) | 175 views

0 votes

1 answer

21

ISI2018-PCB-CS8
Consider a $5$ ... $\text{(in ns)}$ needed to execute the program.

asked May 12, 2019 in Operating System by akash.dinkar12 Boss (42.5k points) | 121 views

0 votes

0 answers

22

No of chips
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. No of chips required to design the memory system ______. Please provide a detailed solution.

asked May 7, 2019 in CO and Architecture by Tuhin Dutta Boss (10.7k points) | 132 views

0 votes

0 answers

23

Branch Address
To get branch address, do we need base register value or Program Counter value?

asked Apr 17, 2019 in CO and Architecture by srestha Veteran (119k points) | 63 views

0 votes

0 answers

24

#Pipeliningdoubt
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.

asked Apr 16, 2019 in CO and Architecture by Ritabrata Dey (53 points) | 33 views

0 votes

0 answers

25

Microprogrammed approach
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?

asked Apr 12, 2019 in CO and Architecture by Miny (139 points) | 12 views

0 votes

0 answers

26

Carl Hamacher: Machine Instruction and Programs-Chapter $2$
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ ... //Auto Decrement $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement

asked Apr 2, 2019 in CO and Architecture by srestha Veteran (119k points) | 78 views

0 votes

1 answer

27

Memory Access Doubt
How many memory accesses are there in this code? LOAD R1, a(RO)

asked Apr 1, 2019 in CO and Architecture by aditi19 Loyal (5.2k points) | 96 views

0 votes

0 answers

28

CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.

asked Mar 20, 2019 in CO and Architecture by Devshree Dubey Boss (13.8k points) | 42 views

0 votes

0 answers

29

Subject Topic- CO & Architecture
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB

asked Mar 18, 2019 in CO and Architecture by Doraemon Junior (791 points) | 60 views

+1 vote

0 answers

30

Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).

asked Mar 10, 2019 in CO and Architecture by s_dr_13 (299 points) | 134 views

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