Recent questions tagged co-and-architecture

+1 vote

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1

Pipeline Stall
Whenever Question is given on pipeline with branching i am confused to calculate that how many stalls will be there in the pipeline according to the constraint depicted in the pipeline. How to solve Such Questions? Like in this Question https://gateoverflow.in/683/gate2000 ... And what is meant by this line "If there are N Cycles then N-1 Stalls will be there"? Please Help

asked 2 days ago in CO & Architecture by Na462 Active (1.6k points) | 23 views

+1 vote

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2

Pipeline
Say Machine with 10ns click and takes 4 cycles for AlU and other operations. When we talk about the time taken by pipelined processor it is = the highest time taken by a stage + overhead We took the highest time only because we know that there is no stalling so ... plz explain why then CPI is one in all cases when stalls aren't there. And plz explain the cpi for non pipelined processor .

asked 2 days ago in CO & Architecture by Na462 Active (1.6k points) | 13 views

+1 vote

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3

#sample_test_iitk
An address sequence S experiences 100 compulsory cache misses. The sequence S experiences 500 misses when it is passed through a 32 KB fully-associative cache. The sequence S experiences 1000 misses when it is passed through a 32 KB 8-way set- ... conflict misses that the sequence S experiences when it is passed through a 32 KB 8-way set-associative cache is ___________

asked 6 days ago in CO & Architecture by tapzo Junior (507 points) | 43 views

0 votes

1 answer

4

Addressing Mode
Adding a constant to the content of register Is it a)Immediate mode or b) Indexed mode?

asked 6 days ago in CO & Architecture by srestha Veteran (81.9k points) | 47 views

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5

MCQs in Computer Science -Timothy Williams 5 edition

asked Apr 10 in CO & Architecture by DEEPAK PANDEY 1 (165 points) | 30 views

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2 answers

6

I/O organization- Hamacher
Consider a synchronous bus that operates according to the timing diagram in figure. The address transmitted by the processor appears on the bus after 4 ns. The propagation delay on the bus wires between the processor and different devices connected varies from 1 to ... . The input buffer needs 3 ns. set up time. What is maximum clock speed at which this bus can operate?

asked Apr 8 in CO & Architecture by srestha Veteran (81.9k points) | 37 views

+3 votes

1 answer

7

computer organization
Consider two cache organizations. The first one if $64 \text{ KB}$ way associative with $64\text{ byte}$ block size. The second one is of the $64 \text{ KB}$ direct mapped cache. The size of an address is $32\text{bits}$ in both ... between the hit latencies of both cache organizations (i.e. associative hit latency - direct mapped hit latency) (in nsec) is ________ .

asked Apr 6 in CO & Architecture by Prince Sindhiya (355 points) | 70 views

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8

Made easy co

asked Apr 6 in CO & Architecture by Prince Sindhiya (355 points) | 79 views

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9

There seem two version of carl hamacher books? which one to get?

asked Apr 6 in CO & Architecture by cynicthnkr (7 points) | 27 views

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1 answer

10

Videos for Computer Architecture
The Gate Overflow Page for CO&A(https://gatecse.in/co-architecture/) has a broken YouTube link and I could not find any other good video lectures for Computer Organization. Kindly suggest any online video lectures that would be useful for GATE preparation

asked Apr 5 in CO & Architecture by Sivarama Subramanian (153 points) | 46 views

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1 answer

11

Computer Organization
Suppose we are given frequency of cpu say 2GHZ then 1/2GHZ will be the instruction cycle time rt? I.e time to complete one instruction. Is instruction cycle time and cpu cycle time the same thing?

asked Apr 1 in CO & Architecture by Na462 Active (1.6k points) | 29 views

0 votes

0 answers

12

PGEE - Sample Question
Consider the following statements which may or may not be true. A bit in a control register is used to differentiate between kernel and user mode. A program translates to kernel mode when it executes a bad instruction. Modification to page tables is ... (iii) is essential for processes to execute Statement (iv) is required for object-oriented programs Statement (v) is true

asked Mar 30 in Operating System by Archit Sanghvi (123 points) | 139 views

+1 vote

2 answers

13

pipelining
A CPU has five-stage pipeline where each stage takes $1\hspace{0.1cm}ns$, $2\hspace{0.1cm}ns$, $1.5\hspace{0.1cm} ns$, $3\hspace{0.1cm}ns$, $2.5\hspace{0.1cm} ns$. Instruction fetch happens in the first stage of the pipeline. A ... one clock cycle. $30\%$ of the instructions are conditional branches. Find the average execution time of the program for $1200$ instructions is ________.

asked Mar 29 in CO & Architecture by Amit puri Active (2.8k points) | 127 views

+2 votes

1 answer

14

Memory interfacing
A memory constructed with 2B words and capacity of memory $2^{18}$ bits. Number of decoder required and type of decoder if memory built using $1K\times 4$ RAM chips? (if possible give some reference and diagram)

asked Mar 24 in CO & Architecture by srestha Veteran (81.9k points) | 105 views

+1 vote

0 answers

15

gate 1998-Cache memory

asked Mar 22 in CO & Architecture by HHH777 (19 points) | 48 views

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16

# Co doubt
How instruction 1 is taking 2 words?????

asked Mar 21 in CO & Architecture by Sankha Narayan Bose (123 points) | 31 views

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17

Hit Ratio and miss ratio question
In some problems we multiply only with the second part of the equation with (1-H1) component and leave the first part. Whereas in other cases we multiply with cache hit and miss. Is there any patterns for this or could be explained.

asked Mar 17 in CO & Architecture by nirupama thakur (15 points) | 48 views

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1 answer

18

Shift operator
Why left shift operator does't preserve its sign bit?? I think not preserving sign bit is meaning less.

asked Mar 17 in CO & Architecture by Ravi prakash pandey Junior (751 points) | 45 views

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1 answer

19

Pipeline Stall
I am very Confused in determining the number of stalls in a given execution. Please determine how to find out the number of stalls in the execution of the pipeline. Like In this example calculate the number of stalls:- I successfully calculated the total clock cycle but plz indicate number of ... place ? Instruction Fetch Decode Execute Write 1 1 2 2 1 2 2 3 3 2 3 3 1 1 1 4 1 1 1 1

asked Mar 16 in CO & Architecture by Na462 Active (1.6k points) | 83 views

0 votes

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20

#1 Testbook Mock Test (COA - Cache Memory)

asked Mar 15 in CO & Architecture by rfzahid Active (1.2k points) | 48 views

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1 answer

21

Split Phase of Pipelining
Can anybody explain the concept of Split phase (2 stages in same clock-cycle) in Pipelining Briefly. i.e. When to use,How to use and Advantages.

asked Mar 13 in CO & Architecture by Na462 Active (1.6k points) | 35 views

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22

Pipeline
@Arjun sir In the Question :- https://gateoverflow.in/1391/gate2005-68 I have drawn like :- F D E M W F D D E M W F - D E M W Total 8 Clock cycle with operand forwarding. Why cant we Overlap stuffs means:- In first case at second instruction ... cycles. Checkout the comment of Arjun Sir:- https://gateoverflow.in/3623/gate2006-it-79 Or when to use such technique as depicted by Arjun Sir.

asked Mar 13 in CO & Architecture by Na462 Active (1.6k points) | 36 views

0 votes

1 answer

23

Pipeline
In question like say "I have $4$ stages with delay $1,2,3,4 \hspace{0.1cm}ns$ and total instructions are $100$. Calculate the total time?" In such questions by default we consider a synchronous pipeline processor right? that why we apply $(k+n-1)*tp$ ??

asked Mar 13 in CO & Architecture by Na462 Active (1.6k points) | 44 views

+1 vote

1 answer

24

Computer Organization
Is Horizontal and Vertical Microprogramming in our syllabus for GATE 2019 ?

asked Mar 12 in GATE by Na462 Active (1.6k points) | 61 views

0 votes

1 answer

25

Cache Organization
Ques. In a two-level memory hierarchy, let $t_1 = 10^{-7s}$ and $t_2 = 10^{-2s}$. If ta denotes the average access time of the memory hierarchy, and if we define the access efficiency to be equal to $t_1=t_a$, then what must the hit ratio $H$ be in ... Time)$ Why they have considered only Hit Time instead of Hit Ratio and Hit time.... and plz explain which one to use and when...

asked Mar 10 in CO & Architecture by Na462 Active (1.6k points) | 54 views

+1 vote

1 answer

26

Cache Organization
My Doubt is simple How to know which cache organization to use hierarchical or direct cache while calculating the average access time. Like in this Question:- https://gateoverflow.in/2308/gate1993-11 Here hierarchal access is used and why? Plz help me

asked Mar 9 in CO & Architecture by Na462 Active (1.6k points) | 31 views

0 votes

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27

Computer Organization and architecture
Design a optimal system with 25 processing elements and 9 shared memory modules

asked Mar 9 in CO & Architecture by Debargha Das (11 points) | 47 views

0 votes

2 answers

28

ACE Test Series

asked Mar 8 in CO & Architecture by pankaj_vir Loyal (6.3k points) | 80 views

0 votes

0 answers

29

Unable to understand how to take 1-Address Instruction Opcode ? I am quiet Confused.

asked Mar 5 in CO & Architecture by Karan Dodwani (27 points) | 87 views

0 votes

1 answer

30

Cache-Memory
If it takes 50ns to search associative registers and also about 100ns to get access to main memory then find out the % of slowdown in memory access time?(Given hit ratio 90%)- A)60 B)75 C)20 D)90

asked Mar 3 in CO & Architecture by satendra (121 points) | 45 views

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