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Recent questions tagged co-and-architecture

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Recent questions tagged co-and-architecture

1 vote
1 answer
1
UGCNET-Oct2020-II: 5
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$
asked Nov 20, 2020 in CO and Architecture jothee 195 views
0 votes
1 answer
2
UGCNET-Oct2020-II: 6
The following program is stored in memory unit of the basic computer. What is the content of the accumulator after the execution of program? (All location numbers listed below are in hexadecimal). ... $1002\text{H}$ $2011\text{H}$ $2022\text{H}$ $0215\text{H}$
The following program is stored in memory unit of the basic computer. What is the content of the accumulator after the execution of program? (All location numbers listed below are in hexadecimal). ... $1002\text{H}$ $2011\text{H}$ $2022\text{H}$ $0215\text{H}$
asked Nov 20, 2020 in CO and Architecture jothee 116 views
0 votes
1 answer
3
UGCNET-Oct2020-II: 7
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$
asked Nov 20, 2020 in CO and Architecture jothee 96 views
0 votes
1 answer
4
UGCNET-Oct2020-II: 43
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer from the options ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$
asked Nov 20, 2020 in CO and Architecture jothee 60 views
0 votes
0 answers
5
UGCNET-Oct2020-II: 44
Which of the following statements with respect to multiprocessor system are true? Multiprocessor system is controlled by one operating system In Multiprocessor system, multiple computers are connected by the means of communication lines Multiprocessor system is classified as multiple instruction stream and multiple ... $(b)$ only $(a)$ and $(c)$ only $(b)$ and $(c)$ only
Which of the following statements with respect to multiprocessor system are true? Multiprocessor system is controlled by one operating system In Multiprocessor system, multiple computers are connected by the means of communication lines Multiprocessor system is classified as multiple instruction stream and multiple data stream ... $(b)$ only $(a)$ and $(c)$ only $(b)$ and $(c)$ only
asked Nov 20, 2020 in CO and Architecture jothee 39 views
0 votes
1 answer
6
UGCNET-Oct2020-II: 75
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$
asked Nov 20, 2020 in CO and Architecture jothee 60 views
1 vote
1 answer
7
UGCNET-Oct2020-II: 81
Given below are two statements: Statement $I$: Hardwired control unit can be optimized to produce fast mode of operation Statement $II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, choose the correct ... false Statement $I$ is correct but Statement $II$ is false Statement $I$ is incorrect but Statement $II$ is true
Given below are two statements: Statement $I$: Hardwired control unit can be optimized to produce fast mode of operation Statement $II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, choose the correct answer from the ... are false Statement $I$ is correct but Statement $II$ is false Statement $I$ is incorrect but Statement $II$ is true
asked Nov 20, 2020 in CO and Architecture jothee 39 views
0 votes
4 answers
8
NIELIT 2016 MAR Scientist C - Section C: 19
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the Stack pointer Accumulator Program counter Stack
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the Stack pointer Accumulator Program counter Stack
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 288 views
0 votes
1 answer
9
NIELIT 2016 MAR Scientist C - Section C: 27
The process of entering data into a storage location causes variation in its address number adds to the contents of the location is called a readout operation is destructive of previous contents
The process of entering data into a storage location causes variation in its address number adds to the contents of the location is called a readout operation is destructive of previous contents
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 157 views
0 votes
1 answer
10
NIELIT 2016 MAR Scientist C - Section C: 28
Serial access memories are useful in applications where data consists of numbers short access time is required each stored word is processed differently data naturally needs to flow in and out in serial form
Serial access memories are useful in applications where data consists of numbers short access time is required each stored word is processed differently data naturally needs to flow in and out in serial form
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 116 views
0 votes
1 answer
11
NIELIT 2016 MAR Scientist C - Section C: 45
An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control
An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 193 views
0 votes
1 answer
12
NIELIT 2016 MAR Scientist C - Section C: 46
Micro program is the name of source program in micro computers the set of instructions indicating the primitive operations in a system primitive form of macros used in assembly language programming program of very small size
Micro program is the name of source program in micro computers the set of instructions indicating the primitive operations in a system primitive form of macros used in assembly language programming program of very small size
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 143 views
0 votes
1 answer
13
NIELIT 2016 MAR Scientist C - Section C: 47
If a processor does not have any stack pointer register, then it cannot have subroutine call instruction it can have subroutine call instruction, but no nested subroutine calls nested subroutine calls are possible, but interrupts are not all sequences of subroutine calls and also interrupts are possible
If a processor does not have any stack pointer register, then it cannot have subroutine call instruction it can have subroutine call instruction, but no nested subroutine calls nested subroutine calls are possible, but interrupts are not all sequences of subroutine calls and also interrupts are possible
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 110 views
0 votes
1 answer
14
NIELIT 2016 MAR Scientist C - Section C: 61
Microprogramming is a technique for writing small programs effectively programming output/input routines programming the microprocessors programming the control steps of a computer
Microprogramming is a technique for writing small programs effectively programming output/input routines programming the microprocessors programming the control steps of a computer
asked Apr 2, 2020 in Digital Signal Processing Lakshman Patel RJIT 92 views
0 votes
2 answers
18
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 18
A pipeline is having speed up factor as $10$ and operating with efficiency of $80\%.$ What will be the number of stages in the pipeline? $10$ $8$ $13$ None
A pipeline is having speed up factor as $10$ and operating with efficiency of $80\%.$ What will be the number of stages in the pipeline? $10$ $8$ $13$ None
asked Apr 1, 2020 in CO and Architecture Lakshman Patel RJIT 258 views
0 votes
1 answer
19
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 22
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
In time division switches if each memory access takes $100\;ns $ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
asked Apr 1, 2020 in CO and Architecture Lakshman Patel RJIT 275 views
0 votes
1 answer
20
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 26
Which level of RAID refers to disk mirroring with block striping? RAID level $1$ RAID level $2$ RAID level $0$ RAID level $3$
Which level of RAID refers to disk mirroring with block striping? RAID level $1$ RAID level $2$ RAID level $0$ RAID level $3$
asked Apr 1, 2020 in CO and Architecture Lakshman Patel RJIT 146 views
0 votes
1 answer
21
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 35
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$
asked Apr 1, 2020 in CO and Architecture Lakshman Patel RJIT 302 views
0 votes
2 answers
22
NIELIT 2017 OCT Scientific Assistant A (CS) - Section C: 1
Which level of RAID refers to disk mirroring with block striping? RAID level $1$ RAID level $2$ RAID level $0$ RAID level $3$
Which level of RAID refers to disk mirroring with block striping? RAID level $1$ RAID level $2$ RAID level $0$ RAID level $3$
asked Apr 1, 2020 in CO and Architecture Lakshman Patel RJIT 191 views
2 votes
3 answers
23
NIELIT 2017 OCT Scientific Assistant A (CS) - Section C: 2
Which of the following is not a form of main memory? Instruction cache Instruction register Instruction opcode Translation look-aside buffer
Which of the following is not a form of main memory? Instruction cache Instruction register Instruction opcode Translation look-aside buffer
asked Apr 1, 2020 in CO and Architecture Lakshman Patel RJIT 227 views
0 votes
2 answers
26
NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 25
A micro programmed control unit Is faster than a hardwired unit Facilitates easy implementation of a new instruction Is useful when small programs are to be run All of the above
A micro programmed control unit Is faster than a hardwired unit Facilitates easy implementation of a new instruction Is useful when small programs are to be run All of the above
asked Apr 1, 2020 in CO and Architecture Lakshman Patel RJIT 196 views
1 vote
2 answers
27
NIELIT 2017 DEC Scientific Assistant A - Section B: 23
A $3.5$ inch micro floppy high density disk contains the data _________ . $720 \: MB$ $1.44 \: MB$ $720 \: KB$ $1.44 \: KB$
A $3.5$ inch micro floppy high density disk contains the data _________ . $720 \: MB$ $1.44 \: MB$ $720 \: KB$ $1.44 \: KB$
asked Mar 31, 2020 in CO and Architecture Lakshman Patel RJIT 356 views
1 vote
4 answers
28
NIELIT 2016 MAR Scientist B - Section C: 9
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor? Pointers. Arrays. Records. All of these.
asked Mar 31, 2020 in CO and Architecture Lakshman Patel RJIT 512 views
1 vote
2 answers
30
NIELIT 2016 DEC Scientist B (IT) - Section B: 39
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data
asked Mar 31, 2020 in CO and Architecture Lakshman Patel RJIT 293 views
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