Recent questions tagged co-and-architecture

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CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.

asked 3 days ago in CO & Architecture by Devshree Dubey Boss (13.6k points) | 10 views

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Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).

asked Mar 10 in CO & Architecture by s_dr_13 (93 points) | 29 views

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3

Pipeline
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE

asked Mar 8 in CO & Architecture by s_dr_13 (93 points) | 23 views

–1 vote

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GradeUp COA
If a processor has 64 address lines and 8 data lines. Then find maximum number of opcodes generated by processor. a)6 b)9 c)3 d)8

asked Feb 24 in CO & Architecture by Abhisek Tiwari 4 Active (4.2k points) | 119 views

+1 vote

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#ComputerArchitecture
If a computer executes a store, should it place the data into the cache or main memory? Cache only Main memory only Both cache and main memory Cache only OR Both cache and main memory

asked Feb 14 in CO & Architecture by Reshu $ingh (345 points) | 51 views

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#MulticoreVSParallel
What is the difference between Multicore Processing and Parallel processing given that in both tasks/operations are performed simultaneously?

asked Feb 13 in CO & Architecture by Reshu $ingh (345 points) | 52 views

+1 vote

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GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

asked Feb 7 in CO & Architecture by Arjun Veteran (386k points) | 2.9k views

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GATE2019-2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF

asked Feb 7 in CO & Architecture by Arjun Veteran (386k points) | 2k views

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9

GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of road operations is ______$\times 10^6$ bytes/sec

asked Feb 7 in CO & Architecture by Arjun Veteran (386k points) | 1.9k views

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10

ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

asked Feb 1 in CO & Architecture by newdreamz a1-z0 Active (1.7k points) | 55 views

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11

GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.

asked Feb 1 in CO & Architecture by Aman Janko (47 points) | 32 views

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computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

asked Feb 1 in CO & Architecture by learner_geek Active (3.7k points) | 59 views

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13

MadeEasy Test Series 2019: CO & Architecture- Cache Memory
Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512

asked Jan 30 in CO & Architecture by Ram Swaroop Active (2.5k points) | 103 views

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GB Test series: COA
Consider a 32-bit processor with 150 registers and having 76 different types of instructions. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a thirteen-bit immediate value. Each instruction ... given in this problem and i don't think so that 32 bit processor means word size is 32 bits, right?

asked Jan 29 in CO & Architecture by chauhansunil20th Active (4.8k points) | 115 views

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15

MadeEasy Test Series 2019: CO & Architecture - Cache Memory
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be

asked Jan 29 in CO & Architecture by Ram Swaroop Active (2.5k points) | 83 views

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16

IEEE smallest difference
What is the minimum difference between two successive real numbers representable in this system?

asked Jan 28 in Digital Logic by Balaji Jegan Active (4.8k points) | 87 views

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MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order. 4,6,3,8,5,6,0,15,6,17,20,15,0,8 If LRU is used for block replacement then memory set 17 will be in the cache block ____. (PS: the given answer is 1)

asked Jan 28 in CO & Architecture by snaily16 (263 points) | 57 views

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18

Self doubt
please arrange them in increasing order of speed: Relative addressing , Absolute addressing , Register addressing , Register Indirect addressing , Indirect addressing , Base addressing , indexed addressing

asked Jan 27 in CO & Architecture by iamdeepakji (227 points) | 35 views

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19

Computer organisation cache
Why can't we have n-levels of cache ?

asked Jan 27 in CO & Architecture by Priyansh Singh (317 points) | 48 views

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20

Cache Organization
Can any one help me out with this question : This was asked in MadeEasy CBT held on 23rd jan

asked Jan 25 in CO & Architecture by Nandkishor3939 Active (1.2k points) | 128 views

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21

MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
All is fine but how did they calculate the miss rate of level 2 cache (L2) i.e.how is m2=0.46875?

asked Jan 24 in CO & Architecture by Iamniks4 (63 points) | 46 views

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1 answer

22

MadeEasy Full Length Test 2019: CO & Architecture - Speedup

asked Jan 23 in CO & Architecture by jatin khachane 1 Loyal (6.4k points) | 64 views

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23

Made easy test series pipelining
Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3,8, 5, 6 and 4 respectively. What is average CPl of non-pipeline CPU when speed up achieved by to pipeline is 4? A. 1.33 B. 1.76 C. 1.14 D. 1.66

asked Jan 23 in CO & Architecture by Ram Swaroop Active (2.5k points) | 95 views

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24

Pipeline Efficiency
A pipeline has a speedup factor of 5 and operating at 70% efficiency. How many stages are there in the pipeline?

asked Jan 22 in CO & Architecture by jatin khachane 1 Loyal (6.4k points) | 46 views

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1 answer

25

Ace Test Series: Operating System - TLB Effective Access Time

asked Jan 21 in Operating System by Na462 Loyal (8.7k points) | 84 views

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26

Ace Test Series: CO & Architecture - Cache Memory

asked Jan 21 in CO & Architecture by Na462 Loyal (8.7k points) | 69 views

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27

Ace Test Series: CO & Architecture - Cache Misses Type

asked Jan 21 in CO & Architecture by Na462 Loyal (8.7k points) | 85 views

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Ace Test Series: CO & Architecture - Instruction Execution
CPU can leave current instruction execution, without completing it for : Service of interrupt DMA Both Neither

asked Jan 21 in CO & Architecture by Na462 Loyal (8.7k points) | 54 views

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29

Speedup

asked Jan 21 in CO & Architecture by bts1jimin (245 points) | 18 views

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MadeEasy Test Series 2019: CO & Architecture - Machine Instruction
Q.A stack based CPU executes the instruction.Memory location 500 contains 0x88 and memory location 700 contains 0x37.The stack pointer is at 0x003F. The instructions are as follows: I1:PUSH 500 I2:PUSH 700 I3:ADD ... after execution instructions c)Memory location 600 contains 0xBF after execution instructions d)Both (a) and (c)

asked Jan 20 in CO & Architecture by Badayayash Junior (889 points) | 63 views

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