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Recent questions tagged co-and-architecture

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2 answers
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In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$
asked Apr 1 in CO and Architecture Lakshman Patel RJIT 76 views
0 votes
1 answer
14
Disk request come to a disk driver for cylinders in the order $10,22,20,2,40,6$ and $38,$ at a time when the disk drive is reading from cylinder $20$. The total seek time, if the disk arm scheduling algorithm is first-come-first-served is $900$ ms $850$ ms $360$ ms $876$ ms
asked Apr 1 in CO and Architecture Lakshman Patel RJIT 54 views
1 vote
2 answers
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Which of the following is an interrupt according to temporal relationship with system clock? Maskable interrupt Periodic interrupt Division by zero Synchronous interrupt
asked Mar 24 in CO and Architecture jothee 154 views
0 votes
2 answers
20
The general configuration of the microprogrammed control unit is given below: What are blocks B and C in the diagram respectively? Block address register and cache memory Control address register and control memory Branch register and cache memory Control address register and random access memory
asked Mar 24 in CO and Architecture jothee 114 views
0 votes
1 answer
22
In $8085$ microprocessor, the digit $5$ indicates that the microprocessor needs $-5$ volts, $+5$ volts supply $+5$ volts supply only $-5$ volts supply only $5$ MHz clock
asked Mar 24 in CO and Architecture jothee 96 views
0 votes
1 answer
23
In $8085$, which of the following performs: load register pair immediate operation? LDAX rp LKLD addr LXI rp, data INX rp
asked Mar 24 in CO and Architecture jothee 82 views
0 votes
1 answer
24
Consider the following assembly language instructions: mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H add ah, 0 What is the value in $ax$ register after execution of above instructions? $0270H$ $0170H$ $01E0H$ $0370H$
asked Mar 24 in CO and Architecture jothee 418 views
0 votes
1 answer
25
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and sign flag $(SF)$ after executing $'SUB AL, BL'$ assembly language instruction, are $AL=0FH; \: CF=1; \: SF= 1$ $AL = F0H; \: CF = 0; \: SF = 0$ $AL =F1H; \: CF = 1; \: SF= 1$ $AL =1FH; \: CF=1; \:SF=1$
asked Mar 24 in CO and Architecture jothee 219 views
5 votes
2 answers
26
Consider the following statements. Daisy chaining is used to assign priorities in attending interrupts. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. In polling,the CPU periodically checks the status bits to know if any device needs its ... same time. Which of the above statements is/are TRUE? Ⅰ and Ⅱ only Ⅰ and Ⅳ only Ⅰ and Ⅲ only Ⅲ only
asked Feb 12 in CO and Architecture Arjun 2.1k views
3 votes
6 answers
27
Consider the following data path diagram. Consider an instruction: $R0 \leftarrow R1 +R2$. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts $r$ and $w$ ... of execution of the above steps? $2,1,4,5,3$ $1,2,4,3,5$ $3,5,2,1,4$ $3,5,1,2,4$
asked Feb 12 in CO and Architecture Arjun 1.8k views
4 votes
4 answers
28
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2$0 ns to bring the first word of a block from the main memory, while each subsequent word takes $5$ ns. The word size is $64$ bits. The average memory access time in ns (round off to $1$ decimal place) is______.
asked Feb 12 in CO and Architecture Arjun 3.6k views
4 votes
4 answers
29
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined ... program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.
asked Feb 12 in CO and Architecture Arjun 2.4k views
3 votes
3 answers
30
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ ... and by how many $\text{MOV}$ instructions? $\text{Case 2,2}$ $\text{Case 2,3}$ $\text{Case 1,2}$ $\text{Case 1,3}$
asked Jan 13 in CO and Architecture Satbir 684 views
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