Recent questions tagged co-and-architecture

0 votes

0 answers

1

Minimum clock cycle

asked 17 hours ago in CO & Architecture by Na462 Loyal (5.7k points) | 11 views

0 votes

0 answers

2

Branch Offset
Consider a processor where each instruction size is exactly two bytes long. Conditional and unconditional branch instructions use PC relative addressing mode with offset specified in Bytes to the target location of the branch instruction; the offset is always with ... sequence. The below program is executed (All values are specified in decimal), type of memory is byte addressable

asked 17 hours ago in CO & Architecture by Na462 Loyal (5.7k points) | 10 views

0 votes

0 answers

3

Subroutine Call

asked 17 hours ago in CO & Architecture by Na462 Loyal (5.7k points) | 28 views

0 votes

0 answers

4

Memory cycles

asked 18 hours ago in CO & Architecture by Na462 Loyal (5.7k points) | 13 views

0 votes

0 answers

5

Vectored I/O

asked 18 hours ago in CO & Architecture by Na462 Loyal (5.7k points) | 10 views

0 votes

1 answer

6

Data dependancies
Anti- dependency will not ALWAYS create stall because we can use register renaming to remove stall. Please confirm below statement: Anti-dependency MAY create stall (True/False)

asked 1 day ago in CO & Architecture by Suneel Padala (57 points) | 8 views

0 votes

0 answers

7

#CO pipeline doubt
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below: What is the number of cycles needed to execute the following loop? For (i=1 to 2){I1; I2; ... stage, the current instruction(I4) cannot execute a given stage P.S.- Refer here- https://gateoverflow.in/244642/%23co-gate-2009-self-doubt

asked 3 days ago in CO & Architecture by iarnav Loyal (8.1k points) | 19 views

0 votes

0 answers

8

Self Doubt
how we generally write addressing mode in instruction. eg. immediate addressing mode: add #5 1. Direct 2. Indirect 3. Register 4. Register Indirect 5. Indexed 6. Based 7. Displacement 8. Stack

asked 5 days ago in CO & Architecture by iamdeepakji (39 points) | 9 views

0 votes

0 answers

9

#CO Gate 2009 Self Doubt.
Original question- https://gateoverflow.in/1314/gate2009-28 In the best answer selected, why in 6th cycle we are introducing I4 {S1} while I3 {S2} hasn't gone to next stage? In this question if we take the above approach, we will get different ... , Refer this GATE 2004-IT question- https://gateoverflow.in/3690/gate2004-it-47 in this we are doing as the above approach.

asked 5 days ago in CO & Architecture by iarnav Loyal (8.1k points) | 17 views

0 votes

0 answers

10

Doubt in memory hierarchy
What are the external connections in memory circuit ?

asked Sep 15 in CO & Architecture by Abbas Ahmad (7 points) | 5 views

0 votes

1 answer

11

Cache
What happens on write miss in a write back cache? First write in main memory then bring the block to cache (dirty bit = 0) or First bring the block to cache then write it (dirty bit = 1).

asked Sep 14 in CO & Architecture by MayankSharma (181 points) | 21 views

0 votes

0 answers

12

CO general doubt
Consider an array has 100 elements and each element occupies 4 words .A 32 word cache is used and divided into a block of 8 words .What is the hit ratio for this statement for(i=0; i<100; i++) A[i] = A[i]+10; I just want to ask that whenever ... ie 2 elements) are fetched and placed in cache,so why we are doing like this is it because we have to follow law of spatial locality ?

asked Sep 14 in CO & Architecture by Prince Sindhiya Active (2.7k points) | 18 views

0 votes

0 answers

13

Self doubt
When the process is in memory and executing with PC value = 100 Let virtual memory concept is used when next process is scheduled and main memory doesn't have space so anyone one of the process(pages) should be swapped out to secondary memory. If currently executing ... then in order to preserve its state does OS stores its PCB also in Secondary storage ?? and restore later to MM ??

asked Sep 14 in Operating System by jatin khachane 1 Junior (527 points) | 6 views

0 votes

0 answers

14

Computer organisation- DMA

asked Sep 13 in CO & Architecture by sidlewis (327 points) | 13 views

0 votes

0 answers

15

Computer Organisation- Cache

asked Sep 13 in CO & Architecture by sidlewis (327 points) | 9 views

0 votes

0 answers

16

Computer Organisation

asked Sep 13 in CO & Architecture by sidlewis (327 points) | 6 views

0 votes

1 answer

17

Computer Organisation

asked Sep 13 in CO & Architecture by sidlewis (327 points) | 26 views

0 votes

0 answers

18

Set Associative cache. Calculate cache capacity.

asked Sep 12 in CO & Architecture by Mk Utkarsh Boss (17k points) | 44 views

0 votes

0 answers

19

Self Doubt
Since a DMA contoller is connected with the number of I/O devices. Is it possible that DMA controller (say master) is connected with number of other DMA controllers (say slaves). And with these slaves DMA controller, a number of I/O devices are connected?

asked Sep 12 in CO & Architecture by !KARAN Junior (563 points) | 8 views

0 votes

0 answers

20

Dout Write_back
IN write-back policies what does meant by the update in memory is supposed to happen when block in cache is evicted?

asked Sep 10 in CO & Architecture by Vasu sahu (271 points) | 19 views

0 votes

0 answers

21

Self Doubt on GATE2005-65
https://gateoverflow.in/1388/gate2005-65 $\text{In this question, what will be the number of }$ $\textbf{cycles}$ $\text{needed during execution cycle of instruction}$ $\text{According to me I am getting 6 cycles. Please tell what could be the correct answer for it}$

asked Sep 10 in CO & Architecture by !KARAN Junior (563 points) | 21 views

0 votes

1 answer

22

Self doubt
What is the difference between Memory access time and Memory latency. Memory access time : It is the time elapsed between CPU generating request for particular address and the time it locates it on Memory before actual transfer of bytes into registers. Is Memory Latency is same as Memory access time ???

asked Sep 9 in CO & Architecture by jatin khachane 1 Junior (527 points) | 6 views

0 votes

0 answers

23

Self Doubt : Pipe lining
Given 100 instructions executed on a 5 stage pipeline . probability (p) that an instruction is branch is p. Branch penalty 4.Assuming that each stage of pipeline takes 1 cycle.Calculate total execution time. My query is since first instruction will take 5 clk so how to calculate ? is 5+ 99[(1-p)*1 + p*4] the correct approach ?

asked Sep 8 in CO & Architecture by Shiv Gaur Active (1.3k points) | 26 views

0 votes

0 answers

24

Addressing Instructions
Are memory to memory instructions allowed? Eg. ADD [123], [345] or MOV [123], [343] If not, then why?

asked Sep 6 in CO & Architecture by Asutosh (387 points) | 22 views

0 votes

0 answers

25

Operand Forwarding Doubt
I dont understand here:- Load R2,(R3) 1. Fetch 2. Decode: Rz <--- Address of R3 given in instruction 3. Compute : NOP 4. Memory Memory address <---[RZ] , read memory, Ry <---MemData 5. R2 <--- [Ry] If i wrote above right then R2 is available at Cycle 5 but there is extra stall at cycle 6 for Instruction j+1 why ??

asked Sep 3 in CO & Architecture by Na462 Loyal (5.7k points) | 22 views

0 votes

0 answers

26

Pipeline Doubt
Its a snapshot from hamacher. According to me there should be stall of 2 cycles why 3 ?? Because after Write stage the data will be available in register file so why extra stall in 6th clock cycle ?

asked Sep 3 in CO & Architecture by Na462 Loyal (5.7k points) | 13 views

0 votes

0 answers

27

Cache-tag-directory
What is the size of tag in cache directory for direct and set-associative memory? For set-associative memory do we multiply by no of sets or no of blocks? According to me Size of Tag in cache directory = Number of tag bits(+ any extra bits like valid, ... = Number of tag bits(+ any extra bits like valid, modified etc) * number of sets Tag is associated with each block or set?

asked Sep 2 in CO & Architecture by Apoorva Jain (135 points) | 26 views

0 votes

1 answer

28

Miss latency and miss penalty
Are miss latency & miss penalty same in cache?if no then what's the difference???

asked Aug 29 in CO & Architecture by MayankSharma (181 points) | 27 views

+1 vote

0 answers

29

COA -INSTRUCTION PIPELINE
Consider a 4 stage pipeline:fetch-IF(2cycle), decode& read -ID(1 cycle) execute-Ex(4 cycle for multiply and 7 cycle for divide ,1 cycle for all other arithmatic operations ) and Write Back WB(1 cycle) . Assume that in a program A there ... divides,85% of othe types of instructions that take 1 cycle in execute stage . How many cycle does it take to execute program A?

asked Aug 28 in CO & Architecture by gourav94240 (23 points) | 65 views

+3 votes

0 answers

30

Addressing Mode
Addressing Mode. Instruction Meaning Description $1.$Register Addressing Mode (or) Register Direct AM $\text{Add} R_{1},R_{2}$ $R_{1}\leftarrow R_{1}+R_{2}$ Two General Purpose Register value is added. Operands stored in GPRs $2 ... Plz check https://www.slideshare.net/aliasgharmanjotho11/addressing-modes-37108170 http://web.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/addressMode.html

asked Aug 28 in CO & Architecture by srestha Veteran (96.1k points) | 48 views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

Recent questions tagged co-and-architecture

Recent Posts

Recent Blog Comments