Recent questions tagged co-and-architecture

Recent questions tagged co-and-architecture

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Question on 4 way set associative cache
Consider a system with 4 way set associative cache of 256KB.The cache size is 8 words(32 bits per word).The smallest addressable unit is a byte, and memory addresses are 64 bits long. What percentage of the cache memory is used for tag bits?

Yashvir asked in CO and Architecture May 4

5 views

0 votes

1 answer

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can 0 address instruction be used in accumulator based architecture? how?
In 0-address instruction, no address is specified within an instruction along with the Opcode, so is it possible to use 0-address instruction in accumulator based architecture?

Subhadeeppathak asked in CO and Architecture Apr 23

by Subhadeeppathak

35 views

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0 answers

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Question on Pipelining
In a pipeline the maximum ideal speed-up is 5. Let the percentage of unconditional branches in a set of typical program be 5% and that of conditional branches be 10%. If 70% of the conditional branches are taken, calculate % loss of speed-up due to branch instructions. It is very difficult to understand this question and solve it. Please help.

Swarnava Bose asked in CO and Architecture Apr 7

by Swarnava Bose

6 views

2 votes

2 answers

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GATE CSE 2022 | Question: 7
Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput? $\text{DMA}$ based $\text{I/O}$ transfer Interrupt driven $\text{I/O}$ transfer Polling based $\text{I/O}$ transfer Programmed $\text{I/O}$ transfer

Arjun asked in CO and Architecture Feb 15

by Arjun

680 views

3 votes

1 answer

5

GATE CSE 2022 | Question: 14
Let $\text{WB}$ and $\text{WT}$ be two set associative cache organizations that use $\text{LRU}$ algorithm for cache block replacement. $\text{WB}$ is a write back cache and $\text{WT}$ ... cache to main memory. A read miss in $\text{WB}$ will never lead to eviction of a dirty block from $\text{WB}.$

Arjun asked in CO and Architecture Feb 15

by Arjun

1.2k views

3 votes

2 answers

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GATE CSE 2022 | Question: 23
A cache memory that has a hit rate of $0.8$ has an access latency $10 \; \text{ns}$ and miss penalty $100 \; \text{ns}.$ An optimization is done on the cache to reduce the miss rate. However, the optimization results ... (rounded off to two decimal places) needed after the optimization such that it should not increase the average memory access time is _______________.

Arjun asked in CO and Architecture Feb 15

by Arjun

1.4k views

2 votes

1 answer

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GATE CSE 2022 | Question: 44
Consider a system with $2 \;\text{KB}$ direct mapped data cache with a block size of $64 \; \text{bytes}.$ The system has a physical address space of $64 \; \text{KB}$ and a word length of $16 \; \text{bits.}$ During the execution of a program, four data ... only $\text{R}$ and $\text{S}$ reside in the cache. Every access to $\text{R}$ evicts $\text{Q}$ from the cache.

Arjun asked in CO and Architecture Feb 15

by Arjun

816 views

4 votes

2 answers

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GATE CSE 2022 | Question: 51
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ ... $\text{X}_{2}$ over $\text{X}_{1}$ in executing $\text{P}$ is _______________.

Arjun asked in CO and Architecture Feb 15

by Arjun

1.3k views

0 votes

1 answer

9

computer organization
Is non-linear pipe lining in gate 2022???

ramraj13 asked in CO and Architecture Jan 20

116 views

0 votes

1 answer

10

General Doubt
Can each operand have a separate mode in a double operand instruction?

Dheeraj Varma asked in CO and Architecture Jan 16

by Dheeraj Varma

127 views

0 votes

0 answers

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GeeksForGeeks AIM 2 - instruction format
Assume that the control memory is 32 bit wide. The micro-instruction format is divided into 3 fields. A micro operation field of 14 bits specifies the micro-operations to be performed. An address selection field specifies a condition based ... . How many bits are in address selection field, address field and the size of control memory in words respectively?

atulcse asked in CO and Architecture Jan 15

137 views

0 votes

2 answers

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made easy test series - instruction format
Consider a hypothetical CPU which supports 16-bit instruction, 64 registers and 1 KB memory space. If there exist 12 2-address instructions which use register references and 12 1-address memory reference instructions then how many 0-address instructions are possible?

atulcse asked in CO and Architecture Jan 13

151 views

0 votes

2 answers

13

Self doubt Pipelining
Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops: while(i<=1) {I1,I2,I3,I4} where i=0. Time (ns) taken by the instruction I1 to I4 for stages S1 to S5 are given below: S1 S2 S3 S4 S5 I1 1 1 2 1 1 I2 1 2 1 1 1 I3 1 2 2 1 1 I4 2 1 2 1 1 Output of I4 will be available at $_____$.

Divyanshu Shukla asked in CO and Architecture Jan 6

by Divyanshu Shukla

130 views

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0 answers

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speedup in pipelining made easy & nptel
Which approach is correct? ASSIGNMENT LINK :-- https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdf nptel assignment q-1 Caption

farmanahmed888 asked in CO and Architecture Jan 6

by farmanahmed888

114 views

0 votes

0 answers

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Test Series: COA
I need help in this one.

ramakrushna asked in CO and Architecture Dec 28, 2021

113 views

1 vote

1 answer

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Test Series: ACE
How to approach this one?

ramakrushna asked in CO and Architecture Dec 23, 2021

123 views

0 votes

0 answers

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NIELIT STA 2021
The addressing mode / s, which uses the PC instead of a general-purpose register is: Indexed with offset Relative Direct Both Indexed with offset and direct

rsansiya111 asked in CO and Architecture Dec 6, 2021

66 views

1 vote

0 answers

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CARL HAMCHER CHAPTER 1 INSTRUCTION SET ARCHITECTURE, Question 2.20
Consider the following possibilities for saving the return address of a subroutine: (a) In a processor register (b) In a memory location associated with the call, so that a different location is used when ... possibilities supports subroutine nesting and which supports subroutine recursion (that is, a subroutine that calls itself)?

Akshara Nair asked in CO and Architecture Dec 6, 2021

by Akshara Nair

105 views

1 vote

1 answer

19

NPTEL Assignment
Consider a direct-mapped cache with 64 blocks and a block size of 16 bytes. Byte address 1200 will map to block number ………… of the cache.

LRU asked in CO and Architecture Dec 4, 2021

by LRU

158 views

1 vote

1 answer

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NPTEL Assignment
Consider a two-level memory hierarchy with separate instruction and data caches in level 1, and main memory in level 2. The clock cycle time in 1 ns. The miss penalty is 20 clock cycles for both read and write. 2% of the instructions are not found ... access time (including hit detection) is 1 clock cycle. The average access time of the memory hierarchy will be . nanoseconds

LRU asked in CO and Architecture Dec 4, 2021

by LRU

111 views

1 vote

1 answer

21

NPTEL Assignment
Assume that a read request takes 50 nsec on a cache miss and 5 nsec on a cache hit. While running a program, it is observed that 80% of the processor’s read requests result in a cache hit. The average read access time is ………….. nsec.

LRU asked in CO and Architecture Dec 4, 2021

by LRU

85 views

0 votes

2 answers

22

Gate Applied Course Test Series
A 5-stage(IF,ID, EX, MEM and WB) MIPS pipeline has a register file without forwarding mechanism.How Many NOPs (or bubbles) will you need to add to make this code work correctly Lw $1, 40($6) Add $6,$2, $2 SW $6, 50($1) //$6 → M[$1+50] A)1 B) 2 C)0 D) 3

Dheeraj Varma asked in CO and Architecture Nov 25, 2021

by Dheeraj Varma

200 views

0 votes

0 answers

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Computer Architecture and Organization
A device with a data transfer rate of 20 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 10 microsecond 1. Total time required in programmed IO for 10 bytes data transfer? 2. Total ... 3. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode?

anwesha-me asked in Set Theory & Algebra Nov 22, 2021

80 views

2 votes

2 answers

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Applied Test Series
Consider the following memories with their miss rates and hit times Then the average memory access time is ______ (in ns)

LRU asked in CO and Architecture Nov 5, 2021

by LRU

220 views

1 vote

2 answers

25

Doubt regarding pipeline
Hi, I have a question like how Load/Store operation behave in pipelining, with or without operand forwarding ?

Nihal Singh asked in CO and Architecture Oct 26, 2021

354 views

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