# Recent questions tagged co-and-architecture

2 votes
1 answer
1
Match list $I$ with List $II$ ... $2\;\;\;\:\:3\;\;\;\:\:1\;\;\;\:\:4$ $1\;\;\;\:\:4\;\;\;\:\:2\;\;\;\:\:3$
0 votes
1 answer
2
Which of the following is not a form of main memory? Instruction cache Instruction register Instruction opcode Translation look-aside buffer
0 votes
1 answer
3
Which of the following is a desirable property of module? Independency Low cohesiveness High Coupling Multifunctional
0 votes
2 answers
4
A pipeline is having speed up factor as $10$ and operating with efficiency of $80\%.$ What will be the number of stages in the pipeline? $10$ $8$ $13$ None
0 votes
1 answer
5
A program $P$ calls two subprograms $P1$ and $P2.\;P1$ can fail $50\%$ time and $P2$ can fail $40\%$ times. The program $P$ can fail $50\%$ $10\%$ $60\%$ $70\%$
0 votes
1 answer
6
In time division switches if each memory access takes $100\;ns$ and one frame period is $125\;\mu s,$ then the maximum number of lines that can be supported is $625$ lines $1250$ lines $2300$ lines $318$ lines
0 votes
1 answer
7
Which level of RAID refers to disk mirroring with block striping? RAID level $1$ RAID level $2$ RAID level $0$ RAID level $3$
0 votes
1 answer
8
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$
0 votes
2 answers
9
Which level of RAID refers to disk mirroring with block striping? RAID level $1$ RAID level $2$ RAID level $0$ RAID level $3$
1 vote
3 answers
10
Which of the following is not a form of main memory? Instruction cache Instruction register Instruction opcode Translation look-aside buffer
0 votes
1 answer
11
Which of the following is a desirable property of module? Independency Low cohesiveness High Coupling Multifunctional
0 votes
1 answer
12
Match list $I$ with List $II$ ... $2\;\;\;\:\:3\;\;\;\:\:1\;\;\;\:\:4$ $1\;\;\;\:\:4\;\;\;\:\:2\;\;\;\:\:3$
0 votes
2 answers
13
A micro programmed control unit Is faster than a hardwired unit Facilitates easy implementation of a new instruction Is useful when small programs are to be run All of the above
0 votes
1 answer
14
Disk request come to a disk driver for cylinders in the order $10,22,20,2,40,6$ and $38,$ at a time when the disk drive is reading from cylinder $20$. The total seek time, if the disk arm scheduling algorithm is first-come-first-served is $900$ ms $850$ ms $360$ ms $876$ ms
1 vote
2 answers
15
A $3.5$ inch micro floppy high density disk contains the data _________ . $720 \: MB$ $1.44 \: MB$ $720 \: KB$ $1.44 \: KB$
0 votes
2 answers
16
How many address lines are needed to address each memory location in a $2048\times4$ memory chip? $10$ $11$ $8$ $12$
1 vote
2 answers
17
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data
0 votes
2 answers
18
The example of implied addressing is Stack addressing Indirect addressing Immediate addressing None of the above
0 votes
1 answer
19
Which of the following is an interrupt according to temporal relationship with system clock? Maskable interrupt Periodic interrupt Division by zero Synchronous interrupt
0 votes
2 answers
20
The general configuration of the microprogrammed control unit is given below: What are blocks B and C in the diagram respectively? Block address register and cache memory Control address register and control memory Branch register and cache memory Control address register and random access memory
0 votes
2 answers
21
Match the following ...
0 votes
1 answer
22
In $8085$ microprocessor, the digit $5$ indicates that the microprocessor needs $-5$ volts, $+5$ volts supply $+5$ volts supply only $-5$ volts supply only $5$ MHz clock
0 votes
1 answer
23
In $8085$, which of the following performs: load register pair immediate operation? LDAX rp LKLD addr LXI rp, data INX rp
0 votes
1 answer
24
Consider the following assembly language instructions: mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H add ah, 0 What is the value in $ax$ register after execution of above instructions? $0270H$ $0170H$ $01E0H$ $0370H$
0 votes
1 answer
25
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and sign flag $(SF)$ after executing $'SUB AL, BL'$ assembly language instruction, are $AL=0FH; \: CF=1; \: SF= 1$ $AL = F0H; \: CF = 0; \: SF = 0$ $AL =F1H; \: CF = 1; \: SF= 1$ $AL =1FH; \: CF=1; \:SF=1$
5 votes
2 answers
26
Consider the following statements. Daisy chaining is used to assign priorities in attending interrupts. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. In polling,the CPU periodically checks the status bits to know if any device needs its ... same time. Which of the above statements is/are TRUE? Ⅰ and Ⅱ only Ⅰ and Ⅳ only Ⅰ and Ⅲ only Ⅲ only
3 votes
6 answers
27
Consider the following data path diagram. Consider an instruction: $R0 \leftarrow R1 +R2$. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts $r$ and $w$ ... of execution of the above steps? $2,1,4,5,3$ $1,2,4,3,5$ $3,5,2,1,4$ $3,5,1,2,4$
4 votes
4 answers
28
A direct mapped cache memory of $1$ MB has a block size of $256$ bytes. The cache has an access time of $3$ ns and a hit rate of $94 \%$. During a cache miss, it takes $2$0 ns to bring the first word of a block from the main memory, while each subsequent word takes $5$ ns. The word size is $64$ bits. The average memory access time in ns (round off to $1$ decimal place) is______.
4 votes
4 answers
29
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined ... program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.
3 votes
3 answers
30
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ ... and by how many $\text{MOV}$ instructions? $\text{Case 2,2}$ $\text{Case 2,3}$ $\text{Case 1,2}$ $\text{Case 1,3}$