Recent questions tagged co-and-architecture - GATE Overflow

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2 answers

1

Stallings 6e Exercise-11.10 (page number-539) I/O Management
A 32-bit computer has two selector channels and one multiplexor channel. Each selector channel supports two magnetic disk and two magnetic tape units. The multiplexor channel has two line printers, two card readers, and ten VDT terminals ... reader 1.2 Kbytes/s VDT 1 Kbytes/s Estimate the maximum aggregate I/O transfer rate in this system

asked Jun 5 in Operating System by aditi19 Active (5k points) | 64 views

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1 answer

2

No of bits required to encode instructions
A computer has the following ISA and description - LOAD and STORE instructions capable of storing data from the accumulator to memory locations with indirect mode taking the argument as a register MOV capable of copying data from one register to another ADD ... 5 bit offset Min no of bits required to encode all the instructions above ?? Is it 4 bits ??

asked Jun 4 in CO and Architecture by s_dr_13 (167 points) | 71 views

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1 answer

3

Indirect Addressing Mode
Consider an instruction of indirect addressing mode. What are the number of memory references by the processor when instruction is a computation that requires a single operand and when it is an unconditional branch instruction respectively ?? 3,3 3,2 2,2 4,3 I believe the answer is B Correct me

asked Jun 4 in CO and Architecture by s_dr_13 (167 points) | 54 views

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2 answers

4

machine instructions and addressing modes
A digital computer has memory unit with $24$ bits word.The instruction set consists of $150$ different operations. All instructions have an operation code part and an address part. Each instruction is stored in one word of memory. $Q1$ How many bits are needed for the OP-CODE and ... $2^{16}, 2^{24}$ $2^{16},2^{24}-1$ $\textrm{None of these}$

asked May 24 in CO and Architecture by Gitika Babbar (157 points) | 138 views

+1 vote

1 answer

5

Self Doubt: CO Syllabus
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

asked May 23 in CO and Architecture by Hirak Active (3.5k points) | 90 views

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0 answers

6

PIPELINING.
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?

asked May 21 in CO and Architecture by Ritabrata Dey (53 points) | 39 views

+1 vote

1 answer

7

Made Easy Test Series:Microprogramming
A hypothetical cpu supports $300$ instructions.each instruction takes $5$ cycle to accomplish the execution. the control unit is designed using vertical programming which has $130$ control signals $,64$ flags and $12$ branch conditions .$X$ and ... register$(CDR)$ respectively.value of $X+Y$ is ______? How to work with branch condition in micro programming :(

asked May 20 in CO and Architecture by srestha Veteran (117k points) | 121 views

0 votes

1 answer

8

ISI2018-PCB-CS8
Consider a $5$ ... $\text{(in ns)}$ needed to execute the program.

asked May 12 in Operating System by akash.dinkar12 Boss (41.8k points) | 85 views

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0 answers

9

No of chips
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. No of chips required to design the memory system ______. Please provide a detailed solution.

asked May 7 in CO and Architecture by Tuhin Dutta Loyal (9.6k points) | 84 views

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0 answers

10

Branch Address
To get branch address, do we need base register value or Program Counter value?

asked Apr 17 in CO and Architecture by srestha Veteran (117k points) | 56 views

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11

#Pipeliningdoubt
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.

asked Apr 16 in CO and Architecture by Ritabrata Dey (53 points) | 28 views

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0 answers

12

Microprogrammed approach
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?

asked Apr 12 in CO and Architecture by Miny (139 points) | 11 views

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0 answers

13

Carl Hamacher: Machine Instruction and Programs-Chapter $2$
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ ... //Auto Decrement $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement

asked Apr 2 in CO and Architecture by srestha Veteran (117k points) | 63 views

0 votes

1 answer

14

Memory Access Doubt
How many memory accesses are there in this code? LOAD R1, a(RO)

asked Apr 1 in CO and Architecture by aditi19 Active (5k points) | 87 views

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0 answers

15

CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.

asked Mar 20 in CO and Architecture by Devshree Dubey Boss (13.7k points) | 34 views

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0 answers

16

Subject Topic- CO & Architecture
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB

asked Mar 18 in CO and Architecture by Doraemon Junior (661 points) | 52 views

+1 vote

0 answers

17

Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).

asked Mar 10 in CO and Architecture by s_dr_13 (167 points) | 114 views

+1 vote

1 answer

18

Pipeline
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE

asked Mar 8 in CO and Architecture by s_dr_13 (167 points) | 100 views

–1 vote

0 answers

19

GradeUp COA
If a processor has 64 address lines and 8 data lines. Then find maximum number of opcodes generated by processor. a)6 b)9 c)3 d)8

asked Feb 24 in CO and Architecture by Abhisek Tiwari 4 Active (5.2k points) | 144 views

+1 vote

1 answer

20

#ComputerArchitecture
If a computer executes a store, should it place the data into the cache or main memory? Cache only Main memory only Both cache and main memory Cache only OR Both cache and main memory

asked Feb 14 in CO and Architecture by Reshu $ingh (259 points) | 62 views

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0 answers

21

#MulticoreVSParallel
What is the difference between Multicore Processing and Parallel processing given that in both tasks/operations are performed simultaneously?

asked Feb 13 in CO and Architecture by Reshu $ingh (259 points) | 60 views

+2 votes

6 answers

22

GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

asked Feb 7 in CO and Architecture by Arjun Veteran (423k points) | 3.9k views

+3 votes

2 answers

23

GATE2019-2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF

asked Feb 7 in CO and Architecture by Arjun Veteran (423k points) | 2.7k views

+6 votes

8 answers

24

GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of road operations is ______$\times 10^6$ bytes/sec

asked Feb 7 in CO and Architecture by Arjun Veteran (423k points) | 2.5k views

+1 vote

0 answers

25

ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

asked Feb 1 in CO and Architecture by newdreamz a1-z0 Active (1.6k points) | 99 views

0 votes

1 answer

26

GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.

asked Feb 1 in CO and Architecture by Aman Janko (49 points) | 88 views

0 votes

1 answer

27

computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

asked Feb 1 in CO and Architecture by learner_geek Active (3.2k points) | 293 views

+2 votes

1 answer

28

MadeEasy Test Series 2019: CO & Architecture- Cache Memory
Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512

asked Jan 30 in CO and Architecture by Ram Swaroop Active (4.4k points) | 214 views

0 votes

1 answer

29

MadeEasy Test Series 2019: CO & Architecture - Cache Memory
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be

asked Jan 29 in CO and Architecture by Ram Swaroop Active (4.4k points) | 196 views

0 votes

0 answers

30

IEEE smallest difference
What is the minimum difference between two successive real numbers representable in this system?

asked Jan 28 in Digital Logic by Balaji Jegan Active (4.9k points) | 115 views

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