Recent questions tagged co-and-architecture

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1

Self Doubt: CO Syllabus
Is pipeline hazards there in the syllabus? And are there any previous year questions from there?

asked 14 hours ago in CO & Architecture by Hirak Active (2.1k points) | 16 views

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2

PIPELINING.
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?

asked 2 days ago in CO & Architecture by Ritabrata Dey (43 points) | 7 views

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3

Made Easy Test Series:Microprogramming
A hypothetical cpu supports $300$ instructions.each instruction takes $5$ cycle to accomplish the execution. the control unit is designed using vertical programming which has $130$ control signals $,64$ flags and $12$ branch conditions .$X$ and ... register$(CDR)$ respectively.value of $X+Y$ is ______? How to work with branch condition in micro programming :(

asked 3 days ago in CO & Architecture by srestha Veteran (114k points) | 13 views

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4

ISI2018-PCB-B8
Consider a $5$ ... $(in\ ns)$ needed to execute the program.

asked May 12 in Operating System by akash.dinkar12 Boss (40.6k points) | 17 views

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5

No of chips
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. No of chips required to design the memory system ______. Please provide a detailed solution.

asked May 7 in CO & Architecture by Tuhin Dutta Loyal (9.6k points) | 31 views

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6

Branch Address
To get branch address, do we need base register value or Program Counter value?

asked Apr 17 in CO & Architecture by srestha Veteran (114k points) | 42 views

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7

#Pipeliningdoubt
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.

asked Apr 16 in CO & Architecture by Ritabrata Dey (43 points) | 22 views

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8

Microprogrammed approach
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?

asked Apr 12 in CO & Architecture by Miny (149 points) | 5 views

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9

Carl Hamacher: Machine Instruction and Programs-Chapter $2$
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ ... //Auto Decrement $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement

asked Apr 2 in CO & Architecture by srestha Veteran (114k points) | 39 views

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1 answer

10

Memory Access Doubt
How many memory accesses are there in this code? LOAD R1, a(RO)

asked Apr 1 in CO & Architecture by aditi19 Active (3.5k points) | 62 views

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11

CPU Performance
Please can anyone help me how to measure the CPU Performance and everything related with it.

asked Mar 20 in CO & Architecture by Devshree Dubey Boss (14k points) | 21 views

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12

Subject Topic- CO & Architecture
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB

asked Mar 18 in CO & Architecture by Doraemon (203 points) | 28 views

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13

Caching
Given the following information: TLB hit rate 95%, TLB access time is 1 cycle. cache hit rate 90 %, cache access time is 1 cycle. When TLB and cache both get miss; page fault rate is 1% The TLB access and acache access are ... cycles Access to hard drive requires 50,000 cycles. Compute the average memory access latencies when the cache is physically addresses (in cycles).

asked Mar 10 in CO & Architecture by s_dr_13 (147 points) | 52 views

+1 vote

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14

Pipeline
Please cite some useful resources where lots of problems are based on pipeline,illustrating every kind of problems can be asked in GATE

asked Mar 8 in CO & Architecture by s_dr_13 (147 points) | 44 views

–1 vote

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15

GradeUp COA
If a processor has 64 address lines and 8 data lines. Then find maximum number of opcodes generated by processor. a)6 b)9 c)3 d)8

asked Feb 24 in CO & Architecture by Abhisek Tiwari 4 Active (4.7k points) | 128 views

+1 vote

1 answer

16

#ComputerArchitecture
If a computer executes a store, should it place the data into the cache or main memory? Cache only Main memory only Both cache and main memory Cache only OR Both cache and main memory

asked Feb 14 in CO & Architecture by Reshu $ingh (379 points) | 53 views

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17

#MulticoreVSParallel
What is the difference between Multicore Processing and Parallel processing given that in both tasks/operations are performed simultaneously?

asked Feb 13 in CO & Architecture by Reshu $ingh (379 points) | 56 views

+1 vote

6 answers

18

GATE2019-1
A certain processor uses a fully associative cache of size $16$ kB, The cache block size is $16$ bytes. Assume that the main memory is byte addressable and uses a $32$-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor? $24$ bits and $0$ bits $28$ bits and $4$ bits $24$ bits and $4$ bits $28$ bits and $0$ bits

asked Feb 7 in CO & Architecture by Arjun Veteran (400k points) | 3.3k views

+1 vote

2 answers

19

GATE2019-2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ address lines denoted by $A_{15}$ to $A_0$. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? C800 to CFFF CA00 to CAFF C800 to C8FF DA00 to DFFF

asked Feb 7 in CO & Architecture by Arjun Veteran (400k points) | 2.2k views

+2 votes

4 answers

20

GATE2019-45
A certain processor deploys a single-level cache. The cache block size is $8$ words and the word size is $4$ bytes. The memory system uses a $60$-MHz clock. To service a cache miss, the memory controller first takes $1$ cycle to accept the ... bandwidth for the memory system when the program running on the processor issues a series of road operations is ______$\times 10^6$ bytes/sec

asked Feb 7 in CO & Architecture by Arjun Veteran (400k points) | 2k views

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21

ME adv mock
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)

asked Feb 1 in CO & Architecture by newdreamz a1-z0 Active (1.7k points) | 59 views

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1 answer

22

GRADEUP
For a 4 bit set associative cache 10 bits are required as index to specify cache block. The main memory is of size 4G x 32. Size of cache memory is? Answer is 4096*49. Please explain the notation also.

asked Feb 1 in CO & Architecture by Aman Janko (57 points) | 49 views

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23

computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

asked Feb 1 in CO & Architecture by learner_geek Active (3.8k points) | 111 views

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1 answer

24

MadeEasy Test Series 2019: CO & Architecture- Cache Memory
Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512

asked Jan 30 in CO & Architecture by Ram Swaroop Active (2.6k points) | 129 views

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25

GB Test series: COA
Consider a 32-bit processor with 150 registers and having 76 different types of instructions. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and a thirteen-bit immediate value. Each instruction ... given in this problem and i don't think so that 32 bit processor means word size is 32 bits, right?

asked Jan 29 in CO & Architecture by chauhansunil20th Active (4.9k points) | 118 views

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1 answer

26

MadeEasy Test Series 2019: CO & Architecture - Cache Memory
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be

asked Jan 29 in CO & Architecture by Ram Swaroop Active (2.6k points) | 112 views

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27

IEEE smallest difference
What is the minimum difference between two successive real numbers representable in this system?

asked Jan 28 in Digital Logic by Balaji Jegan Loyal (5.4k points) | 91 views

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28

MadeEasy Full Length Test 2019: CO & Architecture - Cache Memory
Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order. 4,6,3,8,5,6,0,15,6,17,20,15,0,8 If LRU is used for block replacement then memory set 17 will be in the cache block ____. (PS: the given answer is 1)

asked Jan 28 in CO & Architecture by snaily16 (263 points) | 72 views

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29

Self doubt
please arrange them in increasing order of speed: Relative addressing , Absolute addressing , Register addressing , Register Indirect addressing , Indirect addressing , Base addressing , indexed addressing

asked Jan 27 in CO & Architecture by iamdeepakji (257 points) | 38 views

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30

Computer organisation cache
Why can't we have n-levels of cache ?

asked Jan 27 in CO & Architecture by Priyansh Singh (369 points) | 57 views

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