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Recent questions tagged co-and-architecture

1 vote

2 answers

1

igate test series
The instruction pipeline of RISC processor has 200 instruction in which 100 are performing addition, 25 performing division and 75 are performing multiplication, where Execution state for addition take 1 clock, multiplication take 3 clock cycles and division take 5 clock cycles. Assume pipeline ... wrong. approch totel 200 in which (100 add having 1 cc) +(25*5-1) +(75*(3-1))=354

jugnu1337 asked in CO and Architecture Sep 29

82 views

0 votes

1 answer

2

DMA
The below question is from Made Easy Test series The diagram shows single bus detached DMA configuration for a system. How many times system bus is used for single data transfer using DMA(Consider only data transfer, not command or status transfer) 1 2 3 0 Here answer ... My Doubt: In DMA their is direct data transfer from i/o to memory so system bus is accessed only once. Is this correct?

Chaitanya Kale asked in CO and Architecture Sep 24

by Chaitanya Kale

108 views

1 vote

1 answer

3

Test Series
Question : Consider a Device which operates with 20 MBPS operating speed.The device is operating on Programmed control mode of I/O and it has to transfer data of 20 B from it the data is transferred byte wise .Size of status register is 2 Bytes.total time needed to perform the data transfer is --------(microseconds)

lalitver10 asked in CO and Architecture Sep 16

58 views

0 votes

1 answer

4

#Exam
Pipe line consists of 5 stages , add instruction takes 2 cycles in EX stage, mul instruction takes 3 cycles in EX stage .. If we don't use buffer in between stages(no store and forward) , what is the time taken to execute two instruction add,mul???

RamaSivaSubrahmanyam asked in CO and Architecture Sep 14

by RamaSivaSubrahmanyam

58 views

0 votes

0 answers

5

#pipelining self-doubt
In pipielining add instruction takes 2 cycles in execution stage and mul instruction takes 4 clock cycles in the execution stage and in the remaining stages each instruction takes 1 cycle ... Now if we execute both instruction parlelly in pipelining , we get 2 stalls .. Now the question is , how do we treat those stalls? That means are they hazards or simply stalls??

RamaSivaSubrahmanyam asked in CO and Architecture Sep 12

by RamaSivaSubrahmanyam

38 views

0 votes

0 answers

6

control signal
What will be the control signal for executing the 32-bit instruction PC=PC+4? Explain each of the steps in single sentence.

Abhi patil asked in CO and Architecture Sep 12

29 views

0 votes

1 answer

7

prepladder question bank
How many 128 K × 1 RAM chips are required, and what is the size of decoder needed to give the memory capacity of 1 MB. Here memory is byte addressable.

shreyo asked in CO and Architecture Sep 12

by shreyo

75 views

0 votes

1 answer

8

#architecture
What is meant by 32 -bit and 64- bit architecture means... Does it represent wordsize or something else???

RamaSivaSubrahmanyam asked in CO and Architecture Sep 6

by RamaSivaSubrahmanyam

62 views

0 votes

1 answer

9

COA
Please Explain : “ sp content is incremented for stack going downward method and decrement for stack going upward method”

GateOverflow04 asked in CO and Architecture Sep 5

by GateOverflow04

53 views

0 votes

0 answers

10

Interrupts
If Some device wants to Transfer some bytes into memory ?? .. By using which signal the Device will contact the CPU?? READY[I am ready to transfer] Or INTR

RamaSivaSubrahmanyam asked in CO and Architecture Sep 4

by RamaSivaSubrahmanyam

27 views

0 votes

0 answers

11

Computer Organization and Architecture
Please clarify the fourth option only. My doubt: if the same word in requires repeatedly, then for the first the word will be miss and there after it is continuously in use how it can be miss.

GateOverflow04 asked in CO and Architecture Sep 3

by GateOverflow04

36 views

0 votes

0 answers

12

Computer Organization and Architecture
While calculating the average read time , why 0.9*10 + 0.1*(10+110) is not used. .i.e. why cache time is not added in miss frequency.

GateOverflow04 asked in CO and Architecture Sep 3

by GateOverflow04

34 views

1 vote

0 answers

13

Computer organization and architecture
1. In memory hierarchy the fattest memory type is cache memory next to register. So describe mapping process(transformation data from memory to cache memory)

kidussss asked in CO and Architecture Sep 1

29 views

0 votes

0 answers

14

Vishvadeep sir DPP, Instructions
Disadvantages of using 2-address instruction in place of 1-address instructions is/are? More memory required for program Larger sized instructions More number of instructions only 1 only 1 & 3 only 2 all 1,2 and 3

kanakjyoti asked in CO and Architecture Sep 1

31 views

0 votes

0 answers

15

Computer organization and architecture
1. Assume to transfer serial data we use shift register. So if we need to transfer 8 bit data to 8 bit shifter register: a) Show the content of shift register after 2 bit transferred using diagram? b) Show the overall serial transfer of all data using diagram. c) Determine how many shifting is performed to transfer all data?

kidussss asked in CO and Architecture Sep 1

21 views

0 votes

1 answer

16

Computer Architecture and Organisation
1. Assume a Bus System constructed to connect 7 registers and memory unit of 32 word length using multiplexer. So: a) How many multiplexer is needed? b) What type of multiplexer is required i.e size of multiplexer? c) Describe decoder used to select address of memory unit

kidussss asked in CO and Architecture Sep 1

34 views

0 votes

0 answers

17

Basic COA
Why ALU can’t accept operand directly from input/output devices ?

kanakjyoti asked in CO and Architecture Sep 1

27 views

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Recent questions tagged co-and-architecture