Recent questions tagged co-and-architecture

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Structure of control word in control memory
What is the structure of control word for Horizantal microprogrammed control unit? <Conditional branch bit, flag bits, contol field, next address> OR <log(Conditional branch bits), log(flag bits), contol field, next address>

jaswanth431 asked in CO and Architecture Sep 7

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How carry and zero flag bits are modified after CMP instruction is executed?
The instruction format is CMP R1, R2. How will the carry and zero flags we be modified after above instruction is executed? Case 1: R1< R2 Carry Flag = 1 Zero Flag = 0 R1= R2 Carry Flag = 0 Zero Flag = 1 R1> R2 ... 0 Zero Flag = 1 R1> R2 Carry Flag = 1 Zero Flag = 0 Which one of the above two cases is correct?

jaswanth431 asked in CO and Architecture Sep 5

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UGCNET-Dec2019-II: 9
A non-pipelined system takes $\text{30ns}$ to process a task. The same task can be processed in a four-segment pipeline with a clock cycle of $\text{10ns}$. Determine the speed up of the pipeline for $100$ tasks. $3$ $4$ $3.91$ $2.91$

soujanyareddy13 asked in Others May 12

by soujanyareddy13

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5 votes

4 answers

4

GATE CSE 2021 Set 2 | Question: 19
Consider a set-associative cache of size $\text{2KB (1KB} =2^{10}$ bytes$\text{)}$ with cache block size of $64$ bytes. Assume that the cache is byte-addressable and a $32$ -bit address is used for accessing the cache. If the width of the tag field is $22$ bits, the associativity of the cache is _________

Arjun asked in CO and Architecture Feb 18

by Arjun

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4 votes

2 answers

5

GATE CSE 2021 Set 2 | Question: 20
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ ... $\text{DMA}$, the data transfer rate of the device is __________ bits per second.

Arjun asked in CO and Architecture Feb 18

by Arjun

1.7k views

3 votes

2 answers

6

GATE CSE 2021 Set 2 | Question: 27
Assume a two-level inclusive cache hierarchy, $L1$ and $L2$, where $L2$ is the larger of the two. Consider the following statements. $S_1$: Read misses in a write through $L1$ cache do not result in writebacks of dirty lines to the $L2$ $S_2$: Write ... false $S_1$ is false and $S_2$ is true $S_1$ is true and $S_2$ is true $S_1$ is false and $S_2$ is false

Arjun asked in CO and Architecture Feb 18

by Arjun

1.3k views

8 votes

3 answers

7

GATE CSE 2021 Set 2 | Question: 53
Consider a pipelined processor with $5$ stages, $\text{Instruction Fetch} (\textsf{IF})$, $\text{Instruction Decode} \textsf{(ID)}$, $\text{Execute } \textsf{(EX)}$, $\text{Memory Access } \textsf{(MEM)}$ ... $\textit{Speedup} $ achieved in executing the given instruction sequence on the pipelined processor (rounded to $2$ decimal places) is _____________

Arjun asked in CO and Architecture Feb 18

by Arjun

2.6k views

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4 answers

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GATE CSE 2021 Set 1 | Question: 22
Consider a computer system with a byte-addressable primary memory of size $2^{32}$ bytes. Assume the computer system has a direct-mapped cache of size $\text{32 KB}$ ($\text{1 KB}$ = $2^{10}$ bytes), and each cache block is of size $64$ bytes. The size of the tag field is __________ bits.

Arjun asked in CO and Architecture Feb 18

by Arjun

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2 votes

2 answers

9

GATE CSE 2021 Set 1 | Question: 53
A five-stage pipeline has stage delays of $150, 120, 150, 160$ and $140$ nanoseconds. The registers that are used between the pipeline stages have a delay of $5$ nanoseconds each. The total time to execute $100$ independent instructions on this pipeline, assuming there are no pipeline stalls, is _______ nanoseconds.

Arjun asked in CO and Architecture Feb 18

by Arjun

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3 votes

2 answers

10

GATE CSE 2021 Set 1 | Question: 55
Consider the following instruction sequence where registers $\text{R1}, \text{R2}$ and $\text{R3}$ are general purpose and $\text{MEMORY[X]}$ denotes the content at the memory location $\text{X}.$ ... . Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________

Arjun asked in CO and Architecture Feb 18

by Arjun

1.5k views

1 vote

1 answer

11

UGCNET-Oct2020-II: 5
Consider a machine with a byte addressable main memory of $2^{16}$ bytes block size of $8$ bytes. Assume that a direct mapped cache consisting of $32$ lines used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses? $8,5,3$ $8,6,2$ $7,5,4$ $7,6,3$

jothee asked in CO and Architecture Nov 20, 2020

by jothee

864 views

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1 answer

12

UGCNET-Oct2020-II: 6
The following program is stored in memory unit of the basic computer. What is the content of the accumulator after the execution of program? (All location numbers listed below are in hexadecimal). ... $1002\text{H}$ $2011\text{H}$ $2022\text{H}$ $0215\text{H}$

jothee asked in CO and Architecture Nov 20, 2020

by jothee

1.1k views

0 votes

2 answers

13

UGCNET-Oct2020-II: 7
A non-pipeline system takes $50$ns to process a task. The same task can be processed in six-segment pipeline with a clockcycle of $10$ns. Determine approximately the speedup ratio of the pipeline for $500$ tasks. $6$ $4.95$ $5.7$ $5.5$

jothee asked in CO and Architecture Nov 20, 2020

by jothee

498 views

0 votes

1 answer

14

UGCNET-Oct2020-II: 43
Which of the following statements with respect to $K$-segment pipelining are true? Maximum speedup that a pipeline can provide is $k$ theoretically It is impossible to achieve maximum speed up $k$ in $k$-segment pipeline All segments in pipeline take same time in computation Choose the correct answer ... $(b)$ and $(c)$ only $(a)$ and $(c)$ only $(a), (b)$ and $(c)$

jothee asked in CO and Architecture Nov 20, 2020

by jothee

361 views

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0 answers

15

UGCNET-Oct2020-II: 44
Which of the following statements with respect to multiprocessor system are true? Multiprocessor system is controlled by one operating system In Multiprocessor system, multiple computers are connected by the means of communication lines Multiprocessor system is classified as multiple instruction stream and multiple ... $(b)$ only $(a)$ and $(c)$ only $(b)$ and $(c)$ only

jothee asked in CO and Architecture Nov 20, 2020

by jothee

285 views

0 votes

2 answers

16

UGCNET-Oct2020-II: 75
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$

jothee asked in CO and Architecture Nov 20, 2020

by jothee

437 views

1 vote

1 answer

17

UGCNET-Oct2020-II: 81
Given below are two statements: Statement $I$: Hardwired control unit can be optimized to produce fast mode of operation Statement $II$: Indirect addressing mode needs two memory reference to fetch operand In the light of the above statements, choose the correct ... false Statement $I$ is correct but Statement $II$ is false Statement $I$ is incorrect but Statement $II$ is true

jothee asked in CO and Architecture Nov 20, 2020

by jothee

351 views

0 votes

4 answers

18

NIELIT 2016 MAR Scientist C - Section C: 19
When a subroutine is called, then address of the instruction following the CAL instruction is stored in/on the Stack pointer Accumulator Program counter Stack

Lakshman Patel RJIT asked in CO and Architecture Apr 2, 2020

by Lakshman Patel RJIT

548 views

0 votes

1 answer

19

NIELIT 2016 MAR Scientist C - Section C: 27
The process of entering data into a storage location causes variation in its address number adds to the contents of the location is called a readout operation is destructive of previous contents

Lakshman Patel RJIT asked in CO and Architecture Apr 2, 2020

by Lakshman Patel RJIT

268 views

0 votes

1 answer

20

NIELIT 2016 MAR Scientist C - Section C: 28
Serial access memories are useful in applications where data consists of numbers short access time is required each stored word is processed differently data naturally needs to flow in and out in serial form

Lakshman Patel RJIT asked in CO and Architecture Apr 2, 2020

by Lakshman Patel RJIT

180 views

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