Recent questions tagged co-and-architecture

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1

Carl Hamacher Cache Memory
What should be correct answer to this question? In solution it's option A in Carl hamacher text book it's B ? I am confused please help

asked Jun 13 in CO & Architecture by vupadhayayx86 (47 points) | 64 views

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1 answer

2

Branch Instruction
What is meaning of offset in Branch instruction? Is this offset same as conditional instruction offset? What is meaning of offset in virtual address? Where is actual difference between these two?

asked Jun 10 in CO & Architecture by srestha Veteran (86.9k points) | 30 views

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1 answer

3

Cache memory
Consider a scenario, where there is 2 level cache in a memory hierarchy. 1)Now here if we take 1.4 memory accesses per instruction, that means if there are 100 instructions, then there will be 140 memory accesses. Here my question is how memory accesses can ... What miss rate is for L1,L2 and total in this memory hierarchy? Is it not number of misses in total number of instructions?

asked Jun 10 in CO & Architecture by srestha Veteran (86.9k points) | 39 views

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1 answer

4

practice
Q1 A RAM chip has a capacity of 1024 words of 8 bits each(1K x 8).The number of 2 x 4 decoders with enable line needed to construct a 16k x 16 RAM from 1K x 8 RAM is A 4 B. 5 C 6 D.7 Q2 The contents of flag register after execution of following pgm by 8085 microprocessor will be SUB A MVI B,(01)H DCR B HTL A (54)H B(00)H C (01)H D(45)H

asked Jun 9 in CO & Architecture by Prateek kumar Loyal (7.7k points) | 27 views

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1 answer

5

Computer Organization - Pipelining
What are stage delays in pipelining? Are they nothing but execution time required for each stage? and 'After pipelining we have to adjust the stage delays such that no stage will be waiting for another to ensure smooth pipelining (continuous flow) ' What does this statement means? Please give a brief explanation.

asked Jun 9 in CO & Architecture by Swapnil Naik (39 points) | 24 views

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6

Made Easy Test Series
The instruction pipeline of RISC processor has 200 instructions in which 100 are performing addition, 25 performing division and 75 performing multiplications, where Execution state for addition take 1 clock cycle,multiplication take 3 and division take 5. Assume pipeline has ... 5+ (75+5-1)*3 Am i doing wrong? Solution with explanation of formulae being used will be welcomed.

asked Jun 9 in CO & Architecture by Subham Nagar Junior (539 points) | 40 views

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1 answer

7

Instruction Format
Consider a computer has 64 registers and support 15 different instructions. Each instruction has 4 fields i.e. opcode, source register, destination register and immediate value of 6 bits. If each instruction in byte aligned and 50 instructions are ... answer My question is, in this question what is difference between computer has 15 instruction and memory has 50 instructions?

asked Jun 7 in CO & Architecture by srestha Veteran (86.9k points) | 43 views

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1 answer

8

How to find logical adress, physical adress,page number and offset

asked Jun 5 in Theory of Computation by Kxlpa (7 points) | 27 views

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9

self doubt(carl hamacher,chapter1)
Quantify the effect on performance that result from the use of a cache in the case of a program that has a total of $500$ instruction including a $100$ instruction loop that is executed $25$ times.Determine the ratio of execution time without the cache to ... *24=7400$. my doubt is loop is occuring $25$ times so why there is multiplication of $24$ ??why not $25$??

asked Jun 4 in CO & Architecture by BASANT KUMAR (107 points) | 26 views

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10

Computer organization and architecture 10th edition #Problems 14.11

asked Jun 4 in CO & Architecture by Aaron (7 points) | 36 views

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11

Vectored Interrupts
Are Vectored Interrupts possible in CPU having single Interrupt Request line? How/Why not?

asked Jun 2 in CO & Architecture by Harsh Kumar (189 points) | 22 views

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1 answer

12

state exam
Program counter contains address of the Next programs to be fetched Previous programs to be fetched Previous information to be fetched Next information to be fetched

asked May 30 in CO & Architecture by VIDYADHAR SHELKE 1 (71 points) | 59 views

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13

Privileged vs Non Privileged mode
Switching from privileged to non-privileged mode requires a non-privileged instruction according to this link https://gateoverflow.in/706/gate2001-1-13 But below has been quoted in this link https://gateoverflow.in/445/gate2008-34 http://www.cs.rochester ... RFE (return from exception) instruction. Kindly clear this ... Any sort of help is appreciated ... Thanks :)

asked May 30 in Operating System by Pawan Kumar 2 Active (4.5k points) | 32 views

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2 answers

14

#CO and Architecture
There is a $5$ stage Instruction pipeline, which takes $1$ $ns$ to execute each cycle. There are $4000$ branch instructions with a delay of $2$ clock cycles and $6000$ normal instructions ( They get completed in $5$ stages). What will be the total execution ... time for execution will be $6004 + 4006 = 10010$ $ns$ Is this a correct answer and right way to solve such problem?

asked May 29 in CO & Architecture by Swapnil Naik (39 points) | 82 views

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15

Expand opcode technique
The format of a double operand instructions of a cpu consist of $4$ bit opcode and $4$ bit for source and destination.$12$ double operand instructions and $24$ single operand instructions must be implemented.Opcode field must identify the three groups ... operand instructions .what is the total no. of zero operand instructions that can be implemented? $512$ $516$ $521$ $523$

asked May 26 in CO & Architecture by Prateek Raghuvanshi Active (3.9k points) | 128 views

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1 answer

16

Self doubt regarding instruction format
As we know in register to register reference cpu ,for transfer operation we use $LOAD$ and $STORE$ instruction .Both are $2 -$address instruction ,instead of these two ,can we use $MOV$ instruction?? ,which is also $2-$address instruction used in transfer the data between memory and register.

asked May 25 in CO & Architecture by Prateek Raghuvanshi Active (3.9k points) | 39 views

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17

Avg. Access Time
When we calculate avg access time, If it is not given in question like it is Hierarchal or Simultaneous access then by default we have to take which access to calculate avg access time?

asked May 25 in CO & Architecture by jatinkumar (203 points) | 37 views

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1 answer

18

Computer organisation
If cache access time is $100ns$, main memory access time is $1000ns$ and the hit ratio is $0.9$. Find the average access time and also define hit ratio.

asked May 24 in CO & Architecture by Shivani gaikawad (181 points) | 61 views

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1 answer

19

Ugc/gate cse paper
In right shift register, right shift operation of binary $11$ gives $5.5$ $5$ $6$ $\text{none of these}$

asked May 20 in Digital Logic by Gjk (7 points) | 54 views

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1 answer

20

ace test series
Is Hardwire control system used for real time systems?

asked May 11 in CO & Architecture by Kartavya Kothari (81 points) | 44 views

+1 vote

2 answers

21

ace test series
A system has 16 bits instruction that support zero address, one address and two address instructions Assume each address field size is 5 bits it is designed for supporting ‘40’ number of two address instructions, ‘400' number of one address instructions. The maximum number of zero address instructions that can be formulated is

asked May 11 in CO & Architecture by Kartavya Kothari (81 points) | 69 views

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1 answer

22

ACE TEST SERIES
Is the statement true or false; "RISC type processor is designed with minimum number of processing registers" ?

asked May 11 in CO & Architecture by Kartavya Kothari (81 points) | 55 views

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2 answers

23

addressing modes

asked May 10 in CO & Architecture by Sanjay Sharma Boss (48.2k points) | 53 views

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0 answers

24

Cache Coherence
A system with 2 cores $C0$ and $C1$ uses Write–invalidate Snoopy cache coherency protocol with $Valid$, $Dirty$ and $Shared$ bits. A program runs on the system where $C0$ writes to $A$ and afterwards $C1$ reads from $A$. This happens for 1000 times. Find number of times system bus is used by the program..

asked May 8 in CO & Architecture by habedo007 Active (1.9k points) | 39 views

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1 answer

25

wbut 2014
instruction execution throughput increases in proportion with the number of pipeline stages ? is it true justify ?

asked May 6 in CO & Architecture by maitrey vats (7 points) | 43 views

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1 answer

26

I/O Interface
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.

asked May 4 in CO & Architecture by ankitgupta.1729 Loyal (6.1k points) | 66 views

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27

made easy psu book
The read/write line belongs to The data bus The control bus The address bus CPU bus System bus.

asked Apr 30 in CO & Architecture by shruti gupta1 (129 points) | 34 views

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28

Branch Stall
What does the Following line states:- Branch instruction aren't overlapped i.e. the instruction after the branch is not fetched till the branch instruction is executed. Say in below Question :- An instruction pipeline has Five Stages where each stage takes 2ns ... fetching the branch target the instruction which was incorrectly fetched will be in stage 4. Hence total 4 Stalls isn't it?

asked Apr 28 in CO & Architecture by Na462 Active (3.3k points) | 36 views

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1 answer

29

Addressing mode
Plz describe Which addressing mode does this following line represents and how? Index addressing mode, $X\left ( R_{1} \right )$, where $X$ is an offset represented in $2$'s complement $16$ bit representation

asked Apr 26 in CO & Architecture by srestha Veteran (86.9k points) | 68 views

+1 vote

1 answer

30

Pipeline Stall
Whenever Question is given on pipeline with branching i am confused to calculate that how many stalls will be there in the pipeline according to the constraint depicted in the pipeline. How to solve Such Questions? Like in this Question https://gateoverflow.in/683/gate2000 ... And what is meant by this line "If there are N Cycles then N-1 Stalls will be there"? Please Help

asked Apr 19 in CO & Architecture by Na462 Active (3.3k points) | 93 views

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