Recent questions tagged co-and-architecture

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1

ME-flt CO
A stack based CPU executes the instruction. Memory location 500 contain 0x88 and memory location 700 contains 0x37. The stack pointer is at 0x003F. The instructions are as follows: $I_1 -$ PUSH 500 $I_2 -$ PUSH 700 $I_ 3-$ ADD $I_4- $ POP 600 $I_5 -$ PUSH 300 ... all of its suggestions. Log in to use Ginger Limited mode $I_2: PUSH300$ Log in to use Ginger Limited mode $I_2: $PUSH300

asked 13 hours ago in CO & Architecture by shreyansh jain Active (2k points) | 16 views

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2

Zero Address instruction
In an 16 bit instruction the size of address field is 7 bits. The computer uses expanding opcode technique.It has 2, two address instructions and 250 one address instruction. How many Zero address instructions can be formulated ? 5120 15304 768 1024 0

asked 19 hours ago in CO & Architecture by Na462 Loyal (8k points) | 3 views

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3

made easy basic fLT 4
5 stage pipeline → 3,6,5,8,4 latencies(in ns).What is average CPI of non pipelined CPU when speed up achieved by to pipeline is 4 ? (ans = 1.23)

asked 20 hours ago in CO & Architecture by Satbir Active (3k points) | 9 views

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4

AppliedAi MOCK1
An I/O device transfers a data 10MB/s over a bus which is capable of sending the data at a rate 100MB/s. Consider a processor operates at 200MHZ, and it takes 100 clock cycles to handle each DMA request. Suppose 8KB blocks of data has been transferred between I/O and main memory then calculate fraction of CPU time handling of the data transfer with DMA?

asked 1 day ago in CO & Architecture by jatin khachane 1 Loyal (5.5k points) | 20 views

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5

ME test
cache B access time ?

asked 1 day ago in CO & Architecture by Learner_jai Active (2.6k points) | 18 views

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6

ACE Test-4(GCO-2)
S1 : Hardwired control unit is faster then micro-programmed control unit S2: Number if control bit required in the horizontal micro-programmed control unit is $logN$ bit for N' number of control signals. S3 : Base register ... : Memory indirect addressing mode instruction execution requires less number of clock cycles then register indirect addressing mode instruction execution.

asked 2 days ago in CO & Architecture by arya_stark Active (1.4k points) | 6 views

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7

ACE Test-4(GCO-2)
Correct Statements ??? S1 : Generally I/O mapped I/O technique is used to connect more number of I/O devices then memory mapped I/O technique. S2 : Processor generates memory read (MRD) and memory write (MWR) control signals while communication with I/ ... I/O, the valuable memory space address is wasted due to the utilization of this memory space address to the I/O devices.

asked 2 days ago in CO & Architecture by arya_stark Active (1.4k points) | 11 views

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8

ME TEST SERIES
for calculating % why it is divided by 122 ?

asked 3 days ago in CO & Architecture by newdreamz a1-z0 Active (1k points) | 14 views

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9

me_test_series
A cache memory is 30 times faster than main memory (MM) and 50% of the time cache is referred for the execution of instruction. The performance is gained by introducing this cache is ________. What I did EMAT = 0.5(M/30)+0.5(M/30+M) = 32M/60 speed up= (M)/32M/60) =60/32=1.875 answer given is 1.90-1.97 (using amdhal’s law)

asked 3 days ago in CO & Architecture by Shivam Kasat Active (1.6k points) | 55 views

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10

Self Doubt
GATE2018-50 https://gateoverflow.in/204125/gate2018-50 Why can't I do this question with $(k+(n-1))*t_p$ For PO stage: $0.40*3 + 0.35*2 + 0.25*1 = 2.15$ cycles. This is larger than all the 5 stages of the given pipeline. So applying the above formula it gives $(5+99)*2.15 =224$ cycles. why we use the expanded form of the same formula $k*t_p+(n-1)t_p$ and get answer as $219$ cycles

asked 4 days ago in CO & Architecture by Gupta731 Active (4.3k points) | 16 views

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11

Madeeasy
A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is “ inherently sequential ”, then what are the theoretically best elapsed times for this program running with 2 and 4 processors, respectively ?

asked 4 days ago in CO & Architecture by mehul vaidya Active (2.7k points) | 39 views

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12

Effective Access Time
A Computer uses two level Cache L1 and L2 and in 2000 memory references there are 320 misses in L1 and 150 misses in L2. If Miss penalty of L2 is 300 clock cycles, hit time of L1 is 1 clock cycle and hit time in L2 is 10 clock cycle .What is average memory access time ? 3.6 cycles 5.4 cycles 25.06 cycles 4.8 cycles

asked 4 days ago in CO & Architecture by Na462 Loyal (8k points) | 16 views

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13

Self doubt about LRU and Direct mapping cache
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?

asked 5 days ago in CO & Architecture by S Ram Active (1.9k points) | 10 views

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1 answer

14

ME MOCK 2: COA
which addressing mode is faster and why? indirect or relative?

asked 6 days ago in CO & Architecture by aambazinga Active (2.7k points) | 42 views

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1 answer

15

Madeeasy Test Series COA
Please Explain.

asked 6 days ago in CO & Architecture by Shubham Kumar Gupta Junior (665 points) | 47 views

+1 vote

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16

MADEEASY TEST SERIES
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size ... . The speed up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)

asked Jan 9 in CO & Architecture by Jay Bhutada 1 (93 points) | 24 views

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17

MADE EASY TEST SERIES -CO
Consider the following statements: (i) Accessing of data in a column wise fashion maintains spatial locality only when the block size is equal to the total size of the elements in the row (ii) Coherence in write through protocol never occurs even cache memory is organized in multilevel. Which of the above is true?

asked Jan 9 in CO & Architecture by Jay Bhutada 1 (93 points) | 20 views

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18

Madeeasy- Types of Dependencies
Please clarify along with the names.

asked Jan 9 in CO & Architecture by Markzuck (393 points) | 27 views

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19

How many stall cycles are caused due to each incorrect branch prediction?
The title says it all: How many stall cycles are caused due to each incorrect branch prediction? Additional details you might need: Branch is executed in execution stage of pipeline (but will love to know what happens when branch is executed in decode stage too)

asked Jan 9 in CO & Architecture by Raj Singh 1 (207 points) | 8 views

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20

DMA doubt
For word preperatioin time what i thought is the time taken to transfer the data into DMA buffer is it correct ?. Or is any buffer is available inside DMA or not or that we are directly sending the data form disk to memory having a lot of doubt coming to this topic help please @Bikram @prashant sir.

asked Jan 9 in CO & Architecture by VASU SAHU (143 points) | 10 views

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1 answer

21

CO DOUBT
Certain CPU uses expanding op-code . It has 16 bit instructions with 6-bit addresses . It has maximum 192 one-address Instructions. Then number of 2-addresses instructions are supported by the system is __________________

asked Jan 8 in CO & Architecture by Magma Boss (12.7k points) | 50 views

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22

Calculate number of times Zero Flag is Reset
I am getting 37.

asked Jan 8 in CO & Architecture by Shubhanshu Boss (17.8k points) | 18 views

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23

What is mean by "Index Value" in Indexed Addressing Mode?
If someone mentioned "index value" in indexed addressing mode then which value is it referring; the value of index register or the constant value? It should be value of index register, isn't it? But from the given snippet it seems that they are referring constant value Please clarify Thank You

asked Jan 8 in CO & Architecture by newbie (59 points) | 22 views

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24

GATE 2019 2-way set associative
plz explain …..??

asked Jan 7 in Operating System by Vikas123 (355 points) | 31 views

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1 answer

25

ME_test_series
A CPU has recorded 450 memory references. The CPU has been organized into 2-level of cache memory L1 and L2 . There are 50 misses and 25 misses in L1 and L2 respectively. The miss penalty from L2 cache to memory is 60 cycles and hit time of L2 cache is 30 cycles. What is the average stall (in cycles) per instruction.? 20 40 80 32

asked Jan 7 in CO & Architecture by Shivam Kasat Active (1.6k points) | 43 views

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26

Percentage of CPU used in DMA burst mode
Wikipedia says this about DMA burst mode (https://en.wikipedia.org/wiki/Direct_memory_access#Burst_mode) In burst mode, an entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by ... . So should we consider this full duration as CPU consumed or just (bus grant time + bus release time)?

asked Jan 7 in CO & Architecture by Raj Singh 1 (207 points) | 8 views

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27

Percentage CPU consumed in load
𝗪𝗶𝗸𝗶𝗽𝗲𝗱𝗶𝗮 𝘀𝗮𝘆𝘀 𝘁𝗵𝗶𝘀 𝗮𝗯𝗼𝘂𝘁 𝗗𝗠𝗔 𝗯𝘂𝗿𝘀𝘁 𝗺𝗼𝗱𝗲 (https://en.wikipedia.org/wiki/Direct_memory_access#Burst_mode) In burst mode, an entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by the CPU ... ). So should we consider this full duration as CPU consumed or just (bus grant time + bus release time)?

asked Jan 7 in Operating System by Raj Singh 1 (207 points) | 5 views

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28

Percentage CPU consumed in burst mode of DMA
𝗪𝗶𝗸𝗶𝗽𝗲𝗱𝗶𝗮 𝘀𝗮𝘆𝘀 𝘁𝗵𝗶𝘀 𝗮𝗯𝗼𝘂𝘁 𝗗𝗠𝗔 𝗯𝘂𝗿𝘀𝘁 𝗺𝗼𝗱𝗲 (𝗵𝘁𝘁𝗽𝘀://𝗲𝗻.𝘄𝗶𝗸𝗶𝗽𝗲𝗱𝗶𝗮.𝗼𝗿𝗴/𝘄𝗶𝗸𝗶/𝗗𝗶𝗿𝗲𝗰𝘁_𝗺𝗲𝗺𝗼𝗿𝘆_𝗮𝗰𝗰𝗲𝘀𝘀#𝗕𝘂𝗿𝘀𝘁_𝗺𝗼𝗱𝗲) In burst mode, an entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by ... So should we consider this full duration as CPU consumed or just (bus grant time + bus release time)?

asked Jan 7 in CO & Architecture by Raj Singh 1 (207 points) | 17 views

+1 vote

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29

Cycle stealing mode when bus width is bigger than disk buffer
I was going through this problem: Consider a disk drive with the following specifications: 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode ... empty the disk buffer. And only after 4B are there in intermediate buffer, we send it over system bus.

asked Jan 7 in CO & Architecture by Raj Singh 1 (207 points) | 22 views

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1 answer

30

Madeeasy[MOCK]

asked Jan 7 in CO & Architecture by jatin khachane 1 Loyal (5.5k points) | 33 views

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