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Recent questions tagged co-and-architecture
0
votes
1
answer
1261
Computer organisation
If cache access time is $100ns$, main memory access time is $1000ns$ and the hit ratio is $0.9$. Find the average access time and also define hit ratio.
If cache access time is $100ns$, main memory access time is $1000ns$ and the hit ratio is $0.9$. Find the average access time and also define hit ratio.
Shivani gaikawad
540
views
Shivani gaikawad
asked
May 24, 2018
CO and Architecture
co-and-architecture
cache-memory
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0
votes
1
answer
1262
Ugc/gate cse paper
In right shift register, right shift operation of binary $11$ gives $5.5$ $5$ $6$ $\text{none of these}$
In right shift register, right shift operation of binary $11$ gives$5.5$$5$$6$$\text{none of these}$
Gjk
1.1k
views
Gjk
asked
May 20, 2018
Digital Logic
co-and-architecture
shift-registers
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0
votes
1
answer
1263
Ace Test Series: CO & Architecture - Hardwired Control
Is Hardwire control system used for real time systems?
Is Hardwire control system used for real time systems?
Kartavya Kothari
271
views
Kartavya Kothari
asked
May 11, 2018
CO and Architecture
ace-test-series
co-and-architecture
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1
votes
2
answers
1264
Ace Test Series 2019: Number Of Zero Address Instructions
A system has 16 bits instruction that support zero address, one address and two address instructions Assume each address field size is 5 bits it is designed for supporting ‘40’ number of two address instructions, ‘400' number of one address instructions. The maximum number of zero address instructions that can be formulated is
A system has 16 bits instruction that support zero address, one addressand two address instructions Assume each address field size is 5 bits itis designed for supporting ...
Kartavya Kothari
1.0k
views
Kartavya Kothari
asked
May 11, 2018
CO and Architecture
ace-test-series
co-and-architecture
instruction-format
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0
votes
1
answer
1265
Ace Test Series: CO & Architecture - RISC Properties
Is the statement true or false; "RISC type processor is designed with minimum number of processing registers" ?
Is the statement true or false; "RISC type processor is designed with minimum number of processing registers" ?
Kartavya Kothari
487
views
Kartavya Kothari
asked
May 11, 2018
CO and Architecture
ace-test-series
co-and-architecture
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2
votes
2
answers
1266
addressing modes
Sanjay Sharma
1.1k
views
Sanjay Sharma
asked
May 10, 2018
CO and Architecture
co-and-architecture
addressing-modes
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1
votes
1
answer
1267
Calculate time taken for disk access time
A disk is advertised with a seek time of 3 ms, 512 bytes per sector and 128 sectors per track. The disk rotates at 5, 200 rpm. i. Determine the average rotational delay for the disk. ii. Determine the time required to read a 4 Mbyte file. You are to assume that the file occupies sectors on adjacent tracks.
A disk is advertised with a seek time of 3 ms, 512 bytes per sector and 128 sectors per track. The disk rotates at 5, 200 rpm.i. Determine the average rotational dela...
namastayinbed
3.5k
views
namastayinbed
asked
May 8, 2018
CO and Architecture
co-and-architecture
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0
votes
1
answer
1268
Cache Coherence
A system with 2 cores $C0$ and $C1$ uses Write–invalidate Snoopy cache coherency protocol with $Valid$, $Dirty$ and $Shared$ bits. A program runs on the system where $C0$ writes to $A$ and afterwards $C1$ reads from $A$. This happens for 1000 times. Find number of times system bus is used by the program..
A system with 2 cores $C0$ and $C1$ uses Write–invalidate Snoopy cache coherency protocol with $Valid$, $Dirty$ and $Shared$ bits. A program runs on the system where $C...
habedo007
800
views
habedo007
asked
May 7, 2018
CO and Architecture
co-and-architecture
cache-coherence
cache-memory
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0
votes
1
answer
1269
WBUT 2014
instruction execution throughput increases in proportion with the number of pipeline stages ? is it true justify ?
instruction execution throughput increases in proportion with the number of pipeline stages ? is it true justify ?
maitrey vats
1.7k
views
maitrey vats
asked
May 5, 2018
CO and Architecture
co-and-architecture
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0
votes
0
answers
1270
made easy psu book
The read/write line belongs to The data bus The control bus The address bus CPU bus System bus.
The read/write line belongs toThe data busThe control busThe address busCPU busSystem bus.
shruti gupta1
938
views
shruti gupta1
asked
Apr 30, 2018
CO and Architecture
co-and-architecture
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0
votes
0
answers
1271
Branch Stall
What does the Following line states:- Branch instruction aren't overlapped i.e. the instruction after the branch is not fetched till the branch instruction is executed. Say in below Question :- An instruction pipeline has Five Stages where each stage takes ... the branch target the instruction which was incorrectly fetched will be in stage 4. Hence total 4 Stalls isn't it?
What does the Following line states:- Branch instruction aren't overlapped i.e. the instruction after the branch is not fetched till the branch instruction is executed.Sa...
Na462
671
views
Na462
asked
Apr 28, 2018
CO and Architecture
co-and-architecture
stall
pipelining
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1
votes
1
answer
1272
Addressing mode
Plz describe Which addressing mode does this following line represents and how? Index addressing mode, $X\left ( R_{1} \right )$, where $X$ is an offset represented in $2$'s complement $16$ bit representation
Plz describeWhich addressing mode does this following line represents and how?Index addressing mode, $X\left ( R_{1} \right )$, where $X$ is an offset represented in $2$'...
srestha
830
views
srestha
asked
Apr 26, 2018
CO and Architecture
addressing-modes
co-and-architecture
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2
votes
3
answers
1273
ISRO2018-6
A data driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execution. Consider the following pseudo-code: Multiply $E$ by $0.5$ to get $F$ Add $A$ and $B$ to get $E$ Add $B$ with $0.5$ to get ... sequence of execution is valid? B, C, D, A, E C, B, E, A, D A, B, C, D, E E, D, C, B, A
A data driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execut...
Arjun
3.2k
views
Arjun
asked
Apr 22, 2018
CO and Architecture
isro2018
co-and-architecture
instruction-format
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2
votes
5
answers
1274
ISRO2018-31
A byte addressable computer has a memory capacity of $2$^{m}$KB$ ($k$ bytes) and can perform $2$^{n}$ operations. An instruction involving $3$ operands and one operator needs maximum of: $3m$ bits $3m + n$ bits $m + n$ bits none of the above
A byte addressable computer has a memory capacity of $2$$^{m}$$KB$ ($k$ bytes) and can perform $2$$^{n}$ operations. An instruction involving $3$ operands and one operato...
Arjun
4.1k
views
Arjun
asked
Apr 22, 2018
CO and Architecture
isro2018
co-and-architecture
instruction-format
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3
votes
4
answers
1275
ISRO2018-34
Micro program is: the name of a source program in micro computers set of microinstructions that defines the individual operations in response to a machine-language instruction a primitive form of macros used in assembly language programming a very small segment of machine code
Micro program is:the name of a source program in micro computersset of microinstructions that defines the individual operations in response to a machine-language instruct...
Arjun
2.6k
views
Arjun
asked
Apr 22, 2018
CO and Architecture
isro2018
co-and-architecture
microprogramming
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3
votes
2
answers
1276
ISRO2018-65
Of the following, which best characterizes computers that use memory-mapped $\text{I/O}?$ The computer provides special instructions for manipulating $\text{I/O}$ ports $\text{I/O}$ ports are placed at addresses on the bus and are accessed just like ... register and call channel to perform the operation $\text{I/O}$ can be performed only when memory management hardware is turned on
Of the following, which best characterizes computers that use memory-mapped $\text{I/O}?$The computer provides special instructions for manipulating $\text{I/O}$ ports$\t...
Arjun
3.5k
views
Arjun
asked
Apr 22, 2018
CO and Architecture
isro2018
co-and-architecture
io-handling
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4
votes
4
answers
1277
ISRO2018-71
A particular parallel program computation requires $100$ sec when executed on a single processor, if $40\%$ of this computation is inherently sequential (i.e. will not benefit from additional processors), then theoretically best possible elapsed times of this program running with $2$ and $4$ ... sec and $10$ sec $30$ sec and $15$ sec $50$ sec and $25$ sec $70$ sec and $55$ sec
A particular parallel program computation requires $100$ sec when executed on a single processor, if $40\%$ of this computation is inherently sequential (i.e. will not be...
Arjun
4.9k
views
Arjun
asked
Apr 22, 2018
CO and Architecture
isro2018
co-and-architecture
parallel-programming
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3
votes
1
answer
1278
Pipeline Stall
Whenever Question is given on pipeline with branching i am confused to calculate that how many stalls will be there in the pipeline according to the constraint depicted in the pipeline. How to solve Such Questions? Like in this Question https://gateoverflow.in/683/gate2000 ... And what is meant by this line "If there are N Cycles then N-1 Stalls will be there"? Please Help
Whenever Question is given on pipeline with branching i am confused to calculate that how many stalls will be there in the pipeline according to the constraint depicted i...
Na462
2.5k
views
Na462
asked
Apr 19, 2018
CO and Architecture
co-and-architecture
stall
pipelining
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–
1
votes
0
answers
1279
Pipeline
Say Machine with 10ns click and takes 4 cycles for AlU and other operations. When we talk about the time taken by pipelined processor it is = the highest time taken by a stage + overhead We took the highest time only because we know that there is no stalling ... plz explain why then CPI is one in all cases when stalls aren't there. And plz explain the cpi for non pipelined processor .
Say Machine with 10ns click and takes 4 cycles for AlU and other operations.When we talk about the time taken by pipelined processor it is = the highest time taken by a s...
Na462
630
views
Na462
asked
Apr 19, 2018
CO and Architecture
pipelining
co-and-architecture
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–
1
votes
0
answers
1280
#sample_test_iitk
An address sequence S experiences 100 compulsory cache misses. The sequence S experiences 500 misses when it is passed through a 32 KB fully-associative cache. The sequence S experiences 1000 misses when it is passed through a 32 KB 8-way set- ... conflict misses that the sequence S experiences when it is passed through a 32 KB 8-way set-associative cache is ___________
An address sequence S experiences 100 compulsory cache misses. The sequence S experiences 500 misses when it is passed through a 32 KB fully-associative cache. The sequen...
tapzo
748
views
tapzo
asked
Apr 15, 2018
CO and Architecture
cache-memory
co-and-architecture
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–
2
votes
1
answer
1281
Addressing Mode
Adding a constant to the content of register Is it a)Immediate mode or b) Indexed mode?
Adding a constant to the content of registerIs ita)Immediate mode or b) Indexed mode?
srestha
1.3k
views
srestha
asked
Apr 15, 2018
CO and Architecture
addressing-modes
co-and-architecture
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–
0
votes
0
answers
1282
MCQs in Computer Science -Timothy Williams 5 edition
A byte addressable computer has a memory capacity of 2^m kbytes and can perform 2^n operations. An instruction involving 3 operands and one operator needs a maximum of - (a) 3m bits (b) 3m+n bits (c) m+n bits (d) none of the above. Please provide a detailed explanation ...
A byte addressable computer has a memory capacity of 2^m kbytes and can perform 2^n operations. An instruction involving 3 operands and one operator needs a maximum of -...
DEEPAK PANDEY 1
1.5k
views
DEEPAK PANDEY 1
asked
Apr 10, 2018
CO and Architecture
co-and-architecture
memory
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–
3
votes
1
answer
1283
Computer Architecture-Secondary Memory
Susheel is setting up a website. He bought a fancy new hard disk which advertises: an 8 ms average seek time. 10000 RPM or roughly 6 ms per rotation. a2 ms overhead for each disk operation. a transfer speed of 10,000,000 bytes per ... have an average size of 8000 bytes. How much time will it take on an average to read a random HTML file from the disk?
Susheel is setting up a website. He bought a fancy new hard disk which advertises:• an 8 ms average seek time.• 10000 RPM or roughly 6 ms per rotation.• a2 ms overh...
satendra
710
views
satendra
asked
Apr 10, 2018
CO and Architecture
co-and-architecture
secondary-memory
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–
0
votes
2
answers
1284
I/O organization- Hamacher
Consider a synchronous bus that operates according to the timing diagram in figure. The address transmitted by the processor appears on the bus after 4 ns. The propagation delay on the bus wires between the processor and different devices connected varies from 1 to ... . The input buffer needs 3 ns. set up time. What is maximum clock speed at which this bus can operate?
Consider a synchronous bus that operates according to the timing diagram in figure. The address transmitted by the processor appears on the bus after 4 ns. The propagatio...
srestha
2.4k
views
srestha
asked
Apr 8, 2018
CO and Architecture
co-and-architecture
dma
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–
3
votes
1
answer
1285
computer organization
Consider two cache organizations. The first one if $64 \text{ KB}$ way associative with $64\text{ byte}$ block size. The second one is of the $64 \text{ KB}$ direct mapped cache. The size of an address is $32\text{bits}$ in both ... between the hit latencies of both cache organizations (i.e. associative hit latency - direct mapped hit latency) (in nsec) is ________ .
Consider two cache organizations. The first one if $64 \text{ KB}$ way associative with $64\text{ byte}$ block size. The second one is of the $64 \text{ KB}$ direct mappe...
Prince Sindhiya
669
views
Prince Sindhiya
asked
Apr 6, 2018
CO and Architecture
co-and-architecture
cache-memory
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–
0
votes
0
answers
1286
Made easy co
Prince Sindhiya
343
views
Prince Sindhiya
asked
Apr 6, 2018
CO and Architecture
co-and-architecture
+
–
0
votes
0
answers
1287
There seem two version of carl hamacher books? which one to get?
1. Computer Organization and Embedded Systems 6e Paperback – 1 Jul 2017 2. Computer Organization Paperback 5e – 4 Nov 2011 Are these two same, because titles are different, if not which one is recommended for gate preparation? Please help.
1. Computer Organization and Embedded Systems 6e Paperback – 1 Jul 2017 2. Computer Organization Paperback 5e – 4 Nov 2011Are these two same, because titles are diffe...
cynicthnkr
515
views
cynicthnkr
asked
Apr 6, 2018
CO and Architecture
carl-hamacher
co-and-architecture
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–
0
votes
1
answer
1288
Videos for Computer Architecture
The Gate Overflow Page for CO&A(https://gatecse.in/co-architecture/) has a broken YouTube link and I could not find any other good video lectures for Computer Organization. Kindly suggest any online video lectures that would be useful for GATE preparation
The Gate Overflow Page for CO&A(https://gatecse.in/co-architecture/) has a broken YouTube link andI could not find any other good video lectures for Computer Organization...
Sivarama Subramanian
1.6k
views
Sivarama Subramanian
asked
Apr 5, 2018
CO and Architecture
co-and-architecture
video-lectures
gate-preparation
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–
0
votes
1
answer
1289
Computer Organization
Suppose we are given frequency of cpu say 2GHZ then 1/2GHZ will be the instruction cycle time rt? I.e time to complete one instruction. Is instruction cycle time and cpu cycle time the same thing?
Suppose we are given frequency of cpu say 2GHZ then 1/2GHZ will be the instruction cycle time rt? I.e time to complete one instruction. Is instruction cycle time and cpu ...
Na462
362
views
Na462
asked
Apr 1, 2018
CO and Architecture
co-and-architecture
+
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