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Recent questions tagged co-and-architecture
2
votes
2
answers
1291
pipelining
A CPU has five-stage pipeline where each stage takes $1\hspace{0.1cm}ns$, $2\hspace{0.1cm}ns$, $1.5\hspace{0.1cm} ns$, $3\hspace{0.1cm}ns$, $2.5\hspace{0.1cm} ns$. Instruction fetch happens in the first stage of the pipeline. ... one clock cycle. $30\%$ of the instructions are conditional branches. Find the average execution time of the program for $1200$ instructions is ________.
A CPU has five-stage pipeline where each stage takes $1\hspace{0.1cm}ns$, $2\hspace{0.1cm}ns$, $1.5\hspace{0.1cm} ns$, $3\hspace{0.1cm}ns$, $2.5\hspace{0.1cm} ns$. Instru...
Amit puri
1.1k
views
Amit puri
asked
Mar 29, 2018
CO and Architecture
co-and-architecture
pipelining
+
–
0
votes
1
answer
1292
Self doubt
What is the difference between Performance, Throughput ,Efficiency and speedup??
What is the difference between Performance, Throughput ,Efficiency and speedup??
debojit1990
234
views
debojit1990
asked
Mar 27, 2018
CO and Architecture
co-and-architecture
+
–
2
votes
1
answer
1293
Memory interfacing
A memory constructed with 2B words and capacity of memory $2^{18}$ bits. Number of decoder required and type of decoder if memory built using $1K\times 4$ RAM chips? (if possible give some reference and diagram)
A memory constructed with 2B words and capacity of memory $2^{18}$ bits. Number of decoder required and type of decoder if memory built using $1K\times 4$ RAM chips?(if p...
srestha
1.1k
views
srestha
asked
Mar 24, 2018
CO and Architecture
co-and-architecture
memory-interfacing
memory-management
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–
0
votes
0
answers
1294
# Co doubt
How instruction 1 is taking 2 words?????
How instruction 1 is taking 2 words?????
Sankha Narayan Bose
224
views
Sankha Narayan Bose
asked
Mar 21, 2018
CO and Architecture
co-and-architecture
+
–
0
votes
1
answer
1295
Hit Ratio and miss ratio question
In some problems we multiply only with the second part of the equation with (1-H1) component and leave the first part. Whereas in other cases we multiply with cache hit and miss. Is there any patterns for this or could be explained.
In some problems we multiply only with the second part of the equation with (1-H1) component and leave the first part. Whereas in other cases we multiply with cache hit a...
nirupama thakur
2.0k
views
nirupama thakur
asked
Mar 17, 2018
CO and Architecture
hit-ratio
cache-memory
co-and-architecture
+
–
0
votes
1
answer
1296
Shift operator
Why left shift operator does't preserve its sign bit?? I think not preserving sign bit is meaning less.
Why left shift operator does't preserve its sign bit??I think not preserving sign bit is meaning less.
Ravi prakash pandey
922
views
Ravi prakash pandey
asked
Mar 17, 2018
CO and Architecture
co-and-architecture
programming-in-c
+
–
0
votes
1
answer
1297
Pipeline Stall
I am very Confused in determining the number of stalls in a given execution. Please determine how to find out the number of stalls in the execution of the pipeline. Like In this example calculate the number of stalls:- I successfully calculated the total clock cycle but plz indicate number of ... place ? Instruction Fetch Decode Execute Write 1 1 2 2 1 2 2 3 3 2 3 3 1 1 1 4 1 1 1 1
I am very Confused in determining the number of stalls in a given execution. Please determine how to find out the number of stalls in the execution of the pipeline.Like I...
Na462
935
views
Na462
asked
Mar 16, 2018
CO and Architecture
co-and-architecture
stall
pipelining
+
–
1
votes
1
answer
1298
#1 Testbook Mock Test (COA - Cache Memory)
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in the second level cache. Assume miss penalty from the $L2$ cache to memory in $100$ cycles. The hit time of $L2$ cache is $20$ ... $10$ $5$ $15$ $\text{None of these}$
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in the second level cache. Assume miss penalty from the $L2$ cache ...
rfzahid
495
views
rfzahid
asked
Mar 15, 2018
CO and Architecture
testbook-mock-test
cache-memory
co-and-architecture
+
–
3
votes
2
answers
1299
Split Phase of Pipelining
Can anybody explain the concept of Split phase (2 stages in same clock-cycle) in Pipelining Briefly. i.e. When to use,How to use and Advantages.
Can anybody explain the concept of Split phase (2 stages in same clock-cycle) in Pipelining Briefly. i.e. When to use,How to use and Advantages.
Na462
2.0k
views
Na462
asked
Mar 12, 2018
CO and Architecture
co-and-architecture
+
–
0
votes
1
answer
1300
Pipeline
@Arjun sir In the Question :- https://gateoverflow.in/1391/gate2005-68 I have drawn like :- F D E M W F D D E M W F - D E M W Total 8 Clock cycle with operand forwarding. Why cant we Overlap stuffs means:- In first case at second instruction ... cycles. Checkout the comment of Arjun Sir:- https://gateoverflow.in/3623/gate2006-it-79 Or when to use such technique as depicted by Arjun Sir.
@Arjun sirIn the Question :- https://gateoverflow.in/1391/gate2005-68I have drawn like :- F D E M W F D D E M W F - D E M W Tot...
Na462
291
views
Na462
asked
Mar 12, 2018
CO and Architecture
pipelining
co-and-architecture
+
–
0
votes
1
answer
1301
Pipeline
In question like say "I have $4$ stages with delay $1,2,3,4 \hspace{0.1cm}ns$ and total instructions are $100$. Calculate the total time?" In such questions by default we consider a synchronous pipeline processor right? that why we apply $(k+n-1)*tp$ ??
In question like say "I have $4$ stages with delay $1,2,3,4 \hspace{0.1cm}ns$ and total instructions are $100$. Calculate the total time?"In such questions by default we ...
Na462
386
views
Na462
asked
Mar 12, 2018
CO and Architecture
co-and-architecture
pipelining
+
–
1
votes
1
answer
1302
Computer Organization
Is Horizontal and Vertical Microprogramming in our syllabus for GATE 2019 ?
Is Horizontal and Vertical Microprogramming in our syllabus for GATE 2019 ?
Na462
445
views
Na462
asked
Mar 11, 2018
GATE
co-and-architecture
+
–
0
votes
1
answer
1303
Cache Organization
Ques. In a two-level memory hierarchy, let $t_1 = 10^{-7s}$ and $t_2 = 10^{-2s}$. If ta denotes the average access time of the memory hierarchy, and if we define the access efficiency to be equal to $t_1=t_a$, then what must the hit ratio $H$ ... Why they have considered only Hit Time instead of Hit Ratio and Hit time.... and plz explain which one to use and when...
Ques. In a two-level memory hierarchy, let $t_1 = 10^{-7s}$ and $t_2 = 10^{-2s}$. If ta denotes the average accesstime of the memory hierarchy, and if we define the acces...
Na462
483
views
Na462
asked
Mar 9, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
+
–
1
votes
1
answer
1304
Cache Organization
My Doubt is simple How to know which cache organization to use hierarchical or direct cache while calculating the average access time. Like in this Question:- https://gateoverflow.in/2308/gate1993-11 Here hierarchal access is used and why? Plz help me
My Doubt is simple How to know which cache organization to use hierarchical or direct cache while calculating the averageaccess time.Like in this Question:- https://gateo...
Na462
364
views
Na462
asked
Mar 8, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
+
–
0
votes
0
answers
1305
Computer Organization and architecture
Design a optimal system with 25 processing elements and 9 shared memory modules
Design a optimal system with 25 processing elements and 9 shared memory modules
Debargha Das
348
views
Debargha Das
asked
Mar 8, 2018
CO and Architecture
co-and-architecture
+
–
1
votes
2
answers
1306
Ace Test Series: CO & Architecture - Pipelining & Hazards
pankaj_vir
527
views
pankaj_vir
asked
Mar 7, 2018
CO and Architecture
ace-test-series
co-and-architecture
pipelining
data-hazards
+
–
1
votes
1
answer
1307
Unable to understand how to take 1-Address Instruction Opcode ? I am quiet Confused.
A computer has 16-bit Instruction and 5-bit address if there are maximum 128 1-Address Instructions possible,then how many 2-Address Instructions used by Computer ?
A computer has 16-bit Instruction and 5-bit address if there are maximum 128 1-Address Instructions possible,then how many 2-Address Instructions used by Computer ?
Karan Dodwani
594
views
Karan Dodwani
asked
Mar 5, 2018
CO and Architecture
co-and-architecture
gate2018-preparation
gate2019-preparation
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–
0
votes
2
answers
1308
Test_series
can anybody solve this ? It_is_give_that MOV_R1,#5600 will take 12 bytes because opcode size(3) * word size ( 4) but my doubt is why they dont take into consideration size of operand
can anybody solve this ?It_is_give_thatMOV_R1,#5600 will take 12 bytes because opcode size(3) * word size ( 4)but my doubt is why they dont take into consideration size o...
mehul vaidya
303
views
mehul vaidya
asked
Mar 3, 2018
CO and Architecture
co-and-architecture
+
–
0
votes
1
answer
1309
Cache-Memory
If it takes 50ns to search associative registers and also about 100ns to get access to main memory then find out the % of slowdown in memory access time?(Given hit ratio 90%)- A)60 B)75 C)20 D)90
If it takes 50ns to search associative registers and also about 100ns to get access to main memory then find out the % of slowdown in memory access time?(Given hit ratio ...
satendra
1.3k
views
satendra
asked
Mar 3, 2018
CO and Architecture
cache-memory
co-and-architecture
+
–
0
votes
2
answers
1310
Uttrakhand Asst. Professor Exam-14
The number of results produced per unit time by machine is called Complexity Throughput Delay Stages
The number of results produced per unit time by machine is calledComplexityThroughputDelayStages
gatecse
200
views
gatecse
asked
Mar 2, 2018
Unknown Category
uttarakhand-asst-prof-2018
co-and-architecture
+
–
0
votes
1
answer
1311
gateos
Suppose you have a computer system with a $48-bi$t logical address, page size of $16K$ and $4 bytes$ per page table entry. If we have a $48MB$ program such that the entire program and all necessary page tables are in memory. How much memory is used by program, including its page tables?
Suppose you have a computer system with a $48-bi$t logical address, page size of $16K$ and $4 bytes$ per page table entry. If we have a $48MB$ program such that the entir...
Anshu Singh Suryavan
896
views
Anshu Singh Suryavan
asked
Feb 28, 2018
Operating System
co-and-architecture
+
–
66
votes
7
answers
1312
GATE CSE 2018 | Question: 51
A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{- byte}$ instruction format. There are four categories of ... $\text{(1F)}.$ The maximum value of $\text{N}$ is _________.
A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{...
gatecse
24.3k
views
gatecse
asked
Feb 14, 2018
CO and Architecture
gatecse-2018
co-and-architecture
machine-instruction
instruction-format
numerical-answers
2-marks
+
–
60
votes
8
answers
1313
GATE CSE 2018 | Question: 50
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch $(IF)$, Instruction Decode $(ID)$, Operand Fetch $(OF)$, Perform Operation $(PO)$ and Writeback $(WB)$, The $IF$, $ID$, $OF$ and $WB$ ... no data hazards and no control hazards. The number of clock cycles required for completion of execution of the sequence of instruction is _____.
The instruction pipeline of a RISC processor has the following stages: Instruction Fetch $(IF)$, Instruction Decode $(ID)$, Operand Fetch $(OF)$, Perform Operation $(PO)$...
gatecse
23.9k
views
gatecse
asked
Feb 14, 2018
CO and Architecture
gatecse-2018
co-and-architecture
pipelining
numerical-answers
2-marks
+
–
45
votes
9
answers
1314
GATE CSE 2018 | Question: 34
The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache block is $2^M$ words. For a $K$-way set-associative cache memory, the length (in number of bits) of the tag field is $P-N- \log_2K$ $P-N+ \log_2 K$ $P-N-M-W- \log_2 K$ $P-N-M-W+ \log_2 K$
The size of the physical address space of a processor is $2^P$ bytes. The word length is $2^W$ bytes. The capacity of cache memory is $2^N$ bytes. The size of each cache ...
gatecse
12.0k
views
gatecse
asked
Feb 14, 2018
CO and Architecture
gatecse-2018
co-and-architecture
cache-memory
normal
2-marks
+
–
46
votes
3
answers
1315
GATE CSE 2018 | Question: 23
A $32\text{-bit}$ wide main memory unit with a capacity of $1\;\textsf{GB}$ is built using $256\textsf{M} \times 4\text{-bit}$ DRAM chips. The number of rows of memory cells in the DRAM chip is $2^{14}$. The ... The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________.
A $32\text{-bit}$ wide main memory unit with a capacity of $1\;\textsf{GB}$ is built using $256\textsf{M} \times 4\text{-bit}$ DRAM chips. The number of rows of memory ce...
gatecse
25.8k
views
gatecse
asked
Feb 14, 2018
CO and Architecture
gatecse-2018
co-and-architecture
memory-interfacing
normal
numerical-answers
1-mark
+
–
21
votes
7
answers
1316
GATE CSE 2018 | Question: 5
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III
Consider the following processor design characteristics:Register-to-register arithmetic operations onlyFixed-length instruction formatHardwired control unitWhich of the c...
gatecse
12.1k
views
gatecse
asked
Feb 14, 2018
CO and Architecture
gatecse-2018
co-and-architecture
cisc-risc-architecture
easy
1-mark
+
–
0
votes
2
answers
1317
gate 2018
consider the computer system with two byte instruction and has $16$ instruction registers and $64$ floating point registers. type 1 type 2 type 3 type 4 has N instructions requiring 1 floating point register each what is the value of N?
consider the computer system with two byte instruction and has $16$ instruction registers and $64$ floating point registers.type 1type 2type 3type 4 has N instructions re...
akshayakrant
853
views
akshayakrant
asked
Feb 4, 2018
CO and Architecture
co-and-architecture
+
–
1
votes
1
answer
1318
gateforum test series
isn't the answer is directly speedup = number of stages * efficiency please confirm
isn't the answer is directly speedup = number of stages * efficiencyplease confirm
charul
295
views
charul
asked
Feb 1, 2018
CO and Architecture
gateforum-test-series
co-and-architecture
+
–
0
votes
1
answer
1319
Gfg Mock test 1
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 17 ... . If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is ________ .
Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction ...
Utsav09
591
views
Utsav09
asked
Feb 1, 2018
CO and Architecture
co-and-architecture
pipelining
+
–
0
votes
1
answer
1320
MadeEasy Test Series: CO & Architecture - Cache Memory
Assume that for a certain processor, main memory access time is 100 nanoseconds and cache memory access time is 20 nanoseconds. Suppose while running a program, it was observed that 25% of the processor’s requests result in a cache miss. What is the average access time in nanoseconds? A) 75 B) 80 C) 40 D) 45
Assume that for a certain processor, main memory access time is 100 nanoseconds and cache memory access time is 20 nanoseconds. Suppose while running a program, it was ob...
khedkar devidas
277
views
khedkar devidas
asked
Jan 30, 2018
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
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