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Recent questions tagged co-and-architecture
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1321
ME TEST
The format of double operand instruction of a CPU consist of $5$ bits opcode and $6$ bits for source and destination. $26$ double operand instructions and $184$ single operand instructions must be implemented. What will be the total number of zero operand instructions can be implemented? How to solve such questions? I always get confused.
The format of double operand instruction of a CPU consist of $5$ bits opcode and $6$ bits for source and destination. $26$ double operand instructions and $184$ single op...
ankit_thawal
266
views
ankit_thawal
asked
Jan 30, 2018
CO and Architecture
co-and-architecture
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0
votes
0
answers
1322
computer organization
A computer has a cache, main memory and a disk used for virtual memory. If reference word is in cache $15\hspace{0.1cm} ns$ are required to access it. If it is in main memory but not in cache, $50\hspace{0.1cm} nsec$ are needed to load it into cache and ... on this system will be____________. (in μsec) is this correct equation .$90*15 + .10*(.50*(50+15)+.50*(10000000+50))$
A computer has a cache, main memory and a disk used for virtual memory. If reference word is in cache $15\hspace{0.1cm} ns$ are required to access it. If it is in main me...
Kaluti
210
views
Kaluti
asked
Jan 30, 2018
CO and Architecture
co-and-architecture
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–
0
votes
1
answer
1323
Gate_2018_Mock_Paper
What is mean here by word size=4 Byte ? Please solve the below question
What is mean here by word size=4 Byte ?Please solve the below question
Harikesh Kumar
406
views
Harikesh Kumar
asked
Jan 30, 2018
CO and Architecture
co-and-architecture
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–
1
votes
0
answers
1324
MadeEasy Test Series: CO & Architecture - Addressing Modes
A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directory entry contains, in addition to tag address, 1 valid bit and 1 matching bit. The size of ... above till here: TAG Size = $23\ bits * 2^{14}$ = $3\ bytes * 2^{14}$ = 48 KB
A computer has 256 KB, 8 way set associative write back data cache with block size 16 bytes. The processor send 36 bit addresses to the cache controller. Each tag directo...
Rishabh Gupta 2
983
views
Rishabh Gupta 2
asked
Jan 30, 2018
CO and Architecture
made-easy-test-series
cache-memory
co-and-architecture
addressing-modes
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–
0
votes
1
answer
1325
Probability and COA
Can someone explain me these two qns and solution :)
Can someone explain me these two qns and solution :)
gauravkc
405
views
gauravkc
asked
Jan 29, 2018
Probability
co-and-architecture
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0
votes
0
answers
1326
TLB-Memory-access-live-test-2
A system uses $2$ level paging scheme. A regular memory access takes $100$ ns and servicing a page fault takes $10$ millisecond. An avg instruction takes $100$ ns of CPU time and $2$ memory access. The TLB hit ratio is $95\%$. and page fault is $1$ in every $10,000$ memory access. Avg instruction execution time.$?$ Options given are $1300$ns $1150$ns $2320$ns $1275$ns
A system uses $2$ level paging scheme.A regular memory access takes $100$ ns and servicing a page fault takes $10$ millisecond.An avg instruction takes $100$ ns of CPU ti...
Inspiron
501
views
Inspiron
asked
Jan 29, 2018
CO and Architecture
effective-memory-access
co-and-architecture
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1
votes
0
answers
1327
Ace Test Series: CO & Architecture - Cache Memory Tag
Manis
382
views
Manis
asked
Jan 28, 2018
CO and Architecture
ace-test-series
co-and-architecture
cache-memory
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2
votes
1
answer
1328
Ace test series: CO & Architecture - Cache Memory Tag
ashish pal
440
views
ashish pal
asked
Jan 28, 2018
CO and Architecture
ace-test-series
co-and-architecture
cache-memory
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–
7
votes
1
answer
1329
Cache memory - Find Cache size ( given K, line size, tag memory, physical address space )
Consider a physically tagged, word addressable, 16-way set associative cache with the line size of 128 Bytes. What is the size of cache if tag memory size is 2Kbits. Further assume that physical address space is 24 bits and word size is 4 Bytes. a. 1 KB b. 2 KB c. 3 KB d. 4 KB
Consider a physically tagged, word addressable, 16-way set associative cache with the line size of 128 Bytes. What is the size of cache if tag memory size is 2Kbits. Furt...
Tuhin Dutta
1.9k
views
Tuhin Dutta
asked
Jan 27, 2018
CO and Architecture
co-and-architecture
cache-memory
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3
votes
0
answers
1330
Control-memory
Assume that the control memory is 32 bit wide. The micro-instruction format is divided into 3 fields. A micro operation field of 14 bits specifies the micro-operations to be performed. An address selection field specifies a condition based on flags and ... solution they are assuming all 14 bits as address whereas in question its mentioned . Any help would be appreciated thank you !
Assume that the control memory is 32 bit wide. The micro-instruction format is divided into 3 fields. A micro operation field of 14 bits specifies the micro-operations to...
Inspiron
3.3k
views
Inspiron
asked
Jan 27, 2018
CO and Architecture
co-and-architecture
control-memory
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1
votes
0
answers
1331
TEST SERIES CO
Ismail
245
views
Ismail
asked
Jan 27, 2018
CO and Architecture
co-and-architecture
cache-memory
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–
2
votes
0
answers
1332
MadeEasy Test Series 2018: CO & Architecture - Cache Memory
Answer given is 3. But I think the answer should be 4 conflict miss will occur in 100,108,114,1C7,128,1B5,100,108,1C7 (highlighted misses) My approach: I found that no. of sets is 2 and only 1 bit will be sufficient. ... areas. Need your help if I am doing wrong somewhere or may be answer is incorrect. Thanks in advance for your help.
Answer given is 3. But I think the answer should be 4 conflict miss will occur in 100,108,114,1C7,128,1B5,100,108,1C7 (highlighted misses)My approach: I found that no. o...
nishitshah
335
views
nishitshah
asked
Jan 26, 2018
CO and Architecture
cache-memory
co-and-architecture
made-easy-test-series
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–
1
votes
0
answers
1333
Mulitsubject CO and CN
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 2 KB and the threshold at the start of first transmission is 24 KB. Assume that 3 duplicate ACK are received during the 5th ... WB and ID stage i.e. in one half of cycle doing WB and in another half doing ID. Given answer is 14.
Consider an instance of TCP’s Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 2 KB and the threshol...
Shubhanshu
696
views
Shubhanshu
asked
Jan 26, 2018
Programming in C
computer-networks
sliding-window
co-and-architecture
pipelining
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–
3
votes
0
answers
1334
MultiSubject (CO, DIgital, DS)
A 4-bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 100 ns, the maximum clock frequency that can be used is equal to: Ans 2.5MHz. I think it should be $\frac{1}{16*10^{-7}} = 0.625MHz$ ... minimum number of comparisons that will be needed in the worst case by the optimal algorithm for doing this is Ans = 840 I am getting 860.
A 4-bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 100 ns,the maximum clock frequency that can be used is equal to:Ans 2.5MHz.I t...
Shubhanshu
1.7k
views
Shubhanshu
asked
Jan 25, 2018
Programming in C
data-structures
co-and-architecture
binary-tree
digital-logic
ripple-counter-operation
merge-sort
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1
votes
0
answers
1335
Cache
What is Virtually Indexed Virtually Tagged (VIVT)? Similarly we have VIPT, PIPT, PIVT (P is physical) Short explanation or reference pls :)
What is Virtually Indexed Virtually Tagged (VIVT)?Similarly we have VIPT, PIPT, PIVT (P is physical)Short explanation or reference pls :)
gauravkc
278
views
gauravkc
asked
Jan 25, 2018
Operating System
cache-memory
co-and-architecture
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2
votes
0
answers
1336
Computer organization speed up
Consider a hypothetical system,which is used in application where program refers integers units and floats units.Floating units are enhanced so that they run 2 times faster,but only 90% instructions are floating point type.What isn the over all performance gain?
Consider a hypothetical system,which is used in application where program refers integers units and floats units.Floating units are enhanced so that they run 2 times fast...
rahul sharma 5
605
views
rahul sharma 5
asked
Jan 25, 2018
CO and Architecture
co-and-architecture
speedup
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–
1
votes
0
answers
1337
Cache and Main Memory
Consider a single-level cache with an access time of 1.8ns, a line size of 16 bytes, and a hit ratio of 0.85. Main memory uses a block transfer capability that has a first word (4 bytes) access time of 40 ns and an access time of 5 ns for each ... (first 4 bytes) + 75 (remaining 60 bytes) How it get 75ns accesstime ? After 4 words each words is accessed at 5ns Access time.?
Consider a single-level cache with an access time of 1.8ns, a line size of 16 bytes, and a hit ratio of 0.85. Main memory uses a block transfer capability that has a firs...
Madhi Varman
481
views
Madhi Varman
asked
Jan 25, 2018
CO and Architecture
co-and-architecture
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–
4
votes
2
answers
1338
CO Addressing
A computer has 32 bit instruction and 12 bit address . If there are 250 two address instructions , the no. of one -address instructions can be ..... Plz formulate a generic solution for this with diagram .
A computer has 32 bit instruction and 12 bit address . If there are 250 two address instructions , the no. of one -address instructions can be .....Plz formulate a generi...
dragonball
5.2k
views
dragonball
asked
Jan 25, 2018
CO and Architecture
co-and-architecture
addressing-modes
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–
2
votes
0
answers
1339
Computer organization:- Memory size
Consider a processor which contains 32 time multiplexed pins used to carry address and data, and 8 address pins carry address only.Then calculate the size of memory and number of address bits needed to address memory?
Consider a processor which contains 32 time multiplexed pins used to carry address and data, and 8 address pins carry address only.Then calculate the size of memory and n...
rahul sharma 5
443
views
rahul sharma 5
asked
Jan 24, 2018
CO and Architecture
co-and-architecture
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–
3
votes
2
answers
1340
Pipeline hazards
R1 <- R1+R2 R2 <- R3*R4 R3 <- R4-R1 R2 <- R3+R4 Can someone point out hazards. Thanks :)
R1 <- R1+R2R2 <- R3*R4R3 <- R4-R1R2 <- R3+R4Can someone point out hazards. Thanks :)
gauravkc
1.2k
views
gauravkc
asked
Jan 24, 2018
CO and Architecture
pipelining
hazards
co-and-architecture
data-hazards
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–
3
votes
0
answers
1341
DMA Cycle Stealing Mode
In the last step shouldn't it be (Y/X) and not (Y/X+Y) since its Cycle Stealing mode?
In the last step shouldn't it be (Y/X) and not (Y/X+Y) since its Cycle Stealing mode?
vishal chugh
1.3k
views
vishal chugh
asked
Jan 24, 2018
CO and Architecture
dma
co-and-architecture
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–
3
votes
1
answer
1342
Cache Average access time
So as we know there are 2 different approaches for cache.. Sequential and the Hierarchical. Exactly which formula should I use when only access times and hit ratio is mentioned in case of 2 level memory system..? It would be great if someone explains how to approach questions related to average access time.
So as we know there are 2 different approaches for cache..Sequential and the Hierarchical. Exactly which formula should I use when only access times and hit ratio is ment...
Abhijit Howal
665
views
Abhijit Howal
asked
Jan 22, 2018
CO and Architecture
cache-memory
co-and-architecture
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–
1
votes
1
answer
1343
Ace Test Series: CO & Architecture - Cache Memory Tag
The answer was given as 22 bits. I didn't get their method of solving this question. Kindly explain the solution. I even doubt their answer.
The answer was given as 22 bits. I didn't get their method of solving this question. Kindly explain the solution. I even doubt their answer.
Asim Abbas
333
views
Asim Abbas
asked
Jan 22, 2018
CO and Architecture
cache-memory
ace-test-series
co-and-architecture
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–
3
votes
0
answers
1344
Caches.
44 ns?
44 ns?
Inspiron
196
views
Inspiron
asked
Jan 21, 2018
CO and Architecture
co-and-architecture
+
–
2
votes
0
answers
1345
Register evaluation
26?
26?
Inspiron
151
views
Inspiron
asked
Jan 21, 2018
CO and Architecture
co-and-architecture
+
–
3
votes
2
answers
1346
#Conflict Misses
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main memory addresses (in hexadecimal). The conflict miss if 2-way set associative LRU cache is used is ________. 100, 108, 114, 1C7, 128, 1B5, 100, 108, 1C7
A byte addressable computer has a small data cache capable of holding 16 32-bit words. Each cache block consist of four 32 bits words. For the following sequence of main ...
VS
1.1k
views
VS
asked
Jan 20, 2018
CO and Architecture
cache-memory
co-and-architecture
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–
1
votes
1
answer
1347
Ace Test Series: CO & Architecture - DMA And Bus Architecture
Answer is D please explain
Answer is Dplease explain
ashish pal
558
views
ashish pal
asked
Jan 20, 2018
CO and Architecture
ace-test-series
co-and-architecture
dma
+
–
2
votes
1
answer
1348
MadeEasy Test Series 2018: CO & Architecture - Pipelining
The following sequence of instruction is executed in a basic 5 stage pipelined processor (IF, ID, EX, MA and WB). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction ... cycle. What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding?
The following sequence of instruction is executed in a basic 5 stage pipelined processor (IF, ID, EX, MA and WB). Assume that data dependency present in the program is re...
Tuhin Dutta
654
views
Tuhin Dutta
asked
Jan 18, 2018
CO and Architecture
co-and-architecture
pipelining
made-easy-test-series
+
–
1
votes
1
answer
1349
Memory access time
Suppose the time taken to write in cache is tc and time to write in main memory is tm. If write back policy is used, only the main memory is written and time taken is tm. But if write through is used, are the main memory and cache updated simultaneously (time taken would be tm) or serially (time taken would be tc + tm)?
Suppose the time taken to write in cache is tc and time to write in main memory is tm. If write back policy is used, only the main memory is written and time taken is tm....
Sumaiya23
715
views
Sumaiya23
asked
Jan 18, 2018
CO and Architecture
co-and-architecture
effective-memory-access
cache-memory
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–
2
votes
2
answers
1350
MadeEasy Test Series 2018: CO & Architecture - Pipelining
my doubt : In case of branch instruction the address is available at 4th stage. Does it mean fetching of next instruction start from 4th stage or the 5th stage? I think it should be 4 but made easy has solved it by taking IF for next instruction at 5th stage. please help.
my doubt : In case of branch instruction the address is available at 4th stage. Does it mean fetching of next instruction start from 4th stage or the 5th stage?I think it...
Abhishek Kumar Singh
334
views
Abhishek Kumar Singh
asked
Jan 18, 2018
CO and Architecture
co-and-architecture
pipelining
made-easy-test-series
+
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