Recent questions tagged co-and-architecture / GATE Overflow for GATE CSE

1 votes

1 answer

1411

zero address instruction
In a 16 bit computer instruction format, the size of address field is 5 bits. The computer uses expanding opcode technique. It has two 2-address instructions and 1024 one address instruction. How many zeroaddress instruction can be formulated?

In a 16 bit computer instruction format, the size of address field is 5 bits. The computer uses expanding opcode technique. It has two 2-address instructions and 1024 one...

Jaspreet Kaur Bains

398 views

Jaspreet Kaur Bains asked Jan 2, 2018

1 votes

1 answer

1412

The L2 and L3 cache memories are divided into a blocks of 5 words.
Suppose there is a system which has 3 levels of cache i.e L1, L2 and L3. The access times of L1, L2 and L3 cache memories are 100 ns/word, 150 ns/word, and 250 ns/word respectively. The L2 and L3 cache memories are divided ... are 80% and 90% respectively. What is the average access time? A. 103ns B. 108ns C. 220ns D. 112ns

Suppose there is a system which has 3 levels of cache i.e L1, L2 and L3. The access times of L1, L2 and L3 cache memories are 100 ns/word, 150 ns/word, and 250 ns/word re...

Hemant Parihar

1.2k views

Hemant Parihar asked Jan 2, 2018

1 votes

1 answer

1413

Self Doubt: CO & Architecture - Microprogramming
Difference between Horizontal Microprogramming and Vertical Microprogramming Plz explain in detail for GATE point of view only.

Difference between Horizontal Microprogramming and Vertical Microprogramming Plz explain in detail for GATE point of view only.

dragonball

4.0k views

dragonball asked Jan 1, 2018

2 votes

1 answer

1414

pipelining
Assume branch instructions occur 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forwarding, the load delay slot is one cycle and can be filled 60% of the time with ... instructions are loads and 30% of these introduce load delay hazards. What is the New CPI due to load delay slots and branch hazards?

Assume branch instructions occur 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forward...

Parshu gate

388 views

Parshu gate asked Jan 1, 2018

1 votes

0 answers

1415

Previous Year Question : Can any one explain below method
https://gateoverflow.in/?qa=blob&qa_blobid=11484316347737079122 Reference this question https://gateoverflow.in/1314/gate2009-28 can any one tell how this matrix obtain .?

https://gateoverflow.in/?qa=blob&qa_blobid=11484316347737079122Reference this question https://gateoverflow.in/1314/gate2009-28can any one tell how this matrix obtain .?

hem chandra joshi

203 views

hem chandra joshi asked Jan 1, 2018

1 votes

0 answers

1416

Does Load and Store instruction Require ALU Operation ?
Does Load and Store instruction Require ALU Operation ?

Does Load and Store instruction Require ALU Operation ?

Anup patel

374 views

Anup patel asked Jan 1, 2018

4 votes

1 answer

1417

Associative mapping in cache
If main memory $=128 \ KB$ and cache memory is of $2KB$ with $16B$ lines .and uses associative mapping . What would be the # of bits used for Tag for each block?

If main memory $=128 \ KB$ and cache memory is of $2KB$ with $16B$ lines .and uses associative mapping .What would be the # of bits used for Tag for each block?

saxena0612

1.8k views

saxena0612 asked Jan 1, 2018

1 votes

1 answer

1418

Average Access Time In CO
Compute the average access time for a machine with 80%cache hit ratio.The cache access time and memory access time are 20 ns and 200 ns . DOUBT:: While solving these type of questions which type of model we need to follow case 1 or case 2 ? PS: Circle is a processor :P

Compute the average access time for a machine with 80%cache hit ratio.The cache access time and memory access time are 20 ns and 200 ns .DOUBT:: While solving these type ...

dragonball

656 views

dragonball asked Jan 1, 2018

3 votes

2 answers

1419

MadeEasy Test Series: CO & Architecture - Speedup

Kalpataru Bose

924 views

Kalpataru Bose asked Dec 31, 2017

4 votes

1 answer

1420

Cache size
If a 16 – way set associative cache is made up of 64 bit words, 16 words per line and 8192 sets, how big is the cache in mega bytes?

If a 16 – way set associative cache is made up of 64 bit words, 16 words per line and 8192 sets, how big is the cache in mega bytes?

Anjan

4.4k views

Anjan asked Dec 31, 2017

1 votes

1 answer

1421

Doubt on associativity
Does increasing cache associativity decreases conflict misses?

Does increasing cache associativity decreases conflict misses?

Tuhin Dutta

230 views

Tuhin Dutta asked Dec 31, 2017

3 votes

1 answer

1422

MadeEasy Test Series: CO & Architecture - Cache Memory
The statement " Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value." is true or false ?

The statement " Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value." is true or false ?

ashish pal

1.9k views

ashish pal asked Dec 31, 2017

2 votes

0 answers

1423

Microprogrammed control unit
What is the difference between control signal and control word? Also, the difference between micro-operation and microinstruction.

What is the difference between control signal and control word? Also, the difference between micro-operation and microinstruction.

Injila

933 views

Injila asked Dec 29, 2017

2 votes

0 answers

1424

associative mapping
Consider 4-way set associative cache of a 64 KB organized into a 32 blocks. Main memory size is 4 GB. In the cache controller, each line in the set contain 1 valid, 1 modified and 2 replacement bits along with a tag. How much space is required in the cache controller to store the tag information (Meta data)

Consider 4-way set associative cache of a 64 KB organized into a 32 blocks. Main memory size is 4 GB. In the cache controller, each line in the set contain 1 valid, 1 mod...

Jaspreet Kaur Bains

1.6k views

Jaspreet Kaur Bains asked Dec 28, 2017

2 votes

1 answer

1425

COA-PIPELINE
An instruction pipeline consists of following 5 stages: IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MA = Memory Access and WB = Register Write Back Now consider the following code: Assume that each stage takes 1 clock cycle for ... are required to execute the code, without operand forwarding over a bypass network ________. Someone please confirm this i am getting 12

An instruction pipeline consists of following 5 stages: IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MA = Me...

junaid ahmad

954 views

junaid ahmad asked Dec 27, 2017

4 votes

1 answer

1426

MadeEasy Test Series: CO & Architecture - Expanding Opcode
How to solve this ?

How to solve this ?

Kalpataru Bose

783 views

Kalpataru Bose asked Dec 26, 2017

8 votes

4 answers

1427

Avg stall cycles per instruction
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache to memory is $100$ cycles. The hit time of $L_{2}$ cache is $20$ ... $L_{1}$ cache is $10$ cycles. If there are $2.5$ memory references per instruction. How many average stall cycle per instruction?

Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache t...

Parshu gate

4.7k views

Parshu gate asked Dec 25, 2017

0 votes

0 answers

1428

Misses in cache
Consider a cache as follows: Direct mapped 8 words total cache data size 2 words block size A sequence of memory read is performed in the order shown from the following addresses: 0 , 11 , 4 , 14 , 9 , 1 , 8 , 0 , 4 , 11. Find No of compulsory misses and conflict misses and capacity misses.

Consider a cache as follows:Direct mapped8 words total cache data size2 words block sizeA sequence of memory read is performed in the order shown from the following addr...

Anjan

907 views

Anjan asked Dec 24, 2017

2 votes

2 answers

1429

GateForum Test Series
Assume we have two dimensional array of size 100x100, each element is occupying 4 bytes and array is stored in row major order. Further assume RAM is 1MB and cache is 4KB with each size of 32 bytes: X: for(i = 0; i < 100; i++){ for(j = 0; j < ... of 2-way set associative cache, number of cache misses is(assume initially cache is empty) (A) 1250 (B) 2500 (C) 2400 (D) 2372

Assume we have two dimensional array of size 100x100, each element is occupying 4 bytes and array is stored in row major order. Further assume RAM is 1MB and cache is 4KB...

vishal chugh

792 views

vishal chugh asked Dec 24, 2017

1 votes

1 answer

1430

Comp.Architecture-2
Here $128$ block actually refers to Lines right? So it should be $8+4+7=19$ Assume memory is word addessable?Thanks!

Here $128$ block actually refers to Lines right?So it should be $8+4+7=19$ Assume memory is word addessable?Thanks!

saxena0612

221 views

saxena0612 asked Dec 24, 2017

0 votes

1 answer

1431

Comp.Architecture-3
My work: $1+0.1*5+0.05*50=4ns$ Now please give me reasoning about : missing in $L1$ i will access $L2$ and i did that now When i am missing in $L2$ isn`t this obvious that i have actually missed in $L1 $ or should i mention it by $0.05*0.1*50$ Thanks!

My work: $1+0.1*5+0.05*50=4ns$Now please give me reasoning about : missing in $L1$ i will access $L2$ and i did that now When i am missing in $L2$ isn t this obvious tha...

saxena0612

373 views

saxena0612 asked Dec 24, 2017

0 votes

0 answers

1432

#Instruction-pipeline Data hazard between two consecutive memory access instruction
Although the following instructions do not make much sense but if such case occurs, is data forwarding from MA of I1 to MA of I2 allowed? Or will it result in some stall? Please add some reference, I couldn't find any yet. I1: Load A //A<-Mem[address] I2: Store Adress2, A // Mem[Address2] <- A

Although the following instructions do not make much sense but if such case occurs, is data forwarding from MA of I1 to MA of I2 allowed? Or will it result in some stall?...

AskHerOut

473 views

AskHerOut asked Dec 22, 2017

0 votes

1 answer

1433

Test Series
A 32 bit machine processor has 32 register, each of which is 16 bit long. each instruction is specified with four field, namely operation part, immediate operand in addition to two register operands. assume that the immediate operand is signed integer in ... can be represented in immediate operand field is +4095. max number of instruction that can be permitted by this processor is.?

A 32 bit machine processor has 32 register, each of which is 16 bit long. each instruction is specified with four field, namely operation part, immediate operand in addit...

Akshay Koli 4

349 views

Akshay Koli 4 asked Dec 22, 2017

2 votes

1 answer

1434

Booth's coding in 8-bits for the decimal number -57 is: A 0-100+1000 B 0-100+100-1 C 0-1+100-10+1 D 00-10+100-1

Booth's coding in 8-bits for the decimal number -57 is: A 0-100+1000 B 0-100+100-1 C 0-1+100-10+1 D 00-10+100-1 plz explain this question

92komal

1.2k views

92komal asked Dec 20, 2017

1 votes

1 answer

1435

DMA - Data Transfer Rate
A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of 106 instructions per second. An average instruction requires six processor cycles, three of which use the memory ... or status-checking time] ? (A) 2.15 x 106 (B) 3.15 x 106 (C) 1.15 x 106 (D) 4.15 x 106

A computer consists of a CPU and an I/O device D connected to main memory M via a shared bus with a data bus width of one word (16-bits). The CPU can execute a maximum of...

ankitgupta.1729

1.4k views

ankitgupta.1729 asked Dec 20, 2017

1 votes

2 answers

1436

System Performance
Consider a system with cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these are 50% of the total instructions. If the miss penalty is 30 clock cycles and the miss rate is 4%, how much faster would the computer be if all instructions were cache hits? (A) 1 (B) 2.8 (C) 1.6 (D) 3.5

Consider a system with cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these are 50% of th...

ankitgupta.1729

1.7k views

ankitgupta.1729 asked Dec 19, 2017

3 votes

1 answer

1437

Addressing Modes
How many memory accesses required by the following instructions? SUB r1, r2, r3 MUL r1, r2, (r3) DIV r1, r2, @(r4) Suppose every instruction is one word long, as well as every address. (A) 4 (B) 6 (C) 8 (D) 9

How many memory accesses required by the following instructions?SUB r1, r2, r3MUL r1, r2, (r3)DIV r1, r2, @(r4)Suppose every instruction is one word long, as well as ever...

ankitgupta.1729

2.2k views

ankitgupta.1729 asked Dec 19, 2017

3 votes

0 answers

1438

Hamacher
7.14 A pipeline processor uses the delayed branch technique. You are asked to recommend one of the two possibilities for the design of this processor. In the first possibility, the processor has a four stage pipeline and one delay slot, and in second possibility, ... the single delay slot. For the second alternative, the compiler is able to fill the second slot 25 percent of the time.

7.14 A pipeline processor uses the delayed branch technique. You are asked to recommend one of the two possibilities for the design of this processor. In the first possi...

Tesla!

1.4k views

Tesla! asked Dec 19, 2017

2 votes

1 answer

1439

Floating point representation
If the decimal number is 3.248 x 104 ,then its equivalent floating number in IEEE 754 standard is ?

If the decimal number is 3.248 x 104 ,then its equivalent floating number in IEEE 754 standard is ?

Hitoshi

4.9k views

Hitoshi asked Dec 19, 2017

0 votes

1 answer

1440

in a cache memory if total number of sets are S then the set offset
in a cache memory if total number of sets are S then the set offset is a)2^8 b) Log S c)S^2 d) S

in a cache memory if total number of sets are S then the set offset is a)2^8 b) Log S c)S^2 d) S

Sanjay Sharma

2.5k views

Sanjay Sharma asked Dec 18, 2017

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