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Recent questions tagged co-and-architecture
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151
scientist B cpcb exam 2023. computer-science engineering. Need help to solved! Urgent!
We have a combinational block [implementing an operation] that can be divided into 3 partitions as 70ps, 40ps and 65ps. The system throughput can be improved using pipelining. Assuming that we are given one ... is 20 ps, the maximum achievable throughput (in GOPS, rounded to 2 decimal places) is _____________.
We have a combinational block [implementing an operation] that can be divided into 3 partitions as 70ps, 40ps and 65ps. The system throughput can be improved using pipel...
Jai Singh
366
views
Jai Singh
asked
Jun 22, 2023
CO and Architecture
pipelining
co-and-architecture
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0
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1
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152
Topic: Hit Ratio
The access time of a main memory is 800 ns and cache memory access time is 70 ns. The ratio of read and write requests is 7:3. The hit ratio for read access only is 80%. Calculate the hit ratio for all the memory requests (i.e. both read and write requests) if a write-through policy is used for cache updation.
The access time of a main memory is 800 ns and cache memory access time is 70 ns. The ratio of read and write requests is 7:3. The hit ratio for read access only is 80%. ...
rahulkarmakar
430
views
rahulkarmakar
asked
Jun 16, 2023
CO and Architecture
co-and-architecture
effective-memory-access
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0
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1
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153
Ace Test Series | Computer Organistaion
A pipelined processor with a separate instruction & data cache has 5- stages, the cycle time 30 nano sec. It can start a new instruction on every cycle when there were no hazards. It is used with copy- back data cache with a block size of one - ... store which only result hazards. What is the throughout of CPU. a) 31 MIPS b) 24 MIPS c) 48 MIPS d) 10 MIPS
A pipelined processor with a separate instruction & data cache has 5- stages, the cycle time 30 nano sec. It can start a new instruction on every cycle when there were no...
none30
328
views
none30
asked
Jun 12, 2023
CO and Architecture
ace-test-series
co-and-architecture
pipelining
throughput
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0
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2
answers
154
Addressing mode
lea
333
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lea
asked
Jun 12, 2023
CO and Architecture
co-and-architecture
addressing-modes
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0
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1
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155
Addressing Modes
lea
308
views
lea
asked
Jun 12, 2023
CO and Architecture
co-and-architecture
addressing-modes
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0
votes
1
answer
156
Cache Mapping
In a 2 level hierarchy, the cache has an access time of 15 ns and the main memory has an access time of 110 ns, the hit rate of the cache is 90%. If the block size of the cache is 16 Bytes, then average memory access time including miss penalty is?
In a 2 level hierarchy, the cache has an access time of 15 ns and the main memory has an access time of 110 ns, the hit rate of the cache is 90%. If the block size of the...
Mrityudoot
665
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Mrityudoot
asked
Jun 5, 2023
CO and Architecture
co-and-architecture
cache-memory
multilevel-cache
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0
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1
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157
Computer Organization
Under what category does Universal Serial Bus fall: System Bus or a Network connection or something else?
Under what category does Universal Serial Bus fall: System Bus or a Network connection or something else?
Mrityudoot
199
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Mrityudoot
asked
May 22, 2023
CO and Architecture
co-and-architecture
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0
votes
1
answer
158
Synchronization problem on single processor cpu
Consider the following multi threaded code. volatile static int flag1= 0, flag2= 0; // code for thread 1 (or T1) flag1 = 1; if (flag2==0) code1(); // end of code for T1 // code for thread 2 (or T2) flag2 = 1; if ( ... (). no method is invoked. both methods cannot be invoked! Also, what will be the answer if we remove the volatile type from the flags.
Consider the following multi threaded code.volatile static int flag1= 0, flag2= 0; // code for thread 1 (or T1) flag1 = 1; if (flag2==0) code1(); // end of code for T1 //...
dd
379
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dd
asked
May 14, 2023
Operating System
operating-system
co-and-architecture
process-synchronization
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0
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0
answers
159
Computer Architecture Cache, VM, and DRAM
A byte-addressable system with 16-bit addresses ships with a three-way set associative, write-back cache (i.e., each block needs a dirty bit). The cache implements a true LRU replacement policy using the minimum number of replacement policy bits ... and please also do not forget that aside from the tag itself, each block needs 1 valid bit, 1 dirty bit).
A byte-addressable system with 16-bit addresses ships with a three-way set associative, write-back cache (i.e., each block needs a dirty bit). The cache implements a true...
Daeklord
229
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Daeklord
asked
May 5, 2023
CO and Architecture
co-and-architecture
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0
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1
answer
160
when CPU needs to access some data does it first check in registers or L1 cache?
Veer123
187
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Veer123
asked
May 4, 2023
CO and Architecture
co-and-architecture
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0
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0
answers
161
Design a 4M X 32 bits memory using 512X8 bits memory chip.
AYAN CHAKRABORTY
390
views
AYAN CHAKRABORTY
asked
Apr 21, 2023
CO and Architecture
co-and-architecture
bits
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0
votes
1
answer
162
coa question
Interpret the main memory addresses FF010,12364,andC7691 considering direct, associative and 2 way set associative mapping if the main memory size is 1MB,word size is 16 bytes, and cache size is 64KB.
Interpret the main memory addresses FF010,12364,andC7691 considering direct, associative and 2 way set associative mapping if the main memory size is 1MB,word size is 16 ...
1234hello
881
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1234hello
asked
Mar 10, 2023
CO and Architecture
co-and-architecture
memory-management
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1
votes
1
answer
163
BARC 2015
Operand is fetched from memory During (A) fetch phase (B) execute phase (C) decode phase (D) read phase
Operand is fetched from memory During(A) fetch phase(B) execute phase(C) decode phase(D) read phase
dutta18
480
views
dutta18
asked
Mar 8, 2023
CO and Architecture
co-and-architecture
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0
votes
1
answer
164
self doubt
Can Interrupt-Driven I/O be memory mapped? Polling is memory mapped or IO mapped?
Can Interrupt-Driven I/O be memory mapped?Polling is memory mapped or IO mapped?
Rutuja7
269
views
Rutuja7
asked
Mar 7, 2023
CO and Architecture
co-and-architecture
io-handling
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0
votes
1
answer
165
With the help of the following information, determine the size of the sub-fields (in bits) in the address for direct mapping, associative mapping and set-associative mapping: 512 MB main memory and 2 MB cache memory Address space of the processor is 256 MB The block size is 256 bytes There are 16 blocks in a cache set.
rookoodracula
2.1k
views
rookoodracula
asked
Mar 3, 2023
CO and Architecture
co-and-architecture
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0
votes
1
answer
166
self doubt
true/ false cpu generate logical address(which is for Rom/secondary memory) and MAR stores physical address which is (data/instruction ready for execution in ram)
true/ falsecpu generate logical address(which is for Rom/secondary memory) and MAR stores physical address which is (data/instruction ready for execution in ram)
someshawasthi
341
views
someshawasthi
asked
Feb 20, 2023
CO and Architecture
co-and-architecture
logical-reasoning
true-false
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9
votes
4
answers
167
GATE CSE 2023 | Question: 23
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third stages, respectively. Assume that there is no other ... instruction is fetched every cycle. The total execution time for executing $100$ instructions on this processor is _____________ $\mathrm{ns}.$
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for the first, second, and the third...
admin
9.5k
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admin
asked
Feb 15, 2023
CO and Architecture
gatecse-2023
co-and-architecture
pipelining
numerical-answers
1-mark
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11
votes
2
answers
168
GATE CSE 2023 | Question: 24
A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check for a keystroke and consumes $100\; \mu \mathrm{s}$ (micro seconds) for ... interrupt and processing a keystroke. The ratio $\dfrac{T_{1}}{T_{2}}$ is _____________. (Rounded off to one decimal place)
A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) to check ...
admin
8.0k
views
admin
asked
Feb 15, 2023
CO and Architecture
gatecse-2023
co-and-architecture
interrupts
numerical-answers
1-mark
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9
votes
1
answer
169
GATE CSE 2023 | Question: 31
Consider the given $\text{C}$-code and its corresponding assembly code, with a few operands $\text{U1-U4}$ being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable. Which one of ... $(3,4,4, \text{L01)}$ $(8,1,1, \text{L02)}$ $(3,1,1, \text{L01)}$
Consider the given $\text{C}$-code and its corresponding assembly code, with a few operands $\text{U1-U4}$ being unknown. Some useful information as well as the semantics...
admin
7.1k
views
admin
asked
Feb 15, 2023
CO and Architecture
gatecse-2023
co-and-architecture
assembly-code
2-marks
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