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Recent questions tagged co-and-architecture
0
votes
1
answer
1501
COA:- Average stalls per instruction
What will be L1 miss rate? I think it is 80/3600 ,but then answer did not match. But if i take 80/2000,then it matches with the given answer
What will be L1 miss rate? I think it is 80/3600 ,but then answer did not match. But if i take 80/2000,then it matches with the given answer
rahul sharma 5
842
views
rahul sharma 5
asked
Nov 6, 2017
CO and Architecture
co-and-architecture
cache-memory
stall
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–
0
votes
2
answers
1502
COA:- Memory Access Time
rahul sharma 5
775
views
rahul sharma 5
asked
Nov 6, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
2
votes
2
answers
1503
CO:- Memory Access time
rahul sharma 5
1.5k
views
rahul sharma 5
asked
Nov 6, 2017
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
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–
7
votes
1
answer
1504
MadeEasy Subject Test: CO & Architecture - Pipelining
Which of the following statements are true? 1. WAW and WAR can be reduced but cannot be completely removed from the pipeline. 2.In direct mapped cache,may produce more misses of program refers to a memory word that occupies same tag value 3.By register renaming,all the stalls created by anti data dependency are eliminated
Which of the following statements are true?1. WAW and WAR can be reduced but cannot be completely removed from the pipeline.2.In direct mapped cache,may produce more miss...
rahul sharma 5
2.9k
views
rahul sharma 5
asked
Nov 6, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
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–
0
votes
0
answers
1505
MadeEasy Subject Test: CO & Architecture - Clock Frequency
I got 34 as answer, but given is 35.
I got 34 as answer, but given is 35.
rahul sharma 5
374
views
rahul sharma 5
asked
Nov 6, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
clock-frequency
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–
3
votes
3
answers
1506
Hardware requirement in 16-way Set Associative Cache
Cache size 32 KB Block size = 32 Bytes Address size = 28 bit. Associativity of Cache = 16 Determine what is the hardware requirement to design the 16-way set associative cache. Hardware requirement -> Mux, Comparator, Demux, Decoder, Encoder ... lines are 5. 4) 64 And gates 5) 1 OR gate input line = 64 Someone, please verify these attributes??
Cache size 32 KBBlock size = 32 BytesAddress size = 28 bit.Associativity of Cache = 16Determine what is the hardware requirement to design the 16-way set associative cach...
Shubhanshu
3.2k
views
Shubhanshu
asked
Nov 6, 2017
CO and Architecture
cache-memory
co-and-architecture
multiplexer
memory-interfacing
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–
2
votes
1
answer
1507
pipelining
Parshu gate
582
views
Parshu gate
asked
Nov 6, 2017
CO and Architecture
pipelining
co-and-architecture
+
–
1
votes
1
answer
1508
CACHE direct mapping
Parshu gate
1.5k
views
Parshu gate
asked
Nov 6, 2017
CO and Architecture
cache-memory
direct-mapping
co-and-architecture
+
–
1
votes
0
answers
1509
Addressing modes
Can somebody explain what is indirect indexed addressing mode ? Is it similar to indexed addressing mode ? Will the effective address be calculated by adding some constant to the content of some register as is done in indexed AM ? Any help would be appreciated.
Can somebody explain what is indirect indexed addressing mode ? Is it similar to indexed addressing mode ? Will the effective address be calculated by adding some constan...
sumit chakraborty
356
views
sumit chakraborty
asked
Nov 5, 2017
CO and Architecture
addressing-modes
co-and-architecture
+
–
0
votes
0
answers
1510
pipelining
Parshu gate
251
views
Parshu gate
asked
Nov 5, 2017
CO and Architecture
pipelining
co-and-architecture
+
–
2
votes
2
answers
1511
UGC NET CSE | November 2017 | Part 3 | Question: 6
A micro-instruction format has micro-ops field which is divided into three subfields $F1$, $F2$, $F3$ each having seven distinct micro-operations, conditions field $CD$ for four status bits, branch field $BR$ having four options used in conjunction ... $128$ memory locations. The size of micro-instruction is $17$ bits $20$ bits $24$ bits $32$ bits
A micro-instruction format has micro-ops field which is divided into three subfields $F1$, $F2$, $F3$ each having seven distinct micro-operations, conditions field $CD$ f...
Arjun
1.8k
views
Arjun
asked
Nov 5, 2017
CO and Architecture
ugcnetcse-nov2017-paper3
microprocessors
co-and-architecture
+
–
1
votes
2
answers
1512
UGC NET CSE | November 2017 | Part 3 | Question: 5
Which of the following is correct statement? In memory - mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memory words. The isolated I/O method isolates memory and I ... data the two units share a common clock. In synchronous serial transmission of data the two units have different clocks.
Which of the following is correct statement?In memory – mapped I/O, the CPU can manipulate I/O data residing in interface registers that are not used to manipulate memo...
Arjun
3.3k
views
Arjun
asked
Nov 5, 2017
CO and Architecture
ugcnetcse-nov2017-paper3
microprocessors
co-and-architecture
+
–
3
votes
2
answers
1513
UGC NET CSE | November 2017 | Part 3 | Question: 4
Which of the following addressing mode is best suited to access elements of an array of contiguous memory locations? Indexed addressing mode Base Register addressing mode Relative address mode Displacement mode
Which of the following addressing mode is best suited to access elements of an array of contiguous memory locations?Indexed addressing mode Base Register add...
Arjun
970
views
Arjun
asked
Nov 5, 2017
CO and Architecture
ugcnetcse-nov2017-paper3
addressing-modes
co-and-architecture
+
–
1
votes
1
answer
1514
UGC NET CSE | November 2017 | Part 3 | Question: 3
In the architecture of $8085$ ... $\text{(a)-(ii) (b)-(iii) (c)-(i)}$ $\text{(a)-(i) (b)-(ii) (c)-(iv)}$
In the architecture of $8085$ microprocessor match the following :$\begin{array}{clcl} \text{(a)} & \text{Processing unit} & \text{(i)} & \text{Interrupt} \\ \text{(b)}...
Arjun
1.7k
views
Arjun
asked
Nov 5, 2017
CO and Architecture
ugcnetcse-nov2017-paper3
microprocessors
8085-microprocessor
co-and-architecture
+
–
1
votes
0
answers
1515
UGC NET CSE | November 2017 | Part 3 | Question: 2
In $8085$ microprocessor the address bus is of ___________ bits. $4$ $8$ $16$ $32$
In $8085$ microprocessor the address bus is of ___________ bits.$4$$8$$16$$32$
Arjun
2.3k
views
Arjun
asked
Nov 5, 2017
CO and Architecture
ugcnetcse-nov2017-paper3
microprocessors
8085-microprocessor
co-and-architecture
+
–
3
votes
2
answers
1516
UGC NET CSE | November 2017 | Part 3 | Question: 1
In $8085$ microprocessor which of the following flag(s) is (are) affected by an arithmetic operation? AC flag only CY flag Only Z flag Only AC, CY, Z flags
In $8085$ microprocessor which of the following flag(s) is (are) affected by an arithmetic operation?AC flag onlyCY flag OnlyZ flag OnlyAC, CY, Z flags
Arjun
1.6k
views
Arjun
asked
Nov 5, 2017
CO and Architecture
ugcnetcse-nov2017-paper3
microprocessors
8085-microprocessor
co-and-architecture
+
–
0
votes
1
answer
1517
Seek time in cylinders
Parshu gate
669
views
Parshu gate
asked
Nov 5, 2017
CO and Architecture
co-and-architecture
seek-time
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–
1
votes
2
answers
1518
UGC NET CSE | November 2017 | Part 2 | Question: 50
Which speed up could be achieved according to Amdahl's Law for infinte number of processes if $5\%$ of a program is sequential and the remaining part is ideally parallel? Infinite $5$ $20$ $50$
Which speed up could be achieved according to Amdahl's Law for infinte number of processes if $5\%$ of a program is sequential and the remaining part is ideally parallel?...
Arjun
3.1k
views
Arjun
asked
Nov 5, 2017
Unknown Category
ugcnetcse-nov2017-paper2
co-and-architecture
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–
0
votes
1
answer
1519
UGC NET CSE | November 2017 | Part 2 | Question: 46
Which of the following Super Computers is the fastest Super Computer? Sun-way TaihuLight Titan Piz Daint Sequoia
Which of the following Super Computers is the fastest Super Computer?Sun-way TaihuLightTitanPiz DaintSequoia
Arjun
1.3k
views
Arjun
asked
Nov 5, 2017
Unknown Category
ugcnetcse-nov2017-paper2
co-and-architecture
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–
2
votes
2
answers
1520
UGC NET CSE | November 2017 | Part 2 | Question: 31
Consider the following program fragment in assembly language: mov ax, 0h mov cx, 0A h do loop: dec ax loop doloop What is the value of $ax$ and $cx$ registers after the completion of the doloop ? $ax= FFF5 \: h$ and $cx=0 \:h$ $ax= FFF6 \: h$ and $cx=0 \: h$ $ax= FFF7 \: h$ and $cx=0A \:h$ $ax=FFF5 \: h$ and $cx=0A \: h$
Consider the following program fragment in assembly language:mov ax, 0h mov cx, 0A h do loop: dec ax loop doloopWhat is the value of $ax$ and $cx$ registers after the com...
Arjun
6.1k
views
Arjun
asked
Nov 5, 2017
CO and Architecture
ugcnetcse-nov2017-paper2
co-and-architecture
8085-microprocessor
+
–
1
votes
0
answers
1521
Ace Test Series: CO & Architecture - Cache Memory
What is the answer of this question. I think similar question was asked in GATE 2017.
What is the answer of this question. I think similar question was asked in GATE 2017.
rohan mishra
429
views
rohan mishra
asked
Nov 5, 2017
CO and Architecture
ace-test-series
cache-memory
co-and-architecture
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–
1
votes
1
answer
1522
MadeEasy Subject Test: CO & Architecture - Cache Memory
rahul sharma 5
747
views
rahul sharma 5
asked
Nov 4, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
0
votes
1
answer
1523
Basic doubt in CO
1. Effective address(Address of instruction or operand ) is virtual address or physical address? 2. While solving problems is OS we say CPU generates virtual address and while is CO we say CPU generates physical address.But what does CPU actually generates? I think CPU always generates Virtual adress,but not sure.
1. Effective address(Address of instruction or operand ) is virtual address or physical address?2. While solving problems is OS we say CPU generates virtual address and w...
rahul sharma 5
348
views
rahul sharma 5
asked
Nov 4, 2017
CO and Architecture
co-and-architecture
+
–
2
votes
0
answers
1524
Doubt in pipelining questions.
Consider this question and its selected answer: https://gateoverflow.in/3690/gate2004-it-47 And this question: https://gateoverflow.in/1314/gate2009-28 Both questions are somewhat similar. In the first one's answer, instruction $I_1$ (when i = ... I am missing? PS. From where can I study this? Hamacher book doesn't contain pipelining in this much detail.
Consider this question and its selected answer: https://gateoverflow.in/3690/gate2004-it-47And this question: https://gateoverflow.in/1314/gate2009-28Both questions are s...
Rishabh Gupta 2
1.5k
views
Rishabh Gupta 2
asked
Nov 4, 2017
CO and Architecture
co-and-architecture
pipelining
gateit-2004
gatecse-2009
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–
2
votes
1
answer
1525
Computer organization
A system which has lot of crashes, data should be written to the disk using A. Write-through B. Wtite-back C. Both
A system which has lot of crashes, data should be written to the disk usingA. Write-throughB. Wtite-backC. Both
rishu_darkshadow
1.8k
views
rishu_darkshadow
asked
Nov 4, 2017
CO and Architecture
co-and-architecture
write-through
write-back
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–
4
votes
1
answer
1526
Test question on Pipelining
Parshu gate
1.4k
views
Parshu gate
asked
Nov 3, 2017
CO and Architecture
co-and-architecture
pipelining
clock-cycles
+
–
1
votes
1
answer
1527
File system OS
One way to use contiguous allocation of disk and not suffer from holes is to compact the disk every time a file is removed. Since all files are contiguous, copying a file requires a seek and rotational delay to read the file, followed by the transfer at full speed. ... of 1MB, how long does it take to read a file into main memory then write it back to the disk at a new location?
One way to use contiguous allocation of disk and not suffer from holes is to compact the disk every time a file is removed. Since all files are contiguous, copying a file...
rahul sharma 5
1.2k
views
rahul sharma 5
asked
Nov 2, 2017
CO and Architecture
co-and-architecture
operating-system
file-system
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–
5
votes
1
answer
1528
Average Memory Access Time
Suppose cache with hit ratio 'Ch' and access time 'Ct' is given and main memory with hit ratio 'Mh' and access time 'Mt' is given and a disk with access time 'Dt' is given. If with only this information average memory access time is ... (1-Ch) * (1-Mh) * ( Ct + Mt + Dt) If so, why the addition and is it implicit always ?
Suppose cache with hit ratio 'Ch' and access time 'Ct' is given and main memory with hit ratio 'Mh' and access time 'Mt' is given and a disk with access time 'Dt' is give...
sumit chakraborty
1.6k
views
sumit chakraborty
asked
Nov 1, 2017
CO and Architecture
cache-memory
co-and-architecture
effective-memory-access
+
–
4
votes
1
answer
1529
Pipelining
A 5 stage pipeline system is in operation with clock cycle of n ns. If the clock per instruction CPI for non-pipelined system is 5,and Instruction per clock for pipeline is 5,and pipeline efficiency is 70% what is the speed up factor? Please explain the Soultion and concept briefly i am little bit confused.
A 5 stage pipeline system is in operation with clock cycle of n ns. If the clock per instruction CPI for non-pipelined system is 5,and Instruction per clock for pipeline ...
Na462
2.6k
views
Na462
asked
Nov 1, 2017
CO and Architecture
co-and-architecture
pipelining
speedup
+
–
3
votes
1
answer
1530
MadeEasy Subject Test: CO & Architecture - Pipelining
shane.126
923
views
shane.126
asked
Oct 31, 2017
CO and Architecture
co-and-architecture
pipelining
made-easy-test-series
+
–
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