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Recent questions tagged co-and-architecture
7
votes
1
answer
1621
DMA Concept
reference to this pdf :https://gateoverflow.in/?qa=blob&qa_blobid=13639721099184478126 Can any one define in simple terms X μsec =data transfer time or preparation time (words/block) ? Y μsec =memory cycle time or cycle time or transfer time (words/block) ?
reference to this pdf :https://gateoverflow.in/?qa=blob&qa_blobid=13639721099184478126Can any one define in simple termsX μsec =data transfer time or preparation time (w...
hem chandra joshi
3.8k
views
hem chandra joshi
asked
Jun 21, 2017
CO and Architecture
co-and-architecture
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0
votes
3
answers
1622
gateforum CO&A cache memory Level 2 Q17
On a system with 32 bit addresses and 4KB pages, how many levels are required in multilevel page table (assume that each entry in the page table takes 4 bytes of storage)? a. 2 b. 3 c.1 d. None of these
On a system with 32 bit addresses and 4KB pages, how many levels are required in multilevel page table (assume that each entry in the page table takes 4 bytes of storage)...
Satyajeet Singh
459
views
Satyajeet Singh
asked
Jun 14, 2017
CO and Architecture
co-and-architecture
cache-memory
gateforum
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0
votes
2
answers
1623
Gateforum Test Series: CO & Architecture - cache memory
Assume a cache of $2K$ blocks ( 1 block size = 4 words= 16 bytes) and $32-bit$ address. Assume this machine is byte addressable. What is the bit length of each field in direct mapped? $(A).\space 19,11,2$ $(B).\space 20,11,2$ $(C).\space 21,9,2$ $(D). \text{none of these}$
Assume a cache of $2K$ blocks ( 1 block size = 4 words= 16 bytes) and $32-bit$ address. Assume this machine is byte addressable.What is the bit length of each field in di...
Satyajeet Singh
1.8k
views
Satyajeet Singh
asked
Jun 14, 2017
CO and Architecture
co-and-architecture
cache-memory
direct-mapping
gateforum
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–
1
votes
1
answer
1624
DMA %CPU blocked equation
% CPU blocked or consumed = (x/y) (in case of cycle stealing) where x= data preparation time and y= data transfer time.. I read questions and answers using this formula but i cant understand how this formula is formulated .. how we are ... ; data transfer time ' , CPU is blocked for a period equal 'data preparation time'? Please someone help me with equation
% CPU blocked or consumed = (x/y) (in case of cycle stealing)where x= data preparation time and y= data transfer time.. I read questions and answers using this formula ...
Satyajeet Singh
2.8k
views
Satyajeet Singh
asked
Jun 13, 2017
CO and Architecture
dma
co-and-architecture
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0
votes
0
answers
1625
DSSB_2017
The group of digits stored at each address in memory is generally referred as ??? A.memory bit B.memory byte C.memory word D.memory block please explain it if you are answerintg.thanku
The group of digits stored at each address in memory is generally referred as ???A.memory bitB.memory byteC.memory wordD.memory block please explain it if you are answeri...
Harikesh Kumar
748
views
Harikesh Kumar
asked
Jun 12, 2017
CO and Architecture
co-and-architecture
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0
votes
1
answer
1626
can any one explain the following things?
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long.
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long.
hem chandra joshi
352
views
hem chandra joshi
asked
Jun 11, 2017
CO and Architecture
co-and-architecture
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1
votes
2
answers
1627
carl Hamacher 6th edition Q.no 5.11
A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz clock. Instruction statistics in a large program are as follows: Branch 20% Load 20% Store 10% Computational instructions 50% Estimate the rate of instruction ... clock cycles. On average, access to the data operands of a Load or Store instruction is completed in 3 clock cycles.
A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz clock. Instruction statistics in a large program are as follows:Branch 20%Load 20%Sto...
Amit.kumar
1.6k
views
Amit.kumar
asked
Jun 7, 2017
CO and Architecture
co-and-architecture
machine-instruction
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5
votes
2
answers
1628
Carl-Hamacher
A computer system has a main memory consisting 1M 16 bit-words.It also has a 4K-word cache organized in the block-set-associative manner,with 4 blocks per set and 64 words per block. a)assume that the cache is initially empty.Suppose that the processor ... the improvement factor resulting from the use of the cache.Assume that LRU algorithm is used for block replacement. ans is: 2.15
A computer system has a main memory consisting 1M 16 bit-words.It also has a 4K-word cache organized in the block-set-associative manner,with 4 blocks per set and 64 word...
reena_kandari
4.6k
views
reena_kandari
asked
Jun 7, 2017
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
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2
votes
0
answers
1629
Carl-Hamacher
Acomputer with a 16-bit word length has a direct-mapped cache, used for both instructions and data. Memory addresses are 16 bits long, and the memory is byte-addressable. The cache is small for illustrative purposes. It contains only four 16-bit words. ... the execution time for each pass, counting only memory access times @Arjun and @Bikram sir please have a look at this question.
Acomputer with a 16-bit word length has a direct-mapped cache, used for both instructionsand data. Memory addresses are 16 bits long, and the memory is byte-addressable.T...
reena_kandari
676
views
reena_kandari
asked
Jun 7, 2017
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
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0
votes
2
answers
1630
Carl hamacher
A program consists of two nested loops-a small inner loop and a much larger outer loop.The decimal memory addresses shown delineate the location of the two loops and the beginning and end of the total program. All memory locations in the various sections of ... the cycle time of the cache is 1τ s. Compute the total time needed for instruction fetching during execution of the program.
A program consists of two nested loops—a small inner loop and a much larger outer loop.The decimal memory addressesshown delineate the location of the two loops and the...
reena_kandari
1.8k
views
reena_kandari
asked
Jun 7, 2017
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
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5
votes
3
answers
1631
Implementation of BSA(Branch and save address) instruction
I have a doubt regarding the implementation of BSA instruction. I read that BSA instruction can be implemented as :- T4:- m[AR] <-- PC; AR<--AR+1 T5:- PC<--AR; SC<--0 Here T4 and T5 are 4th and ... to the position where PC is written. So they should happen at different clock cycles right so that they can execute in proper order?
I have a doubt regarding the implementation of BSA instruction. I read that BSA instruction can be implemented as :-T4:- m[AR] < PC; AR< AR+1T5:- PC< AR; SC< 0He...
Xylene
3.1k
views
Xylene
asked
Jun 6, 2017
CO and Architecture
co-and-architecture
machine-instruction
branch-conditional-instructions
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5
votes
1
answer
1632
Carl Hamacher
Registers R1 and R2 of a computer contain the decimal values 1200 and 4600.What is the Effective address of the memory operand in each of the following instructions? a) Load 20(R1),R5 b) Move #3000,R5 c) Store R5,30(R1,R2) d) Add -(R2),R5 e) Subtract (R1)+,R5
Registers R1 and R2 of a computer contain the decimal values 1200 and 4600.What is the Effectiveaddress of the memory operand in each of the following instructions?a) Loa...
reena_kandari
33.7k
views
reena_kandari
asked
Jun 4, 2017
CO and Architecture
co-and-architecture
carl-hamacher
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0
votes
1
answer
1633
computer organisation
If a system is Byte-addressable system , Can we always conclude that 1 word = 1 Byte ??? Please explain your answer ...
If a system is Byte-addressable system ,Can we always conclude that 1 word = 1 Byte ???Please explain your answer ...
vignesh
393
views
vignesh
asked
Jun 3, 2017
CO and Architecture
co-and-architecture
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3
votes
1
answer
1634
Computer Organization Interrupts
Assume a CPU takes 17 cycles in worst case to execute an instruction.Number of cycles required to execute the current instruction is 12.If an interrupt occurs during the execution of current instruction,then after how many cycles it will be recogonized? a:) 17 b:) 11 c:)12 d:)17+2
Assume a CPU takes 17 cycles in worst case to execute an instruction.Number of cycles required to execute the current instruction is 12.If an interrupt occurs during the ...
rahul sharma 5
1.1k
views
rahul sharma 5
asked
Jun 1, 2017
CO and Architecture
co-and-architecture
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1
votes
1
answer
1635
[COA] William Stallings ,6.6
Consider a disk that rotates at 3600 rpm.The seek time to move the head between adjacent tracks is 2 ms. There are 32 sectors per track, which are stored in linear order from sector 0 through sector 31.The head sees the sectors in ascending order.Assume ... track 9? b. How long will it take to transfer all the sectors of track 8 to the corresponding sectors of track 9?
Consider a disk that rotates at 3600 rpm.The seek time to move the head between adjacenttracks is 2 ms. There are 32 sectors per track, which are stored in linear orderfr...
rahul sharma 5
2.4k
views
rahul sharma 5
asked
Jun 1, 2017
CO and Architecture
co-and-architecture
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0
votes
1
answer
1636
Computer Organisation & Architecture
Control field of a microinstruction supports 2 groups of control signals in which group 1 indicates none or one of 325 signals and group 2 indicates at most 8 signals from the remaining.What is the size of a control field in the microinstruction?
Control field of a microinstruction supports 2 groups of control signals in which group 1 indicates none or one of 325 signals and group 2 indicates at most 8 signals fro...
Sayantan
659
views
Sayantan
asked
Jun 1, 2017
CO and Architecture
co-and-architecture
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0
votes
1
answer
1637
[COA] List of micro operations
Write the sequence of micro-operations required for the bus structure of following figure to add a number to the AC when the number is a. an immediate operand b. a direct-address operand c. an indirect-address operand
Write the sequence of micro-operations required for the bus structure of following figureto add a number to the AC when the number isa. an immediate operandb. a direct-ad...
rahul sharma 5
1.2k
views
rahul sharma 5
asked
May 31, 2017
CO and Architecture
co-and-architecture
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1
votes
1
answer
1638
[COA] Counting dependencies
Consider the following program to be executed on this processor: I1: Load R1, A /R1 ← Memory (A)/ I2: Add R2, R1 /R2 ← (R2) + R(1)/ I3: Add R3, R4 /R3 ← (R3) + R(4)/ I4: Mul R4, R5 /R4 ← (R4) + R(5)/ I5: Comp R6 /R6 ← (R6)/ I6: Mul R6, R7 /R3 ← (R3) + R(4)/ a. What dependencies exist in the program?
Consider the following program to be executed on this processor:I1: Load R1, A /R1 ← Memory (A)/I2: Add R2, R1 /R2 ← (R2) + R(1)/I3: Add R3, R4 /R3 ← (R3) + R(4)/I4...
rahul sharma 5
467
views
rahul sharma 5
asked
May 31, 2017
CO and Architecture
co-and-architecture
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–
0
votes
0
answers
1639
[COA] William Stallings 12.4,Problem
A microprocessor provides an instruction capable of moving a string of bytes from one area of memory to another. The fetching and initial decoding of the instruction takes 10 clock cycles.Thereafter, it takes 15 clock cycles to transfer ... noninterruptible? c. Repeat part (b) assuming the instruction can be interrupted at the beginning of each byte transfer.
A microprocessor provides an instruction capable of moving a string of bytes fromone area of memory to another. The fetching and initial decoding of the instructiontakes ...
rahul sharma 5
524
views
rahul sharma 5
asked
May 31, 2017
CO and Architecture
co-and-architecture
+
–
0
votes
0
answers
1640
[COA] William Stallings Problem 7.2,8th edition
Consider a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis. a. Assume that interrupt processing takes about 100 s (i.e., the time to jump to the interrupt ... of a block in only 2 s. Determine what fraction of processor time is consumed by this I/O device in this case.
Consider a system employing interrupt-driven I/O for a particular device that transfersdata at an average of 8 KB/s on a continuous basis.a. Assume that interrupt process...
rahul sharma 5
691
views
rahul sharma 5
asked
May 30, 2017
CO and Architecture
co-and-architecture
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–
0
votes
0
answers
1641
[COA[ Hamacher Problem 5.11 Find Speed up ratio
A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword cache divided into four-line sets with 64 words per line. Assume that the cache is initially empty. The processor fetches words from locations ... MRU policy for block replacement. The same question with LRU has been answered:- https://gateoverflow.in/11240/cache-memory
A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword cache divided into four-line sets with 64 words per line. Assume that the cache is init...
rahul sharma 5
628
views
rahul sharma 5
asked
May 30, 2017
CO and Architecture
co-and-architecture
cache-memory
speedup
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–
1
votes
1
answer
1642
[COA] Hamacher Example 5.2,Page 322,Fifth edition
Writing the example in short words; Cache Access =1ns Main Memory Access =10 clock cycles Time to load word into the cache = 17 cycles 30% Instructions perform Memory read and write. Instruction cache Hit rate=.95 and Data cache ... same for both read and write access. Find the performance gain if we use system with cache over system without cache.
Writing the example in short words;Cache Access =1nsMain Memory Access =10 clock cyclesTime to load word into the cache = 17 cycles30% Instructions perform Memory read an...
rahul sharma 5
612
views
rahul sharma 5
asked
May 29, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
1
votes
1
answer
1643
[COA] DMA
In cycle stealing mode,the DMA gets control over ? 1. Data and address bus 2.Data and control bus 3.Address and control bus 4. None
In cycle stealing mode,the DMA gets control over ?1. Data and address bus2.Data and control bus3.Address and control bus4. None
rahul sharma 5
1.1k
views
rahul sharma 5
asked
May 27, 2017
CO and Architecture
co-and-architecture
dma
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–
1
votes
1
answer
1644
[COA] I/o Organization
Consider the following statements:- 1. Change program counter value 2. Change page table register context 3. Disable interrupt 4. Initiate I/o on a disk using memory mapped I/o which of the above can be executed in only in system mode? a.) 1,3,4 b)2,3,4 c.)1,2,3 d)2,4,1 Please give valid explanation with your answer.
Consider the following statements:-1. Change program counter value2. Change page table register context3. Disable interrupt4. Initiate I/o on a disk using memory mapped I...
rahul sharma 5
1.2k
views
rahul sharma 5
asked
May 27, 2017
CO and Architecture
co-and-architecture
interrupts
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–
0
votes
1
answer
1645
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 30
Consider a hypothetical processor that supports two address, one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is placed in $1$ word of memory (memory ... one address instructions. The total number of zero address instructions formulated is ________ (put in integers only)
Consider a hypothetical processor that supports two address, one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is placed i...
Bikram
335
views
Bikram
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
instruction-format
+
–
1
votes
1
answer
1646
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 29
Suppose in a system we store data using arrays, we have $2$ arrays A1 and A2. Array A1 contains $256$ elements of size $4$ bytes each. The first element is stored at physical address $4096$ ... of bytes that will be written to memory during execution of the loop is : $256$ $1$ $0$ $2048$
Suppose in a system we store data using arrays, we have $2$ arrays A1 and A2. Array A1 contains $256$ elements of size $4$ bytes each. The first element is stored at phy...
Bikram
508
views
Bikram
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
cache-memory
+
–
0
votes
1
answer
1647
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 28
Consider the following Micro-operations: ... Memory Buffer Register The given micro-operations describes : Interrupt Cycle Fetch Cycle Execute Cycle Indirect Cycle
Consider the following Micro-operations:$\begin{array}{|l|l|} \hline \text{MAR} & \leftarrow IR \text{[address]} \\ \hline \text{MBR} & \leftarrow \text{Memory} \\ \hline...
Bikram
605
views
Bikram
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
microprogramming
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–
0
votes
2
answers
1648
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 27
Consider a memory hierarchy system consisting of two levels. The access time of level $1$ is $2$ ns. The miss penalty (The time to get data from level $2$, in case of miss) is $100$ ns. If the average memory ... the average access time to $40 \%$, the probability that valid data found in level $1$ is ___________ $\%$
Consider a memory hierarchy system consisting of two levels. The access time of level $1$ is $2$ ns. The miss penalty (The time to get data from level $2$, in case of mis...
Bikram
369
views
Bikram
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
+
–
0
votes
1
answer
1649
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 26
Which of the following statements is/are correct about hazards? One way to implement branch prediction is to store the result of a branch condition in a branch target buffer to help guide instruction pre-fetching if the branch is ... whether the branch is taken. III only II and III only I and III only I, II, and III
Which of the following statements is/are correct about hazards?One way to implement branch prediction is to store the result of a branch condition in a branch target buff...
Bikram
261
views
Bikram
asked
May 27, 2017
CO and Architecture
tbb-coa-2
co-and-architecture
pipelining
data-dependency
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–
2
votes
2
answers
1650
Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 25
Suppose there are $500$ memory references in which $50$ misses in the $1$st level cache and $20$ misses in the $2$nd level cache . Let the miss penalty from L2 cache to memory is $100$ cycles. ... cycles. If there are $2.5$ memory reference/instruction , average number of stall cycles per instruction will be __________
Suppose there are $500$ memory references in which $50$ misses in the $1$st level cache and $20$ misses in the $2$nd level cache . Let the miss penalty from L2 cache to m...
Bikram
549
views
Bikram
asked
May 27, 2017
CO and Architecture
tbb-coa-2
numerical-answers
co-and-architecture
cache-memory
+
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