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Recent questions tagged co-and-architecture
0
votes
1
answer
1711
Addressing_mode
How we define big endian and little endian, word alignment ?
How we define big endian and little endian, word alignment ?
elakashi sharma
240
views
elakashi sharma
asked
Apr 30, 2017
CO and Architecture
co-and-architecture
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0
votes
1
answer
1712
Testbook Test Series: CO & Architecture - Cache Memory
If a 16-way Set Associative cache is made up of 64 bit words , 16 words per line and 8192 sets, How big is the cache in Megabytes ?
If a 16-way Set Associative cache is made up of 64 bit words , 16 words per line and 8192 sets,How big is the cache in Megabytes ?
Devwritt
1.8k
views
Devwritt
asked
Apr 29, 2017
CO and Architecture
co-and-architecture
testbook-test-series
cache-memory
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–
0
votes
0
answers
1713
Peripheral devices : CAO
Consider READ and WRITE bits: a) Both are written by CPU b) Both are written by peripheral c) READ bit is written by peripheral while WRITE bit is written by CPU d) WRITE bit is written by peripheral while READ bit is written by CPU
Consider READ and WRITE bits:a) Both are written by CPUb) Both are written by peripheralc) READ bit is written by peripheral while WRITE bit is written by CPUd) WRITE bit...
sh!va
820
views
sh!va
asked
Apr 26, 2017
CO and Architecture
io-organization
co-and-architecture
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–
1
votes
1
answer
1714
Implementation of OR gate using multiplexer.
How we implement OR gate using 2-to-1 multiplexer?
How we implement OR gate using 2-to-1 multiplexer?
elakashi sharma
351
views
elakashi sharma
asked
Apr 26, 2017
CO and Architecture
co-and-architecture
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–
2
votes
1
answer
1715
Miss rate and miss penalty
Difference in miss rate and miss panelaty ?
Difference in miss rate and miss panelaty ?
elakashi sharma
3.7k
views
elakashi sharma
asked
Apr 26, 2017
CO and Architecture
co-and-architecture
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–
1
votes
1
answer
1716
DM controller
What is the difference between DM controller and micropcessor. Block diagram of the device seems similar , both contains pins. Then how they are different from each other?
What is the difference between DM controller and micropcessor. Block diagram of the device seems similar , both contains pins. Then how they are different from each other...
elakashi sharma
313
views
elakashi sharma
asked
Apr 26, 2017
CO and Architecture
co-and-architecture
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–
0
votes
1
answer
1717
Performance consideration from coa
How this average access time derived ? Tavg=hC+(1-h)M. Please explain. M not getting this.
How this average access time derived ?Tavg=hC+(1-h)M.Please explain. M not getting this.
elakashi sharma
1.1k
views
elakashi sharma
asked
Apr 25, 2017
CO and Architecture
co-and-architecture
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–
0
votes
1
answer
1718
Standard books PDF.
Anyone is having standard book for coa hamachare 7 edition pls share link.
Anyone is having standard book for coa hamachare 7 edition pls share link.
elakashi sharma
2.6k
views
elakashi sharma
asked
Apr 24, 2017
Others
co-and-architecture
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–
2
votes
1
answer
1719
Coa-cache memory.
Cache size = 512KB ; Tag size = 7, Find out main memory size and tag directory. Given it is 8-way set associative .
Cache size = 512KB ; Tag size = 7, Find out main memory size and tag directory. Given it is 8-way set associative .
elakashi sharma
1.0k
views
elakashi sharma
asked
Apr 24, 2017
CO and Architecture
co-and-architecture
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–
2
votes
2
answers
1720
databases
what is the difference between a "Block" and "Sector" in Hard disk ..??? Are they both same ???
what is the difference between a "Block" and "Sector" in Hard disk ..??? Are they both same ???
vignesh
364
views
vignesh
asked
Apr 23, 2017
Databases
databases
b-tree
co-and-architecture
operating-system
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–
0
votes
0
answers
1721
How we decide address bit to select bit from one row?
It is given that for 4096 cells in each row are divided in to 512 groups of 8. Therefore address bits are of 12 to select row and 9 are to select a bit from a selected row. My question is how we decide this 9 bits for one row in order to select one bit ?
It is given that for 4096 cells in each row are divided in to 512 groups of 8. Therefore address bits are of 12 to select row and 9 are to select a bit from a selected ro...
elakashi sharma
334
views
elakashi sharma
asked
Apr 22, 2017
CO and Architecture
co-and-architecture
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0
votes
1
answer
1722
One bit data and one bit information are same ?
Some times it is given that memory cell stores one bit of information and some times one bit of data. Are these two statements same ? Register store one bit of data and memory cell stores one bit if information ? Difference in two ?
Some times it is given that memory cell stores one bit of information and some times one bit of data. Are these two statements same ?Register store one bit of data and me...
elakashi sharma
278
views
elakashi sharma
asked
Apr 21, 2017
CO and Architecture
co-and-architecture
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–
0
votes
1
answer
1723
Address generated by CPU is dependent on which factor?
Does address sent by CPU to Main Memory varies according to size of processor? 32 bit computer means size of processor or can it send 32 bits in one address to memory. Explain about address length sent by CPU
Does address sent by CPU to Main Memory varies according to size of processor? 32 bit computer means size of processor or can it send 32 bits in one address to memory. ...
elakashi sharma
273
views
elakashi sharma
asked
Apr 20, 2017
CO and Architecture
co-and-architecture
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–
0
votes
1
answer
1724
ISI-JRF
A machine M has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses: F-stage - instruction fetch (9 ns), D-stage - instruction decode and register fetch (3 ns), X-stage - execute/address ... , where every 3rd instruction needs a 1-cycle stall before the X-stage. Calculate the CPU time in seconds for completing P.
A machine M has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses:F-stage — instruction fetch (9 n...
kauray
458
views
kauray
asked
Apr 20, 2017
CO and Architecture
co-and-architecture
pipelining
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–
0
votes
1
answer
1725
Measurement of performance of computer system
Response time, elapsed time, access time all are consider same and equivalent ? Explanation.
Response time, elapsed time, access time all are consider same and equivalent ? Explanation.
elakashi sharma
1.1k
views
elakashi sharma
asked
Apr 20, 2017
CO and Architecture
co-and-architecture
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–
1
votes
2
answers
1726
ISI-JRF
Write the smallest real number greater than 6.25 that can be represented in the IEEE-754 single precision format (32-bit word with 1 sign bit and 8-bit exponent).
Write the smallest real number greater than 6.25 that can be represented in the IEEE-754 single precision format (32-bit word with 1 sign bit and 8-bit exponent).
kauray
827
views
kauray
asked
Apr 19, 2017
CO and Architecture
ieee-representation
co-and-architecture
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–
0
votes
1
answer
1727
Computer Organization- Memory Addressing
For 16 bit address-bus, if an 8 K RAM chip is selected when $A_{13}, A_{14}$ and $A_{15}$ address bits are all one, then what is the range of the memory address? Options - a) 2 b) 3 c) 4 d) 5
For 16 bit address-bus, if an 8 K RAM chip is selected when $A_{13}, A_{14}$ and $A_{15}$ address bits are all one, then what is the range of the memory address?Options -...
Devwritt
1.4k
views
Devwritt
asked
Apr 12, 2017
CO and Architecture
co-and-architecture
ram
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–
0
votes
1
answer
1728
program-status-word, computer-architecture
What are the various values of Carry(C), Overflow (V) and Sign (S) flag in case of signed unsigned, 2's complement addition and subtraction. When are they set to 0 / 1 and what do they mean ?
What are the various values of Carry(C), Overflow (V) and Sign (S) flag in case of signed unsigned, 2's complement addition and subtraction. When are they set to 0 / 1 an...
Arunav Khare
588
views
Arunav Khare
asked
Apr 5, 2017
CO and Architecture
co-and-architecture
program-status-word
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–
0
votes
2
answers
1729
ISRO 2015- Main memory [EE]
Techniques that automatically move program and data blocks into physical main memory when they are required for execution are called (a) Main memory techniques (b) Cache memory techniques (c) Virtual memory techniques (d) Associate memory techniques
Techniques that automatically move program and data blocks into physical main memory when they are required for execution are called(a) Main memory techniques(b) Cache me...
sh!va
1.1k
views
sh!va
asked
Mar 10, 2017
CO and Architecture
isro-ee
co-and-architecture
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2
votes
1
answer
1730
False sharing in cache Line
Here is pseudo code for a multiprocessing purpose: set_num_threads(NUM_THREADS); double sum=0.0; sum_local[NUM_THREADS]; parallel region { int this_thread_id = get_thread_number(); // returns 0 to (no_of_threads-1) sum_local[this_thread_id] = 0.0; for (i ... I think frequent DRAM write back causing the problem, but not very clear, though. please explain a bit. @Arjun Sir
Here is pseudo code for a multiprocessing purpose:set_num_threads(NUM_THREADS); double sum=0.0; sum_local[NUM_THREADS]; parallel region { int this_thread_id = get_thread_...
dd
1.1k
views
dd
asked
Mar 5, 2017
CO and Architecture
co-and-architecture
cache-memory
non-gate
descriptive
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–
0
votes
1
answer
1731
8086 instructions
In x86, which of the following is not executed by itself ? (A) cld (B) rep (C) std (D) nop
In x86, which of the following is not executed by itself ?(A) cld(B) rep(C) std(D) nop
Beyonder
1.4k
views
Beyonder
asked
Mar 4, 2017
CBSE/UGC NET
8086
co-and-architecture
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0
votes
1
answer
1732
8086 .exe and .com programs
(8086 .exe and .com programs) : Which of the following statements is false ? (A) An .exe program on disk starts with a 512-byte header file, but not a .com program (B) A .com program uses separate segments for code, data and the stack ( ... program can be converted to a .com program (D) Generally, a .com program is simpler than a .exe program with the same functionality
(8086 .exe and .com programs) : Which of the following statements is false ?(A) An .exe program on disk starts with a 512-byte header file, but nota .com program(B) A .co...
Beyonder
1.1k
views
Beyonder
asked
Mar 4, 2017
Digital Logic
8086
co-and-architecture
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–
0
votes
1
answer
1733
8086 assembly language
In 8086 assembly language, which of the following is not in the category of reserved words ? (A) directive (B) predefined symbol (C) operator (D) label
In 8086 assembly language, which of the following is not in the category of reserved words ?(A) directive(B) predefined symbol(C) operator(D) label
Beyonder
1.4k
views
Beyonder
asked
Mar 4, 2017
Digital Logic
8086
co-and-architecture
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–
0
votes
2
answers
1734
ISRO 2006- ECE
If the memory chip size is 256 x 1 bits, then the number of chips required to make up 1K bytes of memory is a) 32 b) 24 c) 12 d) 8
If the memory chip size is 256 x 1 bits, then the number of chips required to make up 1K bytes of memory isa) 32b) 24c) 12d) 8
sh!va
1.3k
views
sh!va
asked
Mar 3, 2017
CO and Architecture
isro-ece
co-and-architecture
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–
0
votes
1
answer
1735
ISRO 2006-ECE WAIT states
WAIT states are used to a) Make the processor wait during a DMA operation b) Make the processor wait during a power interrupt processing c) Make the processor wait during a power shutdown d) Interface slow peripherals to the processor
WAIT states are used toa) Make the processor wait during a DMA operationb) Make the processor wait during a power interrupt processingc) Make the processor wait during a ...
sh!va
1.3k
views
sh!va
asked
Mar 3, 2017
CO and Architecture
isro-ece
co-and-architecture
+
–
0
votes
1
answer
1736
ISRO 2007- ECE Program Counter
When a program is being executed in an 8085 microprocessor, its Program Counter contains a) The number of instructions in the current program that have already been executed b) The total number of instructions in the program being executed c) ... of the instruction that is being currently executed d) The memory address of the instruction that is to be executed next
When a program is being executed in an 8085 microprocessor, its Program Counter containsa) The number of instructions in the current program that have already been execut...
sh!va
770
views
sh!va
asked
Mar 3, 2017
CO and Architecture
isro-ece
co-and-architecture
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–
0
votes
1
answer
1737
ISRO 2007- ECE Time division MUX
In time division multiplexing a) Time is doubled between bits of a byte b) Time slicing at CPU level takes place c) Total time available in the channel is divided between several users and each users is allotted a time slice. d) None of the above
In time division multiplexinga) Time is doubled between bits of a byteb) Time slicing at CPU level takes placec) Total time available in the channel is divided between se...
sh!va
443
views
sh!va
asked
Mar 3, 2017
CO and Architecture
isro-ece
co-and-architecture
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–
0
votes
1
answer
1738
ISRO 2007-ECE Memory
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is a) 2 b) 4 c) 8 d) 16
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to d...
sh!va
4.5k
views
sh!va
asked
Mar 3, 2017
CO and Architecture
isro-ece
co-and-architecture
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–
0
votes
1
answer
1739
ISRO 2008-ECE Computer architecture
Digital signal processors use a computer architecture derived from (a) Harvard Architecture (b) Von-Neumann Architecture (c) Cray Architecture (d) None of the above
Digital signal processors use a computer architecture derived from(a) Harvard Architecture(b) Von-Neumann Architecture(c) Cray Architecture(d) None of the above
sh!va
611
views
sh!va
asked
Mar 2, 2017
CO and Architecture
isro-ece
co-and-architecture
+
–
1
votes
2
answers
1740
ISRO 2008-ECE Pipeline
Assuming ideal conditions, the speed up obtained from a balanced N stage pipeline is (a) $2N$ (b) $N^ 2$ (c) $N$ (d) $N!$
Assuming ideal conditions, the speed up obtained from a balanced N stage pipeline is(a) $2N$(b) $N^ 2$(c) $N$(d) $N!$
sh!va
642
views
sh!va
asked
Mar 2, 2017
CO and Architecture
isro-ece
co-and-architecture
pipelining
+
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