Recent questions tagged co-and-architecture

0 votes
1 answer
1711
How we define big endian and little endian, word alignment ?
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1 answer
1712
0 votes
0 answers
1713
Consider READ and WRITE bits:a) Both are written by CPUb) Both are written by peripheralc) READ bit is written by peripheral while WRITE bit is written by CPUd) WRITE bit...
1 votes
1 answer
1714
2 votes
1 answer
1715
1 votes
1 answer
1716
What is the difference between DM controller and micropcessor. Block diagram of the device seems similar , both contains pins. Then how they are different from each other...
0 votes
1 answer
1717
How this average access time derived ?Tavg=hC+(1-h)M.Please explain. M not getting this.
0 votes
1 answer
1718
Anyone is having standard book for coa hamachare 7 edition pls share link.
2 votes
1 answer
1719
Cache size = 512KB ; Tag size = 7, Find out main memory size and tag directory. Given it is 8-way set associative .
2 votes
2 answers
1720
what is the difference between a "Block" and "Sector" in Hard disk ..??? Are they both same ???
0 votes
1 answer
1722
0 votes
1 answer
1723
0 votes
1 answer
1725
1 votes
2 answers
1726
Write the smallest real number greater than 6.25 that can be represented in the IEEE-754 single precision format (32-bit word with 1 sign bit and 8-bit exponent).
0 votes
1 answer
1727
For 16 bit address-bus, if an 8 K RAM chip is selected when $A_{13}, A_{14}$ and $A_{15}$ address bits are all one, then what is the range of the memory address?Options -...
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1 answer
1728
What are the various values of Carry(C), Overflow (V) and Sign (S) flag in case of signed unsigned, 2's complement addition and subtraction. When are they set to 0 / 1 an...
0 votes
2 answers
1729
0 votes
1 answer
1731
In x86, which of the following is not executed by itself ?(A) cld(B) rep(C) std(D) nop
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1 answer
1733
In 8086 assembly language, which of the following is not in the category of reserved words ?(A) directive(B) predefined symbol(C) operator(D) label
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2 answers
1734
If the memory chip size is 256 x 1 bits, then the number of chips required to make up 1K bytes of memory isa) 32b) 24c) 12d) 8
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1 answer
1735
WAIT states are used toa) Make the processor wait during a DMA operationb) Make the processor wait during a power interrupt processingc) Make the processor wait during a ...
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1 answer
1737
0 votes
1 answer
1738
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to d...
0 votes
1 answer
1739
Digital signal processors use a computer architecture derived from(a) Harvard Architecture(b) Von-Neumann Architecture(c) Cray Architecture(d) None of the above
1 votes
2 answers
1740
Assuming ideal conditions, the speed up obtained from a balanced N stage pipeline is(a) $2N$(b) $N^ 2$(c) $N$(d) $N!$