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Recent questions tagged co-and-architecture

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1771
8086 instructions
In x86, which of the following is not executed by itself ? (A) cld (B) rep (C) std (D) nop
In x86, which of the following is not executed by itself ?(A) cld(B) rep(C) std(D) nop
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1773
8086 assembly language
In 8086 assembly language, which of the following is not in the category of reserved words ? (A) directive (B) predefined symbol (C) operator (D) label
In 8086 assembly language, which of the following is not in the category of reserved words ?(A) directive(B) predefined symbol(C) operator(D) label
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2 answers
1774
ISRO 2006- ECE
If the memory chip size is 256 x 1 bits, then the number of chips required to make up 1K bytes of memory is a) 32 b) 24 c) 12 d) 8
If the memory chip size is 256 x 1 bits, then the number of chips required to make up 1K bytes of memory isa) 32b) 24c) 12d) 8
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1775
ISRO 2006-ECE WAIT states
WAIT states are used to a) Make the processor wait during a DMA operation b) Make the processor wait during a power interrupt processing c) Make the processor wait during a power shutdown d) Interface slow peripherals to the processor
WAIT states are used toa) Make the processor wait during a DMA operationb) Make the processor wait during a power interrupt processingc) Make the processor wait during a ...
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1777
ISRO 2007- ECE Time division MUX
In time division multiplexing a) Time is doubled between bits of a byte b) Time slicing at CPU level takes place c) Total time available in the channel is divided between several users and each users is allotted a time slice. d) None of the above
In time division multiplexinga) Time is doubled between bits of a byteb) Time slicing at CPU level takes placec) Total time available in the channel is divided between se...
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1778
ISRO 2007-ECE Memory
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is a) 2 b) 4 c) 8 d) 16
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to d...
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1779
ISRO 2008-ECE Computer architecture
Digital signal processors use a computer architecture derived from (a) Harvard Architecture (b) Von-Neumann Architecture (c) Cray Architecture (d) None of the above
Digital signal processors use a computer architecture derived from(a) Harvard Architecture(b) Von-Neumann Architecture(c) Cray Architecture(d) None of the above
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2 answers
1780
ISRO 2008-ECE Pipeline
Assuming ideal conditions, the speed up obtained from a balanced N stage pipeline is (a) $2N$ (b) $N^ 2$ (c) $N$ (d) $N!$
Assuming ideal conditions, the speed up obtained from a balanced N stage pipeline is(a) $2N$(b) $N^ 2$(c) $N$(d) $N!$
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1783
ISRO 2008- ECE Computer architecture
------ machines tend to make use of internal resources of the processor, a rich set of registers and a pipelined organization. (a) CISC (b) Parallel processor (c) RISC (d) Array processor
machines tend to make use of internal resources of the processor, a rich set of registers and a pipelined organization.(a) CISC(b) Parallel processor(c) RISC(d) Array...
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1784
ISRO 2008-ECE array processor
An array processor is a machine (a) SIMD (b) MIMD (c) SISD (d) MISD
An array processor is a machine(a) SIMD(b) MIMD(c) SISD(d) MISD
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1785
ISRO 2008-ECE Computer Architecture
Micro programming refers to (a) Emulation (b) Programming at micro level (c) The use of storage to implement the control unit (d) Array processing
Micro programming refers to(a) Emulation(b) Programming at micro level(c) The use of storage to implement the control unit(d) Array processing
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1786
ISRO 2008- ECE Computer Architecture
The performance gain that can be obtained by improving some portion of a computer can be calculated using (a) Moore's law (b) Djikstra's algorithm (c) Amdahl's law (d) Murphy's law
The performance gain that can be obtained by improving some portion of a computer can be calculated using(a) Moore's law(b) Djikstra's algorithm(c) Amdahl's law(d) Murphy...
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1787
if one computer transmistion afile size 38400 bytes to other computerhow many frames of data transfer
datatransmition speed bps =9600data bit 8parity bit =evenstop bit=2 start bit 1if one computer transmistion afile size 38400 bytes to other computerhow many frames of dat...
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1788
ISRO 2008-ECE Digital Logic
Which type of memory has fast erase and write times (a) EPROM (b) EEPROM (c) Flash memory (d) None of these
Which type of memory has fast erase and write times(a) EPROM(b) EEPROM(c) Flash memory(d) None of these
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1789
ISRO 2008-ECE Cache Memory
The advantage of write (copy) back data cache organization over write through organization is (a) Main memory consistency (b) Write allocate on write miss (c) Less memory bandwidth (d) Higher capacity requirement
The advantage of write (copy) back data cache organization over write through organization is(a) Main memory consistency(b) Write allocate on write miss(c) Less memory ba...
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1791
ISRO 2009- ECE Computer architecture
An 8-bit microcontroller has an external RAM with the memory map from 8000H to 9FFFH. The number of bytes this RAM can store is a) 8193 b) 8192 c) 8191 d) 8000
An 8-bit microcontroller has an external RAM with the memory map from 8000H to 9FFFH.The number of bytes this RAM can store isa) 8193b) 8192c) 8191d) 8000
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1792
ISRO 2009-ECE : Computer Architecture
A micro controller differs from a microprocessor in terms of a) I/O interfaces and instruction decoding b) Memory configuration and I/O interfaces c) Data bus width and clock speed d) Memory configuration and instruction decoding
A micro controller differs from a microprocessor in terms ofa) I/O interfaces and instruction decodingb) Memory configuration and I/O interfacesc) Data bus width and cloc...
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1794
ISRO 2009- ECE Computer Architecture
Consider the following program for 8085 XRA A LXI B, 0007H LOOP : DCX B JNZ LOOP The loop will be executed a) 8 times b) once c) 7 times d) infinite times
Consider the following program for 8085 XRA A LXI B, 0007HLOOP : DCX B JNZ LOOPThe loop will be executeda) 8 timesb) on...
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1796
ISRO 2010-ECE Cache memory
A microprocessor has a cache memory with access time of 2 ns and a main memory with access time of 10 ns. If the cache miss ratio is 0.6, what is the average memory access time? a) 6.8 ns b) 6 ns c) 5.2 ns d) 12 ns
A microprocessor has a cache memory with access time of 2 ns and a main memory with access time of 10 ns. If the cache miss ratio is 0.6, what is the average memory acces...
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1798
ISRO 2011-ECE Computer Architecture
When a microprocessor interfaces with a peripheral or memory device, the normal timing of the microprocessor may need to be altered by introducing____ a. Latching b. Wait states c. Tristate logics d. None of the above
When a microprocessor interfaces with a peripheral or memory device, the normal timing of the microprocessor may need to be altered by introducing____a. Latchingb. Wait s...
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