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Recent questions tagged co-and-architecture
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181
Computer Organization and Architecture
Consider two cache organization which are byte addressable.In both cache organization cache size is 64 KB with 32-byte block.The first cache organization is direct mapped while the other is 4-way set associative.Physical address is of size ... latency of OR gate is 1 is.Find sum the latency of the direct mapped organization and set associative organization?
Consider two cache organization which are byte addressable.In both cache organization cache size is 64 KB with 32-byte block.The first cache organization is direct mapped...
Sourin Kundu
266
views
Sourin Kundu
asked
Jan 27, 2023
CO and Architecture
co-and-architecture
computer-architecture
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0
answers
182
COA
Which of the following is/are true for a CPU which does not have any stack pointer registers? A Interrupts are not possible. B All subroutine calls and interrupts are possible. C It cannot have nested subroutines call. D It cannot have subroutine call instruction.
Which of the following is/are true for a CPU which does not have any stack pointer registers?A Interrupts are not possible. B All subroutine calls and interrupts are po...
Overflow04
479
views
Overflow04
asked
Jan 24, 2023
CO and Architecture
co-and-architecture
self-doubt
interrupts
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2
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1
answer
183
Practice Question Unacademy - Vishvadeep Gothi
Consider a system that supports 2-address, 1-address, and 0-address instructions. The system has 'i' bits instructions and 'a' bits addresses. If there are 'x' 2-address instructions and 'y' 1-address instructions then which of the following is the maximum ... $2 ^ i - 2 ^ a * x - y * 2 ^ a$
Consider a system that supports 2-address, 1-address, and 0-address instructions. The system has 'i' bits instructions and 'a' bits addresses. If there are 'x' 2-address ...
bsreevidya
441
views
bsreevidya
asked
Jan 22, 2023
CO and Architecture
co-and-architecture
machine-instruction
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1
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0
answers
184
NPTEL Assignment
Question : i. CISC architecture a. Symmetric registers ii. RISC architecture b. Multiple memory references iii. Misalignment c. Condition code register iv. Static data d. Single memory reference Options: i-a,ii-c,iii-b,iv-d i-c,ii-a,iii-b,iv-d i-c,ii-a,iii-b,iv-b i-c,ii-a,iii-d,iv-b
Question : i. CISC architecture a. Symmetric registersii. RISC architecture b. Multiple memory referencesiii. Misalignment c. Condition code regis...
lalitver10
228
views
lalitver10
asked
Jan 12, 2023
CO and Architecture
nptel-quiz
co-and-architecture
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0
votes
1
answer
185
#COA #CacheMemory
What is the default access method of Cache Memory? Simultaneous or Hierarchical?
What is the default access method of Cache Memory? Simultaneous or Hierarchical?
iamsubhrajit
396
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iamsubhrajit
asked
Dec 31, 2022
CO and Architecture
co-and-architecture
cache-memory
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0
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1
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186
Addressing Modes
When we write MOV #1000 , it means we are writing the value 1000 into the accumulator. But when we write MOV 1000 here 1000 refers to address of what ? register or MM ? (knowing that MOV works only between registers).
When we write MOV #1000 , it means we are writing the value 1000 into the accumulator. But when we write MOV 1000 here 1000 refers to address of what ? register or MM ? (...
Aaryan_Sharma
370
views
Aaryan_Sharma
asked
Dec 30, 2022
CO and Architecture
co-and-architecture
addressing-modes
goclasses
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2
votes
0
answers
187
cache miss question
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?
h4kr
511
views
h4kr
asked
Dec 27, 2022
CO and Architecture
co-and-architecture
cache-memory
multilevel-cache
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2
votes
3
answers
188
Difference b/w cache & TLB
What is the difference b/w cache & TLB? TLB is stored in cache too right? TLB helps in addressing like a faster version of page table while speaking of cache, it directly stores the process page directly right?
What is the difference b/w cache & TLB? TLB is stored in cache too right? TLB helps in addressing like a faster version of page table while speaking of cache, it directly...
h4kr
534
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h4kr
asked
Dec 27, 2022
CO and Architecture
computer-architecture
co-and-architecture
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0
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1
answer
189
PERSONAL DOUBT [PIPELINING]
So I know pipelining has 5 stages: IF, ID, EX, MA, WB. Now the question is if I have a program of few instruction which has both ALU operation and LOAD/store operation in any sequence. So tell me among the 5 stages how many stages will be reqiured for ALU and how many for LOAD/STORE.
So I know pipelining has 5 stages: IF, ID, EX, MA, WB.Now the question is if I have a program of few instruction which has both ALU operation and LOAD/store operation in ...
DAWID15
358
views
DAWID15
asked
Dec 26, 2022
CO and Architecture
co-and-architecture
pipelining
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0
votes
2
answers
190
Arihant Gate Tutor
If a processor has 32-bit virtual address, 28-bit physical address, 2 kb pages. How many bits are required for the virtual, physical page number? 17, 21 21, 17 6, 10 None The answer given is b. 21, 17
If a processor has 32-bit virtual address, 28-bit physical address, 2 kb pages. How many bits are required for the virtual, physical page number?17, 2121, 176, 10NoneThe ...
arkaprava_gupta
1.4k
views
arkaprava_gupta
asked
Dec 23, 2022
CO and Architecture
co-and-architecture
virtual-memory
operating-system
registers
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