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Recent questions tagged co-and-architecture
0
votes
1
answer
1831
Self doubt
DIfference between Static single assignment, 3 address code , 3 address instruction? How these 3 are different in representation?
DIfference between Static single assignment, 3 address code , 3 address instruction?How these 3 are different in representation?
vaishali jhalani
460
views
vaishali jhalani
asked
Feb 6, 2017
CO and Architecture
co-and-architecture
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–
20
votes
2
answers
1832
COA DMA doubt
What is formula for % of time CPU gets blocked?? Is it X(X+Y) or X/Y only??? What is formula for % of time CPU is consumed in Interuppt driven IO??? Formula for % of CPU slow down in interrupt driven IO???
What is formula for % of time CPU gets blocked??Is it X(X+Y) or X/Y only???What is formula for % of time CPU is consumed in Interuppt driven IO??? Formula for % of CPU s...
Rahul Jain25
10.6k
views
Rahul Jain25
asked
Feb 6, 2017
CO and Architecture
co-and-architecture
dma
interrupts
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–
1
votes
1
answer
1833
Mock Test
The answer given is D) Why is option 3 and 4 correct ? In 4) if there is a branch instruction , it can lead to stalls ,so how will it improve the execution ?
The answer given is D) Why is option 3 and 4 correct ?In 4) if there is a branch instruction , it can lead to stalls ,so how will it improve the execution ?
Harsh181996
325
views
Harsh181996
asked
Feb 5, 2017
CO and Architecture
pipelining
co-and-architecture
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–
5
votes
1
answer
1834
COA pipeline doubt
I) In a 4 stage pipeline processor, if each stage takes 4 cycles then what is CPI in case of successfull pipeline??? II) In a 4 stage pipeline processor, if each stage takes 2,3,4,5 cycles respectively then what is CPI in case ... are branch imstructions and branch address is available in 3rd stage then what should be branch pelanty??(In both the implementations mentioned above)
I) In a 4 stage pipeline processor, if each stage takes 4 cycles then what is CPI in case of successfull pipeline???II) In a 4 stage pipeline processor, if each stage tak...
Rahul Jain25
946
views
Rahul Jain25
asked
Feb 5, 2017
CO and Architecture
co-and-architecture
pipelining
stall
branch-conditional-instructions
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–
1
votes
1
answer
1835
Geeksforgeeks MOCK II COA
Can anyone solve this?? Doubts: Branch penalty should be 2. right? and what is the branch penalty for unconditional branch?
Can anyone solve this??Doubts: Branch penalty should be 2. right?and what is the branch penalty for unconditional branch?
Jason_Roy
768
views
Jason_Roy
asked
Feb 4, 2017
CO and Architecture
geeksforgeeks-test-series
co-and-architecture
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0
votes
0
answers
1836
Memory Hierarchy
How to identify from the question, whether to add the access times of memories which are higher in hierarchy in case of miss?
How to identify from the question, whether to add the access times of memories which are higher in hierarchy in case of miss?
Manoj Majumdar
502
views
Manoj Majumdar
asked
Feb 4, 2017
CO and Architecture
co-and-architecture
memory-hierarchy
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–
0
votes
1
answer
1837
MadeEasy Subject Test: CO & Architecture - Instruction Execution
vaishali jhalani
419
views
vaishali jhalani
asked
Feb 4, 2017
CO and Architecture
co-and-architecture
made-easy-test-series
instruction-execution
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–
1
votes
1
answer
1838
Pipeline
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output present in 4th stage ALU instruction output ... What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resol...
srestha
1.7k
views
srestha
asked
Feb 4, 2017
CO and Architecture
co-and-architecture
pipelining
operand-forwarding
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–
0
votes
1
answer
1839
Memory addressing
The cache can hold 512 KB. Data is transferred between main memory and cache in blocks of 16 byte each. The main memory consist 4 Gbyte. If the cache memory is 2 way set associative then the hexadecimal main memory address (ABCABCCBA)H is mapped to which cache set? I think answer should be 3CCB
The cache can hold 512 KB. Data is transferred between main memory and cache in blocks of 16 byte each. The main memory consist 4 Gbyte. If the cache memory is 2 way set ...
Pankaj Joshi
1.3k
views
Pankaj Joshi
asked
Feb 3, 2017
CO and Architecture
co-and-architecture
cache-memory
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0
votes
0
answers
1840
MadeEasy Subject Test: CO & Architecture - Io Handling
jatinmittal199510
421
views
jatinmittal199510
asked
Feb 2, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
io-handling
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–
0
votes
0
answers
1841
madeesy test series
Explain?
Explain?
naveen81
171
views
naveen81
asked
Feb 2, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
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–
1
votes
2
answers
1842
MadeEasy Test Series
AmitPatil
626
views
AmitPatil
asked
Feb 2, 2017
CO and Architecture
co-and-architecture
dma
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–
4
votes
4
answers
1843
Interrupt I/O
Consider a system employing interrupt driven input/output for a particular device that transfers data at an average of 16 KB/s on a continuous basis. Assume that interrupt processing takes 50 μsec (i.e., the jump to the interrupt service routine (ISR), ... of processor time is consumed by this input/output device if it interrupt for every byte is _______ (Upto 3 decimal places).
Consider a system employing interrupt driven input/output for a particular device that transfers data at an average of 16 KB/s on a continuous basis. Assume that interrup...
Pankaj Joshi
6.7k
views
Pankaj Joshi
asked
Feb 2, 2017
CO and Architecture
co-and-architecture
interrupts
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–
1
votes
1
answer
1844
what are the Computer Organization important type of numerical type question?
In Operating System we have process scheduling and page fault numerical which are hot favorite and comes very often. What are the hot favorite questions in CO and Architecture?
In Operating System we have process scheduling and page fault numerical which are hot favorite and comes very often. What are the hot favorite questions in CO and Archite...
PieChuckerr
798
views
PieChuckerr
asked
Feb 2, 2017
CO and Architecture
co-and-architecture
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–
1
votes
0
answers
1845
general query about the assumption of values of given K or M like for 30KB or 30KB what to take k= 1^3 or 1024
in COA whenever I m doing any some in mock tests... where its given data like 30KB or 60MB which value to be considered? for K and M here??I mean when the answer is in ms...
S Ram
332
views
S Ram
asked
Feb 1, 2017
Others
general
co-and-architecture
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0
votes
1
answer
1846
MadeEasy Subject Test: CO & Architecture - Instruction Execution
Is this the correct answer? Explain. (as word size is 32 bits)
Is this the correct answer? Explain. (as word size is 32 bits)
naveen81
301
views
naveen81
asked
Feb 1, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
instruction-execution
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–
0
votes
1
answer
1847
MadeEasy Subject Test: CO & Architecture - Addressing Modes
vaishali jhalani
358
views
vaishali jhalani
asked
Feb 1, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
addressing-modes
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–
1
votes
1
answer
1848
MadeEasy Workbook: CO & Architecture - Clock Frequency
Smriti012
380
views
Smriti012
asked
Feb 1, 2017
CO and Architecture
made-easy-booklet
co-and-architecture
clock-frequency
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–
0
votes
1
answer
1849
MadeEasy Workbook: CO & Architecture - Clock Frequency
Smriti012
450
views
Smriti012
asked
Feb 1, 2017
CO and Architecture
co-and-architecture
made-easy-booklet
clock-frequency
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–
1
votes
2
answers
1850
Testbook Test Series: CO & Architecture - Microprogramming
# is it correct answer??? plz check
# is it correct answer??? plz check
Hradesh patel
494
views
Hradesh patel
asked
Jan 31, 2017
CO and Architecture
co-and-architecture
microprogramming
testbook-test-series
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–
12
votes
4
answers
1851
MadeEasy Subject Test: CO & Architecture - Dma
Consider $1 \text{ MBPS}$ hard disk is interfaced to the processor in a cycle stealing mode of $\text{DMA}$ whenever $64$ bytes of the data is available in the buffer then it is transferred to the main memory. Processor word length is $64$ bits ... $\text{CPU}$ time is consumed for the $\text{DMA}$ operation is ________ (in $\%$).
Consider $1 \text{ MBPS}$ hard disk is interfaced to the processor in a cycle stealing mode of $\text{DMA}$ whenever $64$ bytes of the data is available in the buffer the...
vaishali jhalani
4.1k
views
vaishali jhalani
asked
Jan 30, 2017
CO and Architecture
co-and-architecture
made-easy-test-series
dma
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–
2
votes
3
answers
1852
Pipeline: Calculate average instruction execution time
An instruction pipeline has five stages with stage latencies 1 ns, 2ns, 5 ns, 2ns, and 0.5 ns, respectively. A program has 10% branch instructions which execute in the fourth stage and produce the next instruction pointer at the end of the fourth stage. Calculate the average instruction execution time:
An instruction pipeline has five stages with stage latencies 1 ns, 2ns, 5 ns, 2ns, and 0.5 ns, respectively. A program has 10% branch instructions which execute in the fo...
sh!va
6.0k
views
sh!va
asked
Jan 30, 2017
CO and Architecture
co-and-architecture
pipelining
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–
13
votes
0
answers
1853
Doubts in PIpelining
1. In case of no data forwarding can we use split phase. 2. Should we have to consider data forwarding, According to options? 3. Where we can use split phase??( I know about WB-ID and EX-ID) @Pc @Arjun Sir Please answer..
1. In case of no data forwarding can we use split phase.2. Should we have to consider data forwarding, According to options?3. Where we can use split phase??( I know abou...
vaishali jhalani
2.4k
views
vaishali jhalani
asked
Jan 30, 2017
CO and Architecture
co-and-architecture
pipelining
+
–
0
votes
0
answers
1854
CO and ARCHITECTURE
WHY WE HAVE TO MULTIPLY THE I4, I5,I6,I7, I8 5 times?
WHY WE HAVE TO MULTIPLY THE I4, I5,I6,I7, I8 5 times?
vishwa ratna
262
views
vishwa ratna
asked
Jan 30, 2017
CO and Architecture
co-and-architecture
+
–
0
votes
1
answer
1855
Cache Associative memory
A cache is having 64KB capacity 128 byte lines and is 4-way set associative the sytem containing the cache uses 32 bit address. How many sets does the cache have ?
A cache is having 64KB capacity 128 byte lines and is 4-way set associative the sytem containing the cache uses 32 bit address. How many sets does the cache have ?
vishal8492
5.3k
views
vishal8492
asked
Jan 29, 2017
CO and Architecture
co-and-architecture
cache-memory
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–
0
votes
2
answers
1856
Pipeline (With split phase- With forwarding)
A $5-$ stage pipelined processor has IF,ID,EX,MEM and WB . WB stage operation is divided into two parts. In the first part register write operation and in second part register read operation is performed. The latency of those stages are $300,400,500,500,300$ ... SUB $R_{1},R_{7},R_{4}$ $R_{1} <- R_{7} - R_{4}$ The program execution time__________ns?
A $5-$ stage pipelined processor has IF,ID,EX,MEM and WB . WB stage operation is divided into two parts. In the first part register write operation and in second part reg...
monty
1.5k
views
monty
asked
Jan 29, 2017
CO and Architecture
co-and-architecture
operand-forwarding
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–
0
votes
0
answers
1857
testbook
Consider the following code Register int i,j; Register float x,y,A[64][64],B[64][64]; For (i=0;i<64;i++) //s1(4 cycles) { For (j=0;j<64;j++) //s2(4 cycles) { x=x+A[i][j]; //s3(10 cycles) } For (j=0; ... both start at the cache line boundaries Number of cycles for each statement invocation is provided in the above code . How many cycles does the above code fragment take for execution?
Consider the following codeRegister int i,j;Register float x,y,A[64][64],B[64][64];For (i=0;i<64;i++) //s1(4 cycles){For (j=0;j<64;j++) ...
Pankaj Joshi
247
views
Pankaj Joshi
asked
Jan 29, 2017
CO and Architecture
testbook-test-series
co-and-architecture
+
–
3
votes
2
answers
1858
Set associative cache
Consider a 16-way set-associative cache with data words are 64 bits long and words are addressed to the half-word. The cache holds 2 Mbytes of data and each block holds 16 data words. Physical addresses are 64 bits long, How many bits of tag, index, ... to this cache? Can someone please explain what do we we mean by words are addressed to the half-word in the above question?
Consider a 16-way set-associative cache with data words are 64 bits long and words are addressed to the half-word. The cache holds 2 Mbytes of data and each block holds 1...
Aakanchha
3.8k
views
Aakanchha
asked
Jan 29, 2017
CO and Architecture
co-and-architecture
+
–
7
votes
1
answer
1859
vertical microprogrammed
A vertical microprogrammed control unit supports 256 instructions. The system is using 8 flag conditions and contains 48 control signals. Each instruction on average requires 1 micro operation. What is the approximate size of control memory in bytes?
A vertical microprogrammed control unit supports 256 instructions. The system is using 8 flag conditions and contains 48 control signals. Each instruction on average requ...
Supremo
6.0k
views
Supremo
asked
Jan 28, 2017
CO and Architecture
co-and-architecture
microprogramming
control-unit
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–
1
votes
2
answers
1860
CPI.......
Is CPI of non pipeline processor 6, means non pipeline processor has 6 stages? ----------------------------------------------------------------------------------------------------------------------- ... 4 GHz and an average CPI of 6. System is enhanced to a 8 stage pipelined processor. The clock rate is reduced to 2 GHz in the new processor. Speedup of a pipelined processor is _________.
Is CPI of non pipeline processor 6, means non pipeline processor has 6 stages? -Consider a non-pipeline system has a clock rate 4 GHz and an average CPI of...
srestha
839
views
srestha
asked
Jan 28, 2017
CO and Architecture
pipelining
co-and-architecture
+
–
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