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Recent questions tagged co-and-architecture
1
votes
5
answers
1861
MadeEasy Subject Test: CO & Architecture - Io Handling
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the device interface register and CPU or memory is ... the device under interrupt mode over operating it under program-controlled mode is __________ . (Upto 1 decimal places)
A device with data transfer rate of 8 KBps is connected to a CPU. Data is transferred bytewise. Let interrupt overhead be 2 μsec. The byte transfer time between the devi...
Pankaj Joshi
2.8k
views
Pankaj Joshi
asked
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
io-handling
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–
1
votes
2
answers
1862
MadeEasy Subject Test: CO & Architecture - Dma
I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. before and after that it can do its own work. Where am I wrong?
I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. bef...
sidsunny
859
views
sidsunny
asked
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
dma
+
–
0
votes
0
answers
1863
madeeasy
How are the delay registers to be considered?
How are the delay registers to be considered?
sidsunny
231
views
sidsunny
asked
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
+
–
0
votes
1
answer
1864
madeeasy
My question is how does cache block size affect the placement of blocks/addresses in cache? Example: here 2 word cache block vs 1 word cache block size. What will be the difference?
My question is how does cache block size affect the placement of blocks/addresses in cache? Example: here 2 word cache block vs 1 word cache block size. What will be the ...
sidsunny
301
views
sidsunny
asked
Jan 26, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
1
votes
1
answer
1865
pipeline bypassing
A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, OF and WO stages takes 1 clock cycle each for any instruction. The PO ... number of clock cycles needed to execute the following sequence of instruction where operand forwarding from WO to PO and PO to OF is used
A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, O...
Pankaj Joshi
2.2k
views
Pankaj Joshi
asked
Jan 25, 2017
CO and Architecture
operand-forwarding
co-and-architecture
pipelining
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–
0
votes
0
answers
1866
MadeEasy Subject Test: CO & Architecture - Dma
vaishali jhalani
321
views
vaishali jhalani
asked
Jan 25, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
dma
+
–
2
votes
1
answer
1867
CO Test 1 q31
Consider a CPU that executes at a clock rate of 200MHz(5ns per cycle) with a single level cache. CPI execution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% arithmetic/Logical, 30% load/store, 20% control instruction. Assume the cache miss rate is 15% and a miss penalty of 50 cycles. The number of times cpu with ideal memory is faster when no miss occurs _______
Consider a CPU that executes at a clock rate of 200MHz(5ns per cycle) with a single level cache. CPI execution i.e. CPI with ideal memory is 1.1. Instruction mix are 50% ...
Vasu_gate2017
2.6k
views
Vasu_gate2017
asked
Jan 25, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
13
votes
1
answer
1868
Discussions on Floating Point Represenation
Question 1 Explain What is Denormalized Number Give Example Give Representation in IEEE 754 and excess 64 (if any) Question 2 How to Convert $(12.625)_10$ $(12.625)_10 \Leftrightarrow (1100.101)_2$ to IEEE ... Precision (With Normalization) IEEE 754 Single Precision (Without Normalization) Excess-64 (With Normalization) Excess-64 (Without Normalization)
Question 1 Explain What is Denormalized NumberGive ExampleGive Representation in IEEE 754 and excess 64 (if any)Question 2 How to Convert $(12.625)_10$$(12.625)_10 \Left...
pC
2.8k
views
pC
asked
Jan 25, 2017
CO and Architecture
floating-point-representation
ieee-representation
co-and-architecture
number-representation
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–
0
votes
1
answer
1869
MadeEasy Subject Test: CO & Architecture - Cache Memory
debanjan sarkar
202
views
debanjan sarkar
asked
Jan 24, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
0
votes
0
answers
1870
MadeEasy Subject Test: CO & Architecture - Cache Memory
debanjan sarkar
192
views
debanjan sarkar
asked
Jan 24, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
+
–
0
votes
1
answer
1871
MadeEasy Subject Test: CO & Architecture - Dma
debanjan sarkar
340
views
debanjan sarkar
asked
Jan 24, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
dma
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–
0
votes
2
answers
1872
MadeEasy Subject Test: CO & Architecture - Addressing Modes
Which signed representation has to be taken?
Which signed representation has to be taken?
vaishali jhalani
497
views
vaishali jhalani
asked
Jan 24, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
addressing-modes
+
–
3
votes
1
answer
1873
MadeEasy Subject Test: CO & Architecture - Pipelining
Kai
442
views
Kai
asked
Jan 24, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
+
–
1
votes
1
answer
1874
Test by Bikram | Mock GATE | Test 2 | Question: 49
Consider the following sequence of instructions intended for execution on a stack machine. Each arithmetic operation pops the second operand, then pops the first operand, operates on them, and then pushes the result back onto the stack. Push b Push x Add ... of execution, the stack is empty. I and III only II and III only II only I, II, and III
Consider the following sequence of instructions intended for execution on a stack machine. Each arithmetic operation pops the second operand, then pops the first operand,...
Bikram
881
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
cpu
machine-instruction
+
–
3
votes
2
answers
1875
Test by Bikram | Mock GATE | Test 2 | Question: 41
A $DMA$ module is transferring bytes to memory using cycle stealing mode from a device transmitting at $16 KB/s$. The processor is fetching instructions at the rate of $1 MB/s$. The percentage by which the processor will be slowed down due to the $DMA$ activity is ______.
A $DMA$ module is transferring bytes to memory using cycle stealing mode from a device transmitting at $16 KB/s$. The processor is fetching instructions at the rate of $1...
Bikram
889
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
numerical-answers
co-and-architecture
dma
+
–
1
votes
1
answer
1876
Test by Bikram | Mock GATE | Test 2 | Question: 40
Consider a set associative cache memory with $8$ cache blocks $(0 - 7)$ and main memory with $128$ blocks. The following block requests are made by the $CPU$ ($\text{LRU}$ ... pair in which main memory block $7$ is present is: $3, 7$ $3, 6$ $2, 5$ $7$ is recently replaced
Consider a set associative cache memory with $8$ cache blocks $(0 - 7)$ and main memory with $128$ blocks. The following block requests are made by the $CPU$ ($\text{LRU}...
Bikram
407
views
Bikram
asked
Jan 24, 2017
CO and Architecture
tbb-mockgate-2
co-and-architecture
page-replacement
cache-memory
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–
2
votes
2
answers
1877
Test by Bikram | Mock GATE | Test 2 | Question: 26
The designers of a computer must select a cache system. They have two options. In first design they uses a direct-mapped cache containing $2$ words per cache line. It would have an instruction miss rate of $3%$ and a data miss rate of $8%$. In second design they uses a $2$- ... $D1 = 0.70, D2 = 0.40$ $D1 = 1.10, D2 = 0.40$ $D1 = 0.70, D2 = 0.48$
The designers of a computer must select a cache system. They have two options.In first design they uses a direct-mapped cache containing $2$ words per cache line. It woul...
Bikram
641
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
cache-memory
+
–
5
votes
3
answers
1878
Test by Bikram | Mock GATE | Test 2 | Question: 18
Which of the following statements is/are true? Floating point addition is always associative. Shifting a twos-complement integer right by one bit, and filling from the left with $0$, is always equivalent to dividing by $2$. An integer's ones ... twos-complement representation. I and II only II and III only All are false I, II, and III all are true
Which of the following statements is/are true?Floating point addition is always associative.Shifting a twos-complement integer right by one bit, and filling from the left...
Bikram
761
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
floating-point-representation
+
–
1
votes
2
answers
1879
Test by Bikram | Mock GATE | Test 2 | Question: 15
A certain computer has a $TLB$ cache, a one-level physically-addressed data cache, $DRAM$, and a disk backing store for virtual memory. The processor loads the instruction below and then begins to execute it. LW R3, 0(R4) $[$ LW ... one data cache miss can occur. If a page fault occurs, then a data cache miss definitely does not occur as well.
A certain computer has a $TLB$ cache, a one-level physically-addressed data cache, $DRAM$, and a disk backing store for virtual memory. The processor loads the instructio...
Bikram
742
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
cache-memory
translation-lookaside-buffer
+
–
5
votes
2
answers
1880
Test by Bikram | Mock GATE | Test 2 | Question: 11
A certain architecture supports indirect, direct, and register addressing modes for use in identifying operands for arithmetic instructions. Which of the following cannot be achieved with a single instruction? Specifying a register number in the ... memory location which in turn contains the value of an operand that will be used by the instruction.
A certain architecture supports indirect, direct, and register addressing modes for use in identifying operands for arithmetic instructions.Which of the following cannot ...
Bikram
590
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
addressing-modes
+
–
4
votes
3
answers
1881
Test by Bikram | Mock GATE | Test 2 | Question: 6
The designers of a cache system wants to reduce the number of cache misses that occur in a certain group of programs. Which of the following statements is/are correct regarding what designers can do? If compulsory misses are most common, then ... provide more flexibility when a collision occurs. I, II, and III I and II only II and III only III only
The designers of a cache system wants to reduce the number of cache misses that occur in a certain group of programs.Which of the following statements is/are correct rega...
Bikram
582
views
Bikram
asked
Jan 24, 2017
GATE
tbb-mockgate-2
co-and-architecture
cache-memory
+
–
3
votes
0
answers
1882
Set Associative Cache [GateBook]
biranchi
397
views
biranchi
asked
Jan 24, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
1
votes
2
answers
1883
Data Hazards [GateBook]
biranchi
2.0k
views
biranchi
asked
Jan 24, 2017
CO and Architecture
pipelining
data-hazards
co-and-architecture
+
–
2
votes
1
answer
1884
MadeEasy Subject Test: CO & Architecture - Cache Memory
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from the L2 cache memory are 50 cycles. The hit time of L2 cache is 10 cycles ... 5 cycles. If there are 1.25 memory references per instruction, then the average stall cycles per instruction is ________.
Suppose that in 250 memory references there are 30 misses in first level cache and 10 misses in second level cache. Assume that miss penalty from the L2 cache memory are ...
Pankaj Joshi
879
views
Pankaj Joshi
asked
Jan 23, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
multilevel-cache
cache-memory
+
–
2
votes
1
answer
1885
MadeEasy CBT 2017: Digital Logic - Ieee Representation
Dulqar
1.0k
views
Dulqar
asked
Jan 23, 2017
Digital Logic
made-easy-test-series
cbt-2017
co-and-architecture
ieee-representation
+
–
0
votes
1
answer
1886
cache miss
harshit agarwal
464
views
harshit agarwal
asked
Jan 23, 2017
CO and Architecture
co-and-architecture
cache-memory
+
–
5
votes
2
answers
1887
MadeEasy CBT 2017: CO & Architecture - Pipelining
Dulqar
1.3k
views
Dulqar
asked
Jan 22, 2017
CO and Architecture
made-easy-test-series
cbt-2017
co-and-architecture
pipelining
+
–
3
votes
1
answer
1888
MadeEasy CBT 2017: CO & Architecture - Cache Memory
Dulqar
884
views
Dulqar
asked
Jan 22, 2017
CO and Architecture
made-easy-test-series
cbt-2017
co-and-architecture
cache-memory
+
–
1
votes
2
answers
1889
MadeEasy CBT 2017: CO & Architecture - Dma
Dulqar
644
views
Dulqar
asked
Jan 22, 2017
CO and Architecture
made-easy-test-series
cbt-2017
co-and-architecture
dma
+
–
2
votes
1
answer
1890
self doubt
which one For computer based on one-address instruction formats/zero-address instruction formats each address field can be used to specify : A memory operand A processor register An implied accumulator register??? #reference gate-2015
which one For computer based on one-address instruction formats/zero-address instruction formats each address field can be used to specify : A memory operand A processor ...
yankur9
239
views
yankur9
asked
Jan 22, 2017
CO and Architecture
co-and-architecture
+
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