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Recent questions tagged co-and-architecture

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211
#COA #CacheMemory
What is the default access method of Cache Memory? Simultaneous or Hierarchical?
What is the default access method of Cache Memory? Simultaneous or Hierarchical?
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212
Addressing Modes
When we write MOV #1000 , it means we are writing the value 1000 into the accumulator. But when we write MOV 1000 here 1000 refers to address of what ? register or MM ? (knowing that MOV works only between registers).
When we write MOV #1000 , it means we are writing the value 1000 into the accumulator. But when we write MOV 1000 here 1000 refers to address of what ? register or MM ? (...
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213
cache miss question
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?
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3 answers
214
Difference b/w cache & TLB
What is the difference b/w cache & TLB? TLB is stored in cache too right? TLB helps in addressing like a faster version of page table while speaking of cache, it directly stores the process page directly right?
What is the difference b/w cache & TLB? TLB is stored in cache too right? TLB helps in addressing like a faster version of page table while speaking of cache, it directly...
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216
Arihant Gate Tutor
If a processor has 32-bit virtual address, 28-bit physical address, 2 kb pages. How many bits are required for the virtual, physical page number? 17, 21 21, 17 6, 10 None The answer given is b. 21, 17
If a processor has 32-bit virtual address, 28-bit physical address, 2 kb pages. How many bits are required for the virtual, physical page number?17, 2121, 176, 10NoneThe ...
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1 answer
217
Arihant Gate Tutor
Which of the following processor registers are used for fetch and execute operations ? Program Counter Instruction Register Address Register Options : a and b b and c a and c None of these
Which of the following processor registers are used for fetch and execute operations ?Program CounterInstruction RegisterAddress RegisterOptions :a and bb and ca and cNon...
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3 answers
218
Arihant Gate Tutor
Memory mapping table is used to (a) Translate virtual address to physical address (b) Translate physical address to virtual address (c) Both (d) None
Memory mapping table is used to(a) Translate virtual address to physical address(b) Translate physical address to virtual address(c) Both(d) None
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219
Calcutta University Question Paper
(a) Corresponding to the following reservation table, draw the state diagram. Clearly indicate the collision vectors, collision matrices, state transition diagram, and MALS 0 1 2 3 4 S1 A B A B S2 A A S3 B AB A
(a) Corresponding to the following reservation table, draw the state diagram. Clearly indicate the collision vectors, collision matrices, state transition diagram, and MA...
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