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Recent questions tagged co-and-architecture

0 votes
0 answers
2131
Write down the sequence of control signals required to execute LDA 1000
Write down the sequence of control signals required to execute LDA 1000 instruction (loading the content of 1000 into accumulator) in single bus CPU organisation. Please show working in answer
Write down the sequence of control signals required to execute LDA 1000 instruction (loading the content of 1000 into accumulator) in single bus CPU organisation.Please s...
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10 votes
4 answers
2135
GATE CSE 1987 | Question: 4b
What is cache memory? What is rationale of using cache memory?
What is cache memory? What is rationale of using cache memory?
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0 votes
1 answer
2138
Find the no of hits and misses in a 4-blocked cache For the LIFO policy
, if the sequence of blocks refered by cpu is given as 1,3,5,6,7,1,5,4.
, if the sequence of blocks refered by cpu is given as 1,3,5,6,7,1,5,4.
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2 votes
2 answers
2140
How many memory refernces are required for fetching and executing...
How many memory refernces are required for fetching and executing each of the following instructions? (a)ADD 50(R­1),R2 b)SUB (R­1)+R­2­
How many memory refernces are required for fetching and executing each of the following instructions?(a)ADD 50(R­1),R2 b)SUB (R­1)+R­2­
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0 votes
2 answers
2143
In a two level hierarchy if the top level has an access time of 8ns and the bottom level has an access time of 60 ns.
In a two level hierarchy if the top level has an access time of 8ns and the bottom level has an access time of 60 ns. What is the hit ratio in top level required to give ...
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0 votes
0 answers
2144
computer organization (co)
Why different clock cycle is needed for sending address and control signal . why not in one cycle?
Why different clock cycle is needed for sending address and control signal . why not in one cycle?
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2 votes
3 answers
2145
GATE CSE 1987 | Question: 2b
State whether the following statements are TRUE or FALSE: Data transfer between a microprocessor and an I/O device is usually faster in memory-mapped-I/O scheme than in I/O-mapped -I/O scheme.
State whether the following statements are TRUE or FALSE:Data transfer between a microprocessor and an I/O device is usually faster in memory-mapped-I/O scheme than in I/...
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5 votes
3 answers
2146
GATE CSE 1987 | Question: 2a
State whether the following statements are TRUE or FALSE In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.
State whether the following statements are TRUE or FALSEIn a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the micro...
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3 votes
1 answer
2152
GATE CSE 1987 | Question: 1-ix
The refreshing rate of dynamic RAMs is in the range of $2$ microseconds $2$ milliseconds. $50$ milliseconds $500$ milliseconds
The refreshing rate of dynamic RAMs is in the range of$2$ microseconds$2$ milliseconds.$50$ milliseconds$500$ milliseconds
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45 votes
6 answers
2155
GATE CSE 1987 | Question: 1-V
The most relevant addressing mode to write position-independent codes is: Direct mode Indirect mode Relative mode Indexed mode
The most relevant addressing mode to write position-independent codes is:Direct modeIndirect modeRelative modeIndexed mode
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2 votes
2 answers
2156
Virtually indexed caches
What is virtual indexed cache? How is it different from physical indexed cache? What is virtually indexed physical tagged cache? If possible point me to proper resources.
What is virtual indexed cache? How is it different from physical indexed cache? What is virtually indexed physical tagged cache? If possible point me to proper resources....
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–1 votes
0 answers
2159
Morris Mano
How to Construct a diagram for a 4×4 omega switching network ??
How to Construct a diagram for a 4×4 omega switching network ??
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