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Recent questions tagged co-and-architecture
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2161
Morris Mano , Gate Application
What is the difference between Loosely Coupled microprocessor System and Tightly Coupled microprocessor system in simple words please tell and explain please??
What is the difference between Loosely Coupled microprocessor System and Tightly Coupled microprocessor system in simple words please tell and explain please??
LavTheRawkstar
367
views
LavTheRawkstar
asked
Nov 4, 2016
CO and Architecture
co-and-architecture
digital-logic
computer
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0
votes
0
answers
2162
Differentiate the following
Differentiate the Following Memory Mapped IO Program Driven IO
Differentiate the Following Memory Mapped IOProgram Driven IO
PEKKA
164
views
PEKKA
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
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–
0
votes
0
answers
2163
different types of Buses [COA]
What is the difference between Universal serial bus IEEE 1394 and normal bus ?
What is the difference between Universal serial bus IEEE 1394 and normal bus ?
LavTheRawkstar
234
views
LavTheRawkstar
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
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–
0
votes
0
answers
2164
Different types of ports and their difference
what is the difference between [1]Serial Port and Parallel Port, [2]Serial port in PC and Serial I/O interface
what is the difference between Serial Port and Parallel Port, Serial port in PC and Serial I/O interface
LavTheRawkstar
428
views
LavTheRawkstar
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
io-handling
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–4
votes
0
answers
2165
COA Interface
What is this RS – 232 interface . Somebody please explain in easy words please
What is this RS – 232 interface . Somebody please explain in easy words please
LavTheRawkstar
852
views
LavTheRawkstar
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
pipelining
test-series
dma
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–
3
votes
2
answers
2166
Morris Mano Numerical
How many 128 × 8 RAM chips are needed to provide a memory capacity of 2048 bytes? How many lines of the address bus must be used to access 2048 byte of memory? How many of these lines will be common to all chips? How many lines must be decoded for chip select? Specify the size of the decoders?
How many 128 × 8 RAM chips are needed to provide a memory capacity of 2048 bytes?How many lines of the address bus must be used to access 2048 byte of memory? How many o...
LavTheRawkstar
35.1k
views
LavTheRawkstar
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
digital-logic
memory-interfacing
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2
votes
1
answer
2167
Morris Mano Numerical Chapter 12 Question 5
A computer employs RAM chips of 256 $\times$ 8 and ROM chips of 1024 $\times$ 8. The computer system needs 2K bytes of RAM, 4K bytes of ROM and four interface units, each with four registers. A memory-mapped I/O configuration is ... for the system. Give the address ranges in hex for RAM, ROM and interface. Show the interconnection of CPU and the chips.
A computer employs RAM chips of 256 $\times$ 8 and ROM chips of 1024 $\times$ 8. The computer system needs 2K bytes of RAM, 4K bytes of ROM and four interface units, each...
LavTheRawkstar
12.4k
views
LavTheRawkstar
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
digital-logic
memory-interfacing
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–
1
votes
1
answer
2168
total cycle time in non-pipeline
a) Pipeline contains 5 stages: IF, ID, EX, M and W; b) Each stage requires one clock cycle; c) All memory references hit in cache; d) Following program segment should be processed: // ADD TWO INTEGER ARRAYS LW R4 # 400 L1: LW R1, ... ; Loop if (R4) != 0 Calculate how many clock cycles will take execution of this segment on the regular (non pipelined) architecture ?
a) Pipeline contains 5 stages: IF, ID, EX, M and W;b) Each stage requires one clock cycle;c) All memory references hit in cache;d) Following program segment should be pro...
Akriti sood
2.4k
views
Akriti sood
asked
Nov 3, 2016
CO and Architecture
pipelining
co-and-architecture
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1
votes
1
answer
2169
Morris Mano Numerical [ Important]
A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers. [i] How many selection inputs are there in each multiplexer? [ii] What size of multiplexers is needed? [iii] How many multiplexers are there in the bus?
A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructedwith multiplexers.[i] How many selection inputs are there in each multi...
LavTheRawkstar
19.7k
views
LavTheRawkstar
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
computer
digital-logic
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–
1
votes
1
answer
2170
conditional and unconditional branch
can someone explain the diff between conditional and unconitional branch with some pipeline diagram or example??
can someone explain the diff between conditional and unconitional branch with some pipeline diagram or example??
Akriti sood
9.7k
views
Akriti sood
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
pipelining
branch-conditional-instructions
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–
3
votes
1
answer
2171
Morris Mano Numerical please explain this easy question
Starting from an initial value of R=11011101, determine the sequence of binary values in R after a logical shift-left, followed by a circular shift-right, followed by a logical shift-right and circular shift-left.
Starting from an initial value of R=11011101, determine the sequence of binary values in R after a logical shift-left, followed by a circular shift-right, followed by a l...
LavTheRawkstar
14.5k
views
LavTheRawkstar
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
computer
digital-logic
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–
1
votes
1
answer
2172
Morris MAno[COA]
Design a digital circuit that perform four logic operations of exclusive-OR, exclusive-NOR, NOR and NAND. Use two selection variables. Show logic diagram of one typical stage?
Design a digital circuit that perform four logic operations of exclusive-OR, exclusive-NOR, NOR and NAND. Use two selection variables. Show logic diagram of one typical s...
LavTheRawkstar
4.4k
views
LavTheRawkstar
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
computer
digital-logic
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–
0
votes
1
answer
2173
Morris Mano [COA]
Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The circuit generates the following four arithmetic operations in conjunction with the input carry Cin. Draw the logic diagram for the first two stages. S Cin = 0 Cin = 1 0 D= A+B (add) D= A+1 (increment) 1 D= A-1 (decrement) D= A+B′+1 (subtract)
Design an arithmetic circuit with one selection variable S and two n-bit data inputs A and B. The circuit generates the following four arithmetic operations in conjunctio...
LavTheRawkstar
7.9k
views
LavTheRawkstar
asked
Nov 3, 2016
CO and Architecture
co-and-architecture
computer
digital-logic
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–
1
votes
1
answer
2174
DMA transfer time
Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address register Decrement the count If count !=0 go to LOOP This is a code to transfer 500 B from ... to transfer one byte of data from the device to the memory. Calculate the DMA transfer time . % time processor is busy
Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address regis...
PEKKA
2.1k
views
PEKKA
asked
Nov 3, 2016
CO and Architecture
dma
co-and-architecture
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–
0
votes
1
answer
2175
Test Series
Sayan Das 1
395
views
Sayan Das 1
asked
Nov 2, 2016
CO and Architecture
co-and-architecture
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–
1
votes
1
answer
2176
What is happening in the following stages of pipeline ?
What is happening in fetch stage decode stage of pipeline . Please explain in details .
What is happening in fetch stage decode stageof pipeline . Please explain in details .
PEKKA
427
views
PEKKA
asked
Nov 2, 2016
CO and Architecture
pipelining
co-and-architecture
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–
1
votes
1
answer
2177
no data forwarding
Consider the following sequence of instructions executed on the five-stage pipelined processor: I1: lw $1, 40($6) I2: add $2, $3, $1 I3: add $1, $2, $6 I4: sw $2, 20($4) I5 : and $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?
Consider the following sequence of instructions executed on the five-stage pipelined processor:I1: lw $1, 40($6)I2: add $2, $3, $1I3: add $1, $2, $6I4: sw $2, 20($4)I5 : ...
Akriti sood
822
views
Akriti sood
asked
Nov 1, 2016
CO and Architecture
pipelining
operand-forwarding
co-and-architecture
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5
votes
1
answer
2178
speedup pipeline
The speedup of a pipeline is 5 and operating with an efficiency of 60% what will be the number of stages ? 8 7 9 1
The speedup of a pipeline is 5 and operating with an efficiency of 60% what will be the number of stages ? 8 7 9 1
Akriti sood
1.7k
views
Akriti sood
asked
Nov 1, 2016
CO and Architecture
pipelining
co-and-architecture
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–
3
votes
1
answer
2179
speedup
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is______________? in this question,speed up is 10/2 = 5 but why it is'nt ... 1.4 * 10) /2 =7.. //i am just confused because speedup is (total time in non pipleine /total time in pipeline)
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 s...
Akriti sood
783
views
Akriti sood
asked
Nov 1, 2016
CO and Architecture
pipelining
co-and-architecture
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–
2
votes
1
answer
2180
Explain the validity
Explain the validity of the statement Only one clock cycle time is required to execute one insstruction in pipelined processor even if CPI is not 1
Explain the validity of the statement Only one clock cycle time is required to execute one insstruction in pipelined processor even if CPI is not 1
PEKKA
331
views
PEKKA
asked
Nov 1, 2016
CO and Architecture
pipelining
co-and-architecture
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–
3
votes
1
answer
2181
miss penalty
Consider a system with CPI of 1.0 on a 5 GHz machine with a 2% miss rate and memory access time of 100ns. To reduce miss penalty designers decided to add a L2 cache with 5ns access time and decrease of overall main memory miss rate to 0.5%, How many clock cycles miss penalty reduced?
Consider a system with CPI of 1.0 on a 5 GHz machine with a 2% miss rate and memory access time of 100ns. To reduce miss penalty designers decided to add a L2 cache with ...
Akriti sood
1.9k
views
Akriti sood
asked
Oct 31, 2016
CO and Architecture
co-and-architecture
cache-memory
misses
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–
2
votes
2
answers
2182
Instruction pipeline utilization factor
Rakesh K
777
views
Rakesh K
asked
Oct 31, 2016
CO and Architecture
co-and-architecture
pipelining
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–
6
votes
1
answer
2183
Micro-programming
Which of the following statements are FALSE? S1: Hardwired control units are slower than micro programmed control units S2: In micro programmed control unit, even a minor modification require redesign and reconnection of control signals S3: In vertical micro programmed contrl unit, control signals are ... (A) All of the above (B) S1 and S2 only (C) S2 and S3 only (D) S1, S3 and S4
Which of the following statements are FALSE?S1: Hardwired control units are slower than micro programmed control unitsS2: In micro programmed control unit, even a minor m...
Rakesh K
6.1k
views
Rakesh K
asked
Oct 31, 2016
CO and Architecture
microprogramming
co-and-architecture
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–
7
votes
2
answers
2184
Addressing mode
What is the number of instrunctions needed to add n numbers in one address mode and store the result in the memory, assuming each number is already loaded in register? (A) n (B) n+1 (C) n-1 (D) 2n
What is the number of instrunctions needed to add n numbers in one address mode and store the result in the memory, assuming each number is already loaded in register?(A)...
Rakesh K
2.4k
views
Rakesh K
asked
Oct 30, 2016
CO and Architecture
co-and-architecture
addressing-modes
instruction-format
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–
4
votes
1
answer
2185
N bit processor means?
What is always true for a n bit processor? Eg: 32 bit processor ; A. Data bus has n lines B. Address bus has n lines C. CPU register is made of n bits D. A and B E. A and C
What is always true for a n bit processor? Eg: 32 bit processor ;A. Data bus has n linesB. Address bus has n linesC. CPU register is made of n bitsD. A and BE. A and C
sh!va
5.6k
views
sh!va
asked
Oct 30, 2016
CO and Architecture
co-and-architecture
+
–
4
votes
1
answer
2186
(Hamacher, pg.255, question 5.20)
1024x1024 array of 32-bit numbers is to be normalized as follows. For each column the largest element is found and all elements of the column are divided by this maximum value. Assume that each page in the virtual memory consists of 4Kbytes and that 1Mbytes of the ... it takes 2 ns to do a comparison, 20 ns to do a divide and 100 ns to do a load/store to memory.
1024x1024 array of 32-bit numbers is to be normalized as follows. For each column the largest element is found and all elements of the column are divided by this maximum ...
sushmita
2.6k
views
sushmita
asked
Oct 29, 2016
CO and Architecture
co-and-architecture
page-fault
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–
12
votes
1
answer
2187
Advanced Computer Architecture , KAI HWANG | How to Find MAL from Collision Vector | Non-Linear Pipeline
Collition Vector : 1011010 MAL for the above Collition Vector is _____Please also tell me how to calculate efficiency and throughtput
PEKKA
14.9k
views
PEKKA
asked
Oct 27, 2016
CO and Architecture
co-and-architecture
pipelining
+
–
3
votes
1
answer
2188
made easy
consider an instruction of indirect addressing mode. what are the number of memory references by the processor when an instruction is a computation that requires a single operand and when it is a branch instruction respectively?? According to me, the answer should be ... and two memory references for operand fetch as it is indirect. But the solution says 3,2. can someone check??
consider an instruction of indirect addressing mode. what are the number of memory references by the processor when an instruction is a computation that requires a single...
sushmita
3.8k
views
sushmita
asked
Oct 25, 2016
CO and Architecture
co-and-architecture
addressing-modes
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–
2
votes
2
answers
2189
Cache Memory Performance Gain
Suppose the cache memory is 100 times faster than main memory and it is used 50% of the time. The performance is gained by introducing this cache is __________.
Suppose the cache memory is 100 times faster than main memory and it is used 50% of thetime. The performance is gained by introducing this cache is __________.
pC
2.8k
views
pC
asked
Oct 24, 2016
CO and Architecture
cache-memory
co-and-architecture
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–
1
votes
0
answers
2190
Register Allocation
Do we have register interference graphs/ coloring in our syllabus and if so can someone please provide any online material for it.I am facing difficulty understanding how the graph is actually constructed.
Do we have register interference graphs/ coloring in our syllabus and if so can someone please provide any online material for it.I am facing difficulty understanding how...
Aakash Das
711
views
Aakash Das
asked
Oct 21, 2016
CO and Architecture
register-allocation
compiler-design
co-and-architecture
graph-theory
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