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Recent questions tagged co-and-architecture

4 votes
1 answer
2191
Pipeline Efficiency
Will it be 6 or 7?
Will it be 6 or 7?
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0 votes
1 answer
2192
Doubt
Min number of registers required to evaluate below expression: x = ( a+b) * (c+d) I am getting 2 but answer is 3. Solution: 1) Load r1,a 2) Add r1, b 3) Load r2, c 4) Add r2,d 5) Mul r1,r2 6) store x, r1
Min number of registers required to evaluate below expression:x = ( a+b) * (c+d)I am getting 2 but answer is 3.Solution: 1) Load r1,a2) Add r1, b3) Load r2, c4) Add r2,d5...
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0 votes
2 answers
2193
Pipeline
I am getting 15..please chk once
I am getting 15..please chk once
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1 votes
0 answers
2198
CO:
What are some study materials for CO ? Please provide links and pdf's and also mention some important topics that students generally leave but should not be left. I don't want to read Textbook, and also suggest me good problems on Pipelining. Thanks in advance
What are some study materials for CO ? Please provide links and pdf's and also mention some important topics that students generally leave but should not be left.I don't ...
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4 votes
1 answer
2199
Online test
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1 votes
2 answers
2200
Online
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1 votes
0 answers
2203
MadeEasy Workbook: CO & Architecture - Interrupts
Q i have doubt that if interrupt occurs on that instruction then value pushed in to stack after exeuting current instruction ...i think
Q i have doubt that if interrupt occurs on that instruction then value pushed in to stack after exeuting current instruction ...i think
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1 votes
1 answer
2206
UGC NET CSE | August 2016 | Part 3 | Question: 3
The register that stores the bits required to mask the interrupts is ______. Status register Interrupt service register Interrupt mask register Interrupt request register
The register that stores the bits required to mask the interrupts is ______.Status registerInterrupt service registerInterrupt mask registerInterrupt request register
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1 votes
1 answer
2208
UGC NET CSE | August 2016 | Part 2 | Question: 32
The content of the accumulator after the execution of the following 8085 assembly language program, is MVI A, 35H MOV B, A STC CMC RAR XRA B $00H$ $35H$ $EFH$ $2FH$
The content of the accumulator after the execution of the following 8085 assembly language program, isMVI A, 35HMOV B, ASTCCMCRARXRA B$00H$ $35H$$EFH$$2FH$
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1 votes
1 answer
2211
Computer organisation
Add #45,R1 what does it do?? according to site it stores result in R1 but my question is according to format after operation field(which is ADD here) Designation comes and only in cae of Store designation comes at last!!
Add #45,R1 what does it do?? according to site it stores result in R1 but my question is according to format after operation field(which is ADD here) Designation comes ...
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3 votes
1 answer
2213
UGC NET CSE | December 2010 | Part 2 | Question: 50
One of the distinguished features of super-computer over other category of computer is Parallel processing Highest accuracy level More speed More capacity
One of the distinguished features of super-computer over other category of computer isParallel processingHighest accuracy levelMore speedMore capacity
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1 votes
4 answers
2214
#Set Associative Memory #computer architecture
Q. A set-associative cache consist of 60 lines,or blocks,divided into four-line sets. Main memory consist of 2K blocks of 512 works each. In the format of main memory addresses, what is the size of tag , set and word is?
Q. A set-associative cache consist of 60 lines,or blocks,divided into four-line sets. Main memory consist of 2K blocks of 512 works each. In the format of main memory add...
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2 votes
1 answer
2216
UGC NET CSE | December 2010 | Part 2 | Question: 34
The register or main memory location which contains the effective address of the operand is known as Pointer Special location Indexed register None of the above
The register or main memory location which contains the effective address of the operand is known asPointerSpecial locationIndexed registerNone of the above
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0 votes
1 answer
2219
Memory-Control Unit
If size of MAR &MBR are $32$ bit and $16$ bit respectively then what is the main memory size. if memory is byte addressable .
If size of MAR &MBR are $32$ bit and $16$ bit respectively then what is the main memory size.if memory is byte addressable .
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