Register

Recent questions tagged co-and-architecture

3 votes
4 answers
2311
ISRO2008-37
The ability to temporarily halt the CPU and use this time to send information on buses is called direct memory access vectoring the interrupt polling cycle stealing
The ability to temporarily halt the CPU and use this time to send information on buses is calleddirect memory accessvectoring the interruptpollingcycle stealing
User Avatar
6 votes
4 answers
2312
ISRO2008-36
An interrupt in which the external device supplies its address as well as the interrupt requests is known as vectored interrupt maskable interrupt non maskable interrupt designated interrupt
An interrupt in which the external device supplies its address as well as the interrupt requests is known asvectored interruptmaskable interruptnon maskable interruptdesi...
User Avatar
8 votes
2 answers
2314
ISRO2007-46
Consider a small $2$-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently (LRU) scheme. The number of cache misses for the following sequence of block addresses is $8, 12, 0, 12, 8$ $2$ $3$ $4$ $5$
Consider a small $2$-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently (LRU) scheme. The number o...
User Avatar
8 votes
2 answers
2315
ISRO2007-37
In comparison with static RAM memory, the dynamic Ram memory has lower bit density and higher power consumption higher bit density and higher power consumption lower bit density and lower power consumption higher bit density and lower power consumption
In comparison with static RAM memory, the dynamic Ram memory haslower bit density and higher power consumptionhigher bit density and higher power consumptionlower bit den...
User Avatar
8 votes
4 answers
2316
ISRO2007-14
The principal of the locality of reference justifies the use of virtual memory interrupts main memory cache memory
The principal of the locality of reference justifies the use ofvirtual memoryinterruptsmain memorycache memory
User Avatar
6 votes
2 answers
2317
ISRO2007-08
A read bit can be read and written by CPU and written by peripheral by peripheral and written by CPU by CPU and written by the peripheral
A read bit can be readand written by CPUand written by peripheralby peripheral and written by CPUby CPU and written by the peripheral
User Avatar
6 votes
2 answers
2324
ISRO2009-23
The process of organizing the memory into two banks to allow $8$-and $16$-bit data operation is called Bank switching Indexed mapping Two-way memory interleaving Memory segmentation
The process of organizing the memory into two banks to allow $8$-and $16$-bit data operation is calledBank switchingIndexed mappingTwo-way memory interleavingMemory segme...
User Avatar
7 votes
4 answers
2326
ISRO2009-21, UGCNET-Dec2012-II: 12
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register? Absolute mode Indirect mode Immediate mode Index mode
In which addressing mode, the effectives address of the operand is generated by adding a constant value to the content of a register?Absolute modeIndirect modeImmediate m...
User Avatar
2 votes
1 answer
2329
UGC NET CSE | June 2012 | Part 3 | Question: 61
Identify the devices given below with their $\textsf{IC}$ ... $\text{(a)-(ii), (b)-(iii), (c)-(iv), (d)-(i)}$
Identify the devices given below with their $\textsf{IC}$ numbers :$\begin{array}{clcl} \text{(a)} & \text{USART} & \text{(i)} & \text{8251} \\ \text{(b)} & \text{Micro...
User Avatar
1 votes
2 answers
2333
UGC NET CSE | December 2013 | Part 3 | Question: 52
Serial access memories are useful in applications where Data consists of numbers Short access time is required Each stored word is processed differently. None of these
Serial access memories are useful in applications whereData consists of numbersShort access time is requiredEach stored word is processed differently.None of these
User Avatar
8 votes
5 answers
2335
ISRO-2013-16
How much speed do we gain by using the cache, when cache is used $80$% of the time? Assume cache is faster than main memory. $5.27$ $2.00$ $4.16$ $6.09$
How much speed do we gain by using the cache, when cache is used $80$% of the time? Assume cache is faster than main memory.$5.27$$2.00$$4.16$$6.09$
User Avatar
9 votes
7 answers
2336
ISRO-2013-15
A pipeline $P$ operating at $400$ MHz has a speedup factor of $6$ and operating at $70$% efficiency. How many stages are there in the pipeline? $5$ $6$ $8$ $9$
A pipeline $P$ operating at $400$ MHz has a speedup factor of $6$ and operating at $70$% efficiency. How many stages are there in the pipeline?$5$$6$$8$$9$
User Avatar
59 votes
4 answers
2340
GATE CSE 2004 | Question: 64
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ ... }\\\hline \end{array} The total number of clock cycles required to execute the program is $29$ $24$ $23$ $20$
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$\begin{array}{|l|l|c|} \hline \text {Instruction} & \text...
User Avatar
Page: