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Recent questions tagged co-and-architecture
2
votes
3
answers
241
CO and Arcitecture | RISC | Instruction pipelining
MSQ Which among the following statements is/are TRUE for a pipelined RISC computer. PC is usually incremented during Instruction Cycle (IF,ID) PC may be incremented during Execution Cycle (EX,MA,WB) Filling the Accumulator ... during the Instruction Cycle (IF,ID) All non-register memory fetching operations are done in Load instructions only.
MSQWhich among the following statements is/are TRUE for a pipelined RISC computer.PC is usually incremented during Instruction Cycle (IF,ID)PC may be incremented during ...
Souvik33
789
views
Souvik33
asked
Dec 16, 2022
CO and Architecture
pipelining
multiple-selects
co-and-architecture
machine-instruction
instruction-execution
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–
1
votes
1
answer
242
DRDO CSE 2022 Paper 2 | Question: 3
The execution of a program occurs on a $250 \mathrm{~GHz}$ processor that executes millions of instructions. Type, $\text{CPI}$ (cycles per instruction) and $\%$ of four instructions are provided in the table. \[\begin{array}{|c|c|c|} \ ... end{array}\] Compute the average $\text{CPI}$ and $\text{MIPS}$ (millions of instructions per second) rate of the processor.
The execution of a program occurs on a $250 \mathrm{~GHz}$ processor that executes millions of instructions. Type, $\text{CPI}$ (cycles per instruction) and $\%$ of four ...
admin
475
views
admin
asked
Dec 15, 2022
CO and Architecture
drdocse-2022-paper2
co-and-architecture
instruction-execution
5-marks
descriptive
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–
1
votes
1
answer
243
DRDO CSE 2022 Paper 2 | Question: 4
A system $\mathrm{X}$ with $2 \mathrm{~GHz}$ clock speed runs a program in $10$ seconds. We want to build a system $\mathrm{Y}$ to run the same program in $6$ seconds. For this, system $\mathrm{Y}$ needs $1.2$ times as many clock cycles as system $\mathrm{X}$. What should be the clock speed of the system $\mathrm{Y}?$
A system $\mathrm{X}$ with $2 \mathrm{~GHz}$ clock speed runs a program in $10$ seconds. We want to build a system $\mathrm{Y}$ to run the same program in $6$ seconds. Fo...
admin
374
views
admin
asked
Dec 15, 2022
CO and Architecture
drdocse-2022-paper2
co-and-architecture
clock-cycles
5-marks
descriptive
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–
0
votes
1
answer
244
Self Doubt | Logical Address | Virtual Address | Virtual Memory
Can anyone explain how are these two things connected (i) Virtual Memory (part of HDD, acting as RAM) and (ii) Virtual Address Space (Logical Address, generated by CPU during compilation), and where exactly is this Logical Address stored?
Can anyone explain how are these two things connected (i) Virtual Memory (part of HDD, acting as RAM) and (ii) Virtual Address Space (Logical Address, generated by CPU du...
Souvik33
469
views
Souvik33
asked
Dec 12, 2022
Others
operating-system
memory-management
virtual-memory
paging
co-and-architecture
self-doubt
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2
votes
1
answer
245
L1 and L2 cache
I have few doubts regarding $ L1$ and $ L2 $ cache Consider there is sequential access to L1 and L2 cache i.e L2 is accessed after L1 misses $\textup{Doubt 1:}$ Suppose we want to read data and data is not present in both $ L1$ and $ L2 $ then during reading ... do we write data only to $ L1$ or to both $ L1$ and $ L2 $? What happens if its said that both the cache are inclusive?
I have few doubts regarding $ L1$ and $ L2 $ cacheConsider there is sequential access to L1 and L2 cache i.e L2 is accessed after L1 misses$\textup{Doubt 1:}$Suppose we w...
Chaitanya Kale
373
views
Chaitanya Kale
asked
Dec 12, 2022
CO and Architecture
multilevel-cache
co-and-architecture
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1
votes
1
answer
246
Computer Organization and architecture
Consider a hypothetical processor which supports expand opcode technique. A 32 bit instruction is place in 256MW memory. If there exist 10, one address instruction then how many zero-address instruction are possible.
Consider a hypothetical processor which supports expand opcode technique. A 32bit instruction is place in 256MW memory. If there exist 10, one address instructionthen how...
iabhay.gupta
657
views
iabhay.gupta
asked
Dec 11, 2022
CO and Architecture
co-and-architecture
pipelining
control-unit
ieee-representation
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0
votes
0
answers
247
COA Doubt
What is the bandwidth of the memory , if access time and settling time of main memory are 45 ns and 5 ns respectively ? 20 Hz 20 KHz 20 MHz 50 MHZ
What is the bandwidth of the memory , if access time and settling time of main memory are 45 ns and 5 ns respectively ? 20 Hz20 KHz20 MHz50 MHZ
Jeetmoni saikia
554
views
Jeetmoni saikia
asked
Dec 7, 2022
CO and Architecture
co-and-architecture
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2
votes
0
answers
248
Split Phase | Self-Doubt | COA
How is split phase implemented in the hardware? For common register access between two stages, how is one clock cycle (Giving half a clock cycle to each of the stages) enough to satisfy work for both stages? Any reference to standard resources will also help.
How is split phase implemented in the hardware?For common register access between two stages, how is one clock cycle (Giving half a clock cycle to each of the stages) eno...
DebRC
468
views
DebRC
asked
Dec 6, 2022
CO and Architecture
co-and-architecture
operand-forwarding
operating-system
self-doubt
split-phase
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–
2
votes
1
answer
249
Logical and Physical Address Generation | OS
MSQ Consider execution of the following C code for different cases: printf( %d ,&a); Consider the following statements. Which among these are TRUE: Will print Logical Address in case of Local Variables, as they are static ... runtime, like malloc() Will print Logical Address in case of variables Dynamically allocated during the runtime, like malloc()
MSQConsider execution of the following C code for different cases:printf(“%d”,&a);Consider the following statements. Which among these are TRUE:Will print Logical Add...
Souvik33
506
views
Souvik33
asked
Dec 3, 2022
Operating System
memory-management
paging
co-and-architecture
operating-system
multiple-selects
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–
3
votes
2
answers
250
I/O Modes | Process State Transition | COA & OS
MSQ A ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes? Synchronous I/O Asynchronous I/O Interrupt Driven I/O DMA
MSQA ‘Running’ process is surely put into ‘Blocked/Wait’ state during while requesting for an I/O, in which of the following I/O modes?Synchronous I/OAsynchronous...
Souvik33
787
views
Souvik33
asked
Dec 2, 2022
CO and Architecture
operating-system
process-scheduling
co-and-architecture
dma
interrupts
input-output
multiple-selects
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–
0
votes
1
answer
251
Made Esy Test Series 2022 | COA | Subject wise Q.no 17
** MSQ ** Consider the following sequence of micro-operations (μO) on a system used for instruction fetch: Where MAR is memory address register, PC is program counter, MBR is memory buffer register and IR is instruction register. And ... the following μO's can execute parallely without conflict. μO2 and μO3 μO1 and μO3 μO4 and μO3 μO2 and μO4
MSQ Consider the following sequence of micro-operations (μO) on a system used for instruction fetch:Where MAR is memory address register, PC is program counter, MBR i...
Souvik33
574
views
Souvik33
asked
Nov 23, 2022
CO and Architecture
co-and-architecture
made-easy-test-series
multiple-selects
test-series
instruction-execution
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