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Recent questions tagged co-and-architecture
1
votes
2
answers
2431
Microprogrammed control unit 1
Ques:- Control field of microinstruction contain two groups of control signal group 1 supports none or one of 64 control signals and group 2 supports at most 6 from remaining. What is size of micro operation? (what is the meaning of "from remaining" here?)
Ques:-Control field of microinstruction contain two groups of control signal group 1 supports none or one of 64 control signals and group 2 supports at most 6 from remain...
khushtak
1.3k
views
khushtak
asked
Jan 6, 2016
CO and Architecture
co-and-architecture
microprogramming
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5
votes
1
answer
2432
CO: Cache set Associative
A two way set associative cache has lines of 16 byte and a total cache size of 8 K bytes. The 256 M byte main memory is byte addressable. Which one of the following main memory block is mapped on to the set ‘0’ of the cache memory? A) (CFED09B)16 B) (FCED90C)16 C) (CFED00B)16 D) (FECD10C)16
A two way set associative cache has lines of 16 byte and a total cache size of 8 K bytes. The 256 M byte main memory is byte addressable. Which one of the following main ...
Prasanna
3.5k
views
Prasanna
asked
Jan 5, 2016
CO and Architecture
cache-memory
co-and-architecture
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3
votes
1
answer
2433
CO: Main Memory Hit Ratio
Consider an array of 4 elements and each element occupies 4-words. A 16 word cache is used and divided into a block of 8 words. If the following code is executed what is the hit ratio? for (i = 0; i < 2; i++) for (j = 0; j < 2; j++) x = A[i, j] + A[j, i] (a) 0.5 (b) 0.66 (c) 0.75 (d) 0.87
Consider an array of 4 elements and each element occupies 4-words. A 16 word cache is used and divided into a block of 8 words. If the following code is executed what is ...
Prasanna
1.4k
views
Prasanna
asked
Jan 5, 2016
CO and Architecture
co-and-architecture
cache-memory
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–
1
votes
1
answer
2434
Pipeline problem
A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, OF and WO stages takes 1 clock cycle each for any instruction. The PO stage takes ... question is , Here I1 and I2 are dependent , so how can they start without any stall , no operand forwarding is also mentioned.
A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, O...
worst_engineer
1.6k
views
worst_engineer
asked
Jan 5, 2016
CO and Architecture
co-and-architecture
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–
0
votes
1
answer
2435
Computer Org- write through and write back
confused_luck
578
views
confused_luck
asked
Jan 5, 2016
CO and Architecture
co-and-architecture
look-aside
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0
votes
1
answer
2436
doubt
what is the meaning of below line ?? 1 MB 16-way set associative virtually indexed physically tagged cache(VIPT).
what is the meaning of below line ??1 MB 16-way set associative virtually indexed physically tagged cache(VIPT).
focus _GATE
301
views
focus _GATE
asked
Jan 4, 2016
CO and Architecture
co-and-architecture
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1
votes
3
answers
2437
Ace Test Series: CO & Architecture - Addressing Modes
Given answer is A. I am doubtful between A and B why not B is faster than A. Please explain
Given answer is A. I am doubtful between A and B why not B is faster than A. Please explain
shikharV
1.5k
views
shikharV
asked
Jan 4, 2016
CO and Architecture
ace-test-series
co-and-architecture
addressing-modes
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0
votes
1
answer
2438
Finding transfer time of a sector
Given explanation of the problem: I couldn't understand why to add average rotational latency. I think that transfer time of sector should be just 6 microsec. If the same question comes in GATE what should I write?
Given explanation of the problem:I couldn't understand why to add average rotational latency. I think that transfer time of sector should be just 6 microsec. If the same ...
shikharV
1.6k
views
shikharV
asked
Jan 4, 2016
CO and Architecture
co-and-architecture
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–
1
votes
1
answer
2439
Max size of main memory
why this qs has no effect of two level paging??i dont know if the answer given by madeeasy is right..
why this qs has no effect of two level paging??i dont know if the answer given by madeeasy is right..
resuscitate
1.0k
views
resuscitate
asked
Jan 3, 2016
CO and Architecture
virtual-memory
co-and-architecture
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0
votes
0
answers
2440
Question on constructing larger RAM from smaller RAM
Given explanation: Please explain me the given explanation of this question (if possible with a dig),
Given explanation:Please explain me the given explanation of this question (if possible with a dig),
shikharV
181
views
shikharV
asked
Jan 3, 2016
CO and Architecture
co-and-architecture
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–
0
votes
1
answer
2441
Resource for studying microprogramming
I want to know how much important topic is microprogramming for gate? And what and from where I should prepare for this topic?
I want to know how much important topic is microprogramming for gate? And what and from where I should prepare for this topic?
shikharV
586
views
shikharV
asked
Jan 2, 2016
CO and Architecture
co-and-architecture
horizontal
microprogramming
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3
votes
2
answers
2442
GATE2005
Consider a disk drive with the following specifications: 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one 4 byte word is ready it is sent to memory ... DMA cycle. Memory cycle time is 40 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is____________
Consider a disk drive with the following specifications:16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in ...
pC
1.6k
views
pC
asked
Dec 30, 2015
CO and Architecture
co-and-architecture
io-organization
dma
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–
3
votes
1
answer
2443
Finding Hit Ratio when memory references are given in Hex
A byte addressable computer has a small data cache capable of holding eight 32 bit words. Each cache block consist of two 32 bit words. For the following sequence of addresses (in hexa decimal ). Find the hit ratio if two way ... is conflicting. You can check it here - https://gateoverflow.in/29182/cache-miss-in-two-way-set-associative ]
A byte addressable computer has a small data cache capable of holding eight 32 bit words. Each cache block consist of two 32 bit words. For the following sequence of addr...
Tushar Shinde
2.3k
views
Tushar Shinde
asked
Dec 30, 2015
CO and Architecture
cache-memory
memory-management
co-and-architecture
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–
1
votes
3
answers
2444
UGC NET CSE | December 2015 | Part 3 | Question: 4
A dynamic RAM has refresh cycle of $32$ times per msec. Each refresh operation requires $100$ msec and a memory cycle requires $250$ msec. What percentage of memory's total operating time is required for refreshes? $0.64$ $0.96$ $2.00$ $0.32$
A dynamic RAM has refresh cycle of $32$ times per msec. Each refresh operation requires $100$ msec and a memory cycle requires $250$ msec. What percentage of memory's tot...
Sanjay Sharma
5.6k
views
Sanjay Sharma
asked
Dec 30, 2015
CO and Architecture
ugcnetcse-dec2015-paper3
co-and-architecture
dynamic-ram
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–
1
votes
1
answer
2445
privileged Instructions
What are Privileged Instructions. Describe briefly. Also give some examples.
What are Privileged Instructions. Describe briefly.Also give some examples.
Himanshu1
628
views
Himanshu1
asked
Dec 28, 2015
CO and Architecture
co-and-architecture
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–
1
votes
2
answers
2446
pipelining - branch delay slot
Himanshu1
1.4k
views
Himanshu1
asked
Dec 24, 2015
CO and Architecture
pipelining
co-and-architecture
branch-conditional-instructions
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1
votes
2
answers
2447
pipelining - without operand forwarding
Himanshu1
2.8k
views
Himanshu1
asked
Dec 24, 2015
CO and Architecture
co-and-architecture
pipelining
data-dependency
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2
votes
1
answer
2448
MadeEasy Test Series: CO & Architecture - Instruction Format
worst_engineer
2.5k
views
worst_engineer
asked
Dec 24, 2015
CO and Architecture
co-and-architecture
instruction-format
made-easy-test-series
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–
7
votes
4
answers
2449
Pipeline
Consider a pipeline x' consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 5 ns, 6 ns, 8 ns and 1 ns. The alternative pipeline y' contain the same number of stages but EX stage is divided into ... contains 30% of the instructions which are memory based instructions, the ratio of the speedup ratio of x to the speedup ratio of y is ___________.
Consider a pipeline ‘x’ consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 5 ns, 6 ns, 8 ns and 1 ns. The alternative pipeli...
tiger
3.7k
views
tiger
asked
Dec 20, 2015
CO and Architecture
co-and-architecture
pipelining
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–
1
votes
2
answers
2450
MadeEasy Test Series: CO & Architecture - MicroProgramming
Q.27 Consider a CPU where 150 instructions take 8 clock cycles each to complete the execution. A horizontal microprogrammed control unit has to generate 125 control signals. What is the minimum size of control word? _______ Answer given is 136 ( ... or byte) , Neither they have given that answer should be multiple of 8 , if it is in bit !
Q.27Consider a CPU where 150 instructions take 8 clock cycles each to complete the execution. A horizontal microprogrammed control unit has to generate 125 control signal...
Akash Kanase
2.2k
views
Akash Kanase
asked
Dec 19, 2015
CO and Architecture
co-and-architecture
microprogramming
made-easy-test-series
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–
1
votes
0
answers
2451
GATE CSE 1992 | Question: 05,b
Three devices $A, B$ and $C$ are connected to the bus of a computer, input/output transfers for all three devices use interrupt control. Three interrupt request lines INTR$1,$ INTR$2$ and INTR$3$ are available with priority of INTR$1 >$ priority ... priority logic, using an interrupt mask register, in which Priority of $A$ > Priority of $B$ > Priority of $C.$
Three devices $A, B$ and $C$ are connected to the bus of a computer, input/output transfers for all three devices use interrupt control. Three interrupt request lines INT...
Arjun
827
views
Arjun
asked
Dec 19, 2015
CO and Architecture
gate1992
co-and-architecture
interrupts
normal
descriptive
unsolved
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–
2
votes
0
answers
2452
MadeEasy Test Series: CO & Architecture - Addressing Modes
Q.14 Which of the following is most relevant addressing mode used to write code in which reallocation done at run time? Indexed mode Indirect mode Direct mode Relative mode Related to https://gateoverflow.in/3578/gate2006-it_39 https://gateoverflow.in/1656/gate1998_1-19
Q.14Which of the following is most relevant addressing mode used to write code in which reallocation done at run time?Indexed modeIndirect modeDirect modeRelative modeRel...
Akash Kanase
521
views
Akash Kanase
asked
Dec 19, 2015
CO and Architecture
co-and-architecture
addressing-modes
made-easy-test-series
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–
1
votes
0
answers
2453
MadeEasy Test Series: CO & Architecture - Pipelining
Q.58 Consider 5 stage pipeline which allow all instructions except branch instruction. Program contain 30% conditional instructions out of which 75% are branch instruction. Processor stop fetching the following instruction after the branch instruction ... time. The processor is running with rate of ____________ (in MIPS). Given answer -> 92
Q.58Consider 5 stage pipeline which allow all instructions except branch instruction. Program contain 30% conditional instructions out of which 75% are branch instruction...
Akash Kanase
361
views
Akash Kanase
asked
Dec 19, 2015
CO and Architecture
co-and-architecture
pipelining
made-easy-test-series
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–
0
votes
3
answers
2454
MadeEasy Test Series: CO & Architecture - Speedup
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 30% and the speed of a fixed point unit has been increased by $20$%. The overall speedup achieved if the ratio of the ... operation used to take twice the time taken by fixed point operation in the original design(upto $2$ decimal places is __________.
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 30% and the speed of a fixed point unit has been increased by $20$%. The ...
sonu
572
views
sonu
asked
Dec 17, 2015
CO and Architecture
speedup
co-and-architecture
made-easy-test-series
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–
12
votes
3
answers
2455
direct mapping and types of misses
Consider a cache as follows: Direct mapped 8 words total cache data size 2 words block size A sequence of eight memory read is performed in the order shown from the following addresses: 0 , 11 , 4 , 14 , 9 , 1 , 8 , 0 Calculate No. of misses No of compulsory misses No. of conflict misses No. of capacity misses
Consider a cache as follows:Direct mapped8 words total cache data size2 words block sizeA sequence of eight memory read is performed in the order shown from the following...
khushtak
6.4k
views
khushtak
asked
Dec 15, 2015
CO and Architecture
direct-mapping
misses
cache-memory
co-and-architecture
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–
3
votes
1
answer
2456
Total latch latency
Suppose there is unpipelined processor with a cycle time 30 ns which is evenly divided into 5 pipeline stages. The total latch latency of the pipeline will be _______________ ns.
Suppose there is unpipelined processor with a cycle time 30 ns which is evenly divided into 5 pipeline stages. The total latch latency of the pipeline will be ___________...
prathams
1.0k
views
prathams
asked
Dec 13, 2015
CO and Architecture
co-and-architecture
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–
2
votes
1
answer
2457
What is the time required to execute program without branch prediction ?
Program consists of 16 instructions (I1, I2, I3, ...., I16). In which I6 is a unconditional branch instruction transfer the controls of I12. In the pipeline, branch target address will be available at the end of ... is 10 nsec. What is the time (in nsec) required to execute the above program without using branch prediction?
Program consists of 16 instructions (I1, I2, I3, ...., I16). In which I6 is a unconditional branch instruction transfer the controls of I12. In the pipeline, branch targe...
prathams
714
views
prathams
asked
Dec 13, 2015
CO and Architecture
co-and-architecture
+
–
2
votes
1
answer
2458
UGC NET CSE | December 2012 | Part 3 | Question: 27
In an enhancement of a CPU design, the speed of a floating point unit has been increased by 20% and the speed of a fixed point unit has been increased by 10%. What is the overall speed achieved if the ratio of the number of floating point ... used to take twice the time taken by the fixed point operation in original design? 1.62 1.55 1.85 1.285
In an enhancement of a CPU design, the speed of a floating point unit has been increased by 20% and the speed of a fixed point unit has been increased by 10%. What is the...
prathams
1.1k
views
prathams
asked
Dec 11, 2015
CO and Architecture
co-and-architecture
ugcnetcse-dec2012-paper3
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–
0
votes
1
answer
2459
How to calculate total size of meta data for cache ?
An 16KB 4-way set associative write-back cache is organized as multiple blocks, each of size 64-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising with 1 Valid ... is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?
An 16KB 4-way set associative write-back cache is organized as multiple blocks, each of size 64-bytes. The processor generates 32-bit addresses. The cache controller main...
prathams
2.1k
views
prathams
asked
Dec 10, 2015
CO and Architecture
co-and-architecture
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–
2
votes
3
answers
2460
What is the answer ?
Suppose that a cache is 20 times faster than main memory and cache memory can be used 80% of the time. The speed-up factor that can be achieved by using the cache is _________.
Suppose that a cache is 20 times faster than main memory and cache memory can be used 80% of the time. The speed-up factor that can be achieved by using the cache is ____...
prathams
1.1k
views
prathams
asked
Dec 10, 2015
CO and Architecture
co-and-architecture
cache-memory
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