Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Recent questions tagged co-and-architecture
7
votes
1
answer
31
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 15
An MIPS pipeline has five stages, with a clock cycle of $200 \mathrm{ps}$. Suppose that this MIPS pipeline is redesigned to have four stages, with a clock cycle of $250 \mathrm{ps}$. Assuming an infinite sequence of instructions, what speedup will this new design achieve when compared to the five-stage pipeline?
An MIPS pipeline has five stages, with a clock cycle of $200 \mathrm{ps}$. Suppose that this MIPS pipeline is redesigned to have four stages, with a clock cycle of $250 \...
GO Classes
543
views
GO Classes
asked
Jan 13
CO and Architecture
goclasses2024-mockgate-11
goclasses
numerical-answers
co-and-architecture
pipelining
1-mark
+
–
5
votes
1
answer
32
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 34
Which of the following is the best justification for using the middle bits of an address as the set index into a cache rather than the most significant bits? Indexing with the most significant bits would necessitate a smaller ... is likely to make more efficient use of the cache with middle-bit indexing than with high-bit indexing.
Which of the following is the best justification for using the middle bits of an address as the set index into a cache rather than the most significant bits?Indexing with...
GO Classes
398
views
GO Classes
asked
Jan 13
CO and Architecture
goclasses2024-mockgate-11
goclasses
co-and-architecture
cache-memory
1-mark
+
–
2
votes
1
answer
33
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 42
There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $\textsf{RAMs}\: 1, 2, 3$ and $4$ ... $\textsf{0800H-0BFFH, 1800H-1BFFH, 2800H-2BFFH, 3800H-3BFFH}$
There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $\textsf{RAMs}\: 1, 2, 3$ and $4$ respectively...
GO Classes
393
views
GO Classes
asked
Jan 13
CO and Architecture
goclasses2024-mockgate-11
goclasses
co-and-architecture
2-marks
+
–
5
votes
1
answer
34
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 43
Consider the following $6 \;\mathrm{I} / \mathrm{O}$ operations and their respective cylinder locations on disk. Seek time is $0.1$ milliseconds per cylinder traversed. The cylinders are numbered from $0$ to $99.$ ... total time we spend seeking is $\mathrm{Y}$ milliseconds. What is $10 \ast(\mathrm{X}-\mathrm{Y})?$
Consider the following $6 \;\mathrm{I} / \mathrm{O}$ operations and their respective cylinder locations on disk. Seek time is $0.1$ milliseconds per cylinder traversed. T...
GO Classes
532
views
GO Classes
asked
Jan 13
CO and Architecture
goclasses2024-mockgate-11
goclasses
numerical-answers
co-and-architecture
disk-scheduling
2-marks
+
–
0
votes
1
answer
35
Control Unit
Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be active anytime. The micro instruction of the control unit stores control signal information along with 3-bit MUX select and 12 bits address field. The size of the control memory required is?
Design a vertical micro programmed control unit to generate 40 signals. Out of first 35 those only 3 signals can be active at a time. And remaining 5, anyone can be acti...
arnabjana09
158
views
arnabjana09
asked
Jan 11
CO and Architecture
co-and-architecture
control-unit
microprogramming
+
–
0
votes
0
answers
36
Control Unit
Consider a microprogrammed control unit has to support 32 number of instructions. For each instruction execution control unit generate a sequence of 64 control words. Each micro instruction contains 3 fields: 118 control signals to support horizontal control unit, a MUX select field to select one of 8 inputs, and a next address field. The size of control memory needed is?
Consider a microprogrammed control unit has to support 32 number of instructions. For each instruction execution control unit generate a sequence of 64 control words. Eac...
arnabjana09
124
views
arnabjana09
asked
Jan 11
CO and Architecture
co-and-architecture
control-unit
microprogramming
+
–
2
votes
1
answer
37
ISRO 2024
The operation executed on data stored in registers is called Macro-operation Micro-operation Bit-operation Byte-operation
The operation executed on data stored in registers is calledMacro-operationMicro-operationBit-operationByte-operation
Ramayya
127
views
Ramayya
asked
Jan 7
CO and Architecture
co-and-architecture
+
–
0
votes
1
answer
38
ISRO 2024
An instruction pipeline can be implemented by means of LIFO buffer FIFO buffer Stack None of the above
An instruction pipeline can be implemented by means ofLIFO bufferFIFO bufferStackNone of the above
Ramayya
260
views
Ramayya
asked
Jan 7
CO and Architecture
isro-2024
co-and-architecture
pipelining
+
–
0
votes
1
answer
39
ISRO 2024
Which of the following is false about interrupts? Interrupts can be triggered by a hardware or a software Hardware interrupts may be triggered by sending a signal to CPU through a system bus Software interrupts may be triggered by executing system calls Trap is a hardware generated interrupt
Which of the following is false about interrupts?Interrupts can be triggered by a hardware or a softwareHardware interrupts may be triggered by sending a signal to CPU th...
Ramayya
216
views
Ramayya
asked
Jan 7
CO and Architecture
isro-2024
co-and-architecture
interrupts
+
–
0
votes
0
answers
40
ISRO 2024
In a vectored interrupt The branch address is assigned to a fixed location in a memory The interrupting source supplies the branch information to the processor The branch address is obtained from a register in the processor None of the above A request to the approver.!! This question is asked in ISRO 2024. Due to insufficient points, couldn’t add ‘isro2024’ tag, Please add it.
In a vectored interruptThe branch address is assigned to a fixed location in a memoryThe interrupting source supplies the branch information to the processorThe branch ad...
Ramayya
107
views
Ramayya
asked
Jan 7
CO and Architecture
co-and-architecture
interrupts
+
–
Page:
« prev
1
2
3
4
5
6
7
...
90
next »
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register