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Recent questions tagged co-and-architecture
2
votes
1
answer
61
unacademy test series
lovish_bhatia
254
views
lovish_bhatia
asked
Dec 13, 2023
CO and Architecture
co-and-architecture
unacademy-test-series
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–
1
votes
1
answer
62
unacademy test series
please explain this question
please explain this question
lovish_bhatia
164
views
lovish_bhatia
asked
Dec 13, 2023
CO and Architecture
co-and-architecture
registers
unacademy-test-series
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–
0
votes
0
answers
63
Made Easy Question : Multilevel Paging system, please refer the question below.
In this question, they have asked for memory requirements for page tables across the levels, solving which I am getting number of level 3 page tables as 2^8. Below is a brief of my approach, can anybody please explain if I am right or ... 3 PTs + level 4 PTs = 1 + 1 + 2^8 + 2^16 Where am I doing wrong? Please explain.
In this question, they have asked for memory requirements for page tables across the levels, solving which I am getting number of level 3 page tables as 2^8. Below is a b...
tishhaagrawal
243
views
tishhaagrawal
asked
Dec 5, 2023
CO and Architecture
paging
co-and-architecture
gate-preparation
made-easy-test-series
multilevel-paging
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0
votes
1
answer
64
Made Easy Test Series : Assume a system has a 64bit VAS and 48 bit PAS. Page size is equal to 4KB. If only single level paging is used then the size of the page table (in TB)
Can anybody explain why are they dividing the number of pages by page size?According to me, it should be – Page table size = Number of entries * entry sizei.e PT size =...
tishhaagrawal
335
views
tishhaagrawal
asked
Dec 5, 2023
CO and Architecture
co-and-architecture
gate-preparation
self-doubt
made-easy-test-series
+
–
0
votes
0
answers
65
Made Easy Test Series Question : Assume a system has a 64 bit virtual address space and a 48 bit physical address space, and has a page size equal to 4KB. If single level paging is used in the system then the size of the page table is equal to_________(in TB)?
Can anybody explain why are they dividing the number of pages by page size?According to me, it should be – Page table size = Number of entries * entry sizei.e PT size =...
tishhaagrawal
9
views
tishhaagrawal
asked
Dec 5, 2023
CO and Architecture
go2025-coa-1
co-and-architecture
gate-preparation
made-easy-test-series
test-series
computer
doubt
self-doubt
+
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1
votes
1
answer
66
Made Easy test series
Abhishek3301
397
views
Abhishek3301
asked
Dec 5, 2023
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
gate-preparation
goclasses
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–
0
votes
1
answer
67
gate 2024
do we have non linear pipelines and minimum average latency for gate cs 2024
do we have non linear pipelines and minimum average latency for gate cs 2024
vivek1211
172
views
vivek1211
asked
Nov 28, 2023
CO and Architecture
co-and-architecture
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–
0
votes
0
answers
68
Test Series
Please tell the solution for both questions
Please tell the solution for both questions
sparsh15
142
views
sparsh15
asked
Nov 25, 2023
CO and Architecture
co-and-architecture
test-series
+
–
1
votes
1
answer
69
COA - DMA
A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 500 MHz, and takes 500 and 1000 clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is 1 Kbytes, what is the percentage of processor time consumed for the transfer operation?________(Rounded off to three decimal)
A hard disk with a transfer rate of 1 Mbytes/ second is constantly transferring data to memory using DMA. The processor runs at 500 MHz, and takes 500 and 1000 clock cycl...
ajayraho
599
views
ajayraho
asked
Nov 21, 2023
CO and Architecture
co-and-architecture
dma
interrupts
zeal-workbook
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–
0
votes
1
answer
70
Operand Forwarding [ Self Doubt }
I have a Self doubt question on Operand Forwarding . The data forwarded should be done in EX-EX stage or Mem-EX ? Which one to follow and when ? Using EX-EX we require less no. of cycles.
I have a Self doubt question on Operand Forwarding . The data forwarded should be done in EX-EX stage or Mem-EX ? Which one to follow and when ?Using EX-EX we require les...
Deepak9000
256
views
Deepak9000
asked
Nov 5, 2023
CO and Architecture
pipelining
co-and-architecture
operand-forwarding
data-dependency
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–
0
votes
1
answer
71
Made Easy Test Series 2024
In an enhancement of a CPU design, the speed of a floating point unit has been increased by 25% and the speed of fixed point unit has been increased by 10%. What is the overall speedup achieved if the ratio of the number of floating point operations ... used to take twice the time taken by the fixed point operation in original design? (Upto 3 decimal places) Ans: 1.185
In an enhancement of a CPU design, the speed of a floating point unit has been increased by 25% and the speed of fixed point unit has been increased by 10%. What is the o...
squirrel69
213
views
squirrel69
asked
Nov 1, 2023
CO and Architecture
co-and-architecture
made-easy-test-series
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