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Recent questions tagged combinational-circuit

2 votes

2 answers

1

GATE CSE 2023 | Question: 11
The output of a $2$-input multiplexer is connected back to one of its inputs as shown in the figure. Match the functional equivalence of this circuit to one of the following options. $\text{D}$ Flip-flop $\text{D}$ Latch Half-adder Demultiplexer

admin asked in Digital Logic Feb 15

by admin

1.2k views

2 votes

3 answers

2

GATE CSE 2023 | Question: 34
A Boolean digital circuit is composed using two $4$-input multiplexers $\text{(M1 and M2)}$ and one $2$-input multiplexer $\text{(M3)}$ as shown in the figure. $\text{X0-X7}$ are the inputs of the multiplexers $\text{M1 and M2}$ and could be connected to either $0$ or $1.$ The select lines of the ... $(1,1,0,0,1,1,0,1)$ $(1,1,0,1,1,1,0,0)$ $(0,0,1,1,0,1,1,1)$

admin asked in Digital Logic Feb 15

by admin

881 views

3 votes

1 answer

3

How many NAND gates required?

h4kr asked in Digital Logic Jan 21

by h4kr

94 views

0 votes

0 answers

4

A majority function is generated in a combinational circuit when the output is equal to 1 if the input variables have more 1’s than 0’s. The output is 0 otherwise. Make a 3-input majority function.

M.Zain asked in Digital Logic Dec 31, 2022

by M.Zain

241 views

1 vote

0 answers

5

DRDO CSE 2022 Paper 1 | Question: 24
Given a truth table of the full adder for three inputs. Draw a full adder circuit with a decoder and two $\text{OR}$ ...

admin asked in Digital Logic Dec 15, 2022

by admin

45 views

1 vote

1 answer

6

Digital Logic Question
Consider the following statements regarding the logic circuits: 1. In combinational logic circuits, the outputs at any instant of time are entirely dependent upon the inputs present at that time. 2. The behavior of synchronous sequential circuit depends upon the order in which its input signals change and ... ? (a) 1, 2 and 3 (b) 1 and 2 only (c) 2 and 3 only (d) 1 and 3 only

rsansiya111 asked in Digital Logic Oct 7, 2022

169 views

0 votes

1 answer

7

ISI2020-PCB-CS: 10
Suppose instead of a decoder with $n$ input bits ( $n$ is even) to access a memory of size $2^{n}$, one uses two decoders of input sizes $k$ bits and $(n-k)$ bits. Explain how these two decoders can be used to access the ... address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.

Lakshman Patel RJIT asked in Digital Logic Aug 8, 2022

by Lakshman Patel RJIT

126 views

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Recent questions tagged combinational-circuit