Recent questions tagged combinational-circuits - GATE Overflow

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Morris Mano Edition 3 Exercise 5 Question 35,36 (Page No. 201)
List the PLA programming table for the BCD-to-excess-3-code converter whose boolean functions are given in the figure. repeat the above problem using a PAL.

asked Apr 4 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 17 views

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Morris Mano Edition 3 Exercise 5 Question 34 (Page No. 201)
Derive the PLA Programming table for the combinational circuit that square a 3-bit number.Minimize the number of product term.

asked Apr 4 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 5 views

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Morris Mano Edition 3 Exercise 5 Question 33 (Page No. 201)
Tabulate the PLA programming table for the four boolean functions given. Minimize the number of product terms. $A(x,y,z) = \sum (1,2,4,6)$ $B(x,y,z) = \sum (0,1,6,7)$ $C(x,y,z) = \sum (2,6)$ $D(x,y,z) = \sum (1,2,3,5,7)$

asked Apr 4 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 24 views

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Morris Mano Edition 3 Exercise 5 Question 31 (Page No. 200)
Tabulate a truth table for an $8 \times 4$ ROM that implements the following four boolean functions: $A(x,y,z) = \sum (1,2,4,6)$ $B(x,y,z) = \sum (0,1,6,7)$ $C(x,y,z) = \sum (2,6)$ $D(x,y,z) = \sum (1,2,3,5,7)$

asked Apr 4 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 13 views

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Morris Mano Edition 3 Exercise 5 Question 31 (Page No. 200)
specify the size of a ROM ( Number of words and number of bits per words) that will accommodate the truth table for the following combinational circuit components: A binary multiplexer that multiplies two 4-bit numbers. A 4- ... to-1 line multiplexer with common select and enable inputs. A BCD-to-seven-segment decoder with an enable input.

asked Apr 4 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 11 views

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Morris Mano Edition 3 Exercise 5 Question 30 (Page No. 200)
A ROM chip of 4096 $\times$ 8 bits has two enable inputs and operates from a 5-volt power supply. How many pins are needed for the integrated-circuit package? draw a block diagram and label all the input and output terminals in the ROM

asked Apr 4 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 12 views

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Morris Mano Edition 3 Exercise 5 Question 29 (Page No. 200)
given a $32 \times 8 $ ROM chip with the enable input, show the external connection which is necessary to construct a $128 \times 8$ ROM with 4 chips and a Decoder.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 12 views

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Morris Mano Edition 3 Exercise 5 Question 28 (Page No. 200)
Implement the following boolean function with $4 \times 1$ multiplexer and external gates, connect A and B to selection lines. The input requirement for the four lines will be a function of C and D. These values are obtained by expressing F as a function ... be implemented with the external gates. $F(A,B,C,D) = \sum(1,3,4,11,12,13,14,15)$

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 44 views

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Morris Mano Edition 3 Exercise 5 Question 27 (Page No. 200)
An $8 \times 1$ multiplexer has inputs A,B and C connected to the selection inputs $s _2,s _1$ and $s _0$ respectively.The data inputs $I _0$ through $I _7$ are as follows: $I _1 = I _2 = I _7 = 0$; $ I _3 = I _5 = 1$; $ I _0 = I _4 = D$; and $I _6 = D’$.Determine the boolean function that the multiplexer implements.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 7 views

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Morris Mano Edition 3 Exercise 5 Question 26 (Page No. 200)
Implement the boolean function $F(A,B,C,D) = \sum(0,1,3,4,8,9,15)$ with an $8 \times 1$multiplexer, but with inputs A,B and C connected to selection inputs $s _2,s _1$ and $s _0$ respectively.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 6 views

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Morris Mano Edition 3 Exercise 5 Question 25 (Page No. 200)
Implement a Full adder with two $4 \times 1$ multiplexers.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 5 views

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Morris Mano Edition 3 Exercise 5 Question 24 (Page No. 200)
implement the following boolean function with an $8 \times 1$ multiplexer. $F(A,B,C,D) = \sum(0,3,5,6,8,9,14,15)$

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 4 views

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Morris Mano Edition 3 Exercise 5 Question 23 (Page No. 200)
Construct a $16 \times 1$ multiplexer with two $8 \times 1$ and one $ 2 \times 1$ multiplexers.use the block diagram for the three multiplexers.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 9 views

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Morris Mano Edition 3 Exercise 5 Question 22 (Page No. 200)
Draw the logic diagram of a dual 4-to-1 line multiplexer with common selection inputs and a common enable input.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 11 views

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Morris Mano Edition 3 Exercise 5 Question 21 (Page No. 200)
specify the truth table of an Octal-to-binary priority encoder. Provide an output V to indicate that at least one of the input is 1. The input with the highest subscript number has the highest priority. What will be the value of the four outputs if input $D _3$ and $D _5$ are 1 and the other inputs are all )’s?

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 12 views

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Morris Mano Edition 3 Exercise 5 Question 20 (Page No. 199)
Design a 4-input priority encoder with inputs as given in the tables, but with the input $D _0$ having the highest priority and the input $D _3$ have the lowest priority .

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 8 views

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Morris Mano Edition 3 Exercise 5 Question 19 (Page No. 199)
Rearrange the truth table for the circuit in the figure and verify it can function as demultiplexerr.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 15 views

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Morris Mano Edition 3 Exercise 5 Question 18 (Page No. 199)
Construct a $5 \times 32 $ decoder with four $3\times8$ decoders with enable and one $ 2 \times 4$ decoder. use a block diagram also.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 27 views

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Morris Mano Edition 3 Exercise 5 Question 17 (Page No. 199)
Draw the logic diagram of a 2-to-4 line decoder with only NOR gates. Include an Enable input.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 12 views

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Morris Mano Edition 3 Exercise 5 Question 16 (Page No. 199)
A combinational circuit is specified by the following three boolean functions. implement the circuit with $3 \times 8$ decoder constructed with NAND gates and three external NAND or AND gates. Use a block diagram for the decoder. Minimize the number of input in the external gates. ... $F _3(A,B,C) = \sum(0,2,3,4,7)$

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 48 views

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Morris Mano Edition 3 Exercise 5 Question 15 (Page No. 199)
A combinational circuit is defined by the following three boolean functions. Design a circuit with a decoder and External Gate. F1 = x’y’z’ + xz F2 = xy’z’ + x’y F3 = x’y’z + xy

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 17 views

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Morris Mano Edition 3 Exercise 5 Question 14 (Page No. 199)
Design a BCD to Decimal decoder using the unused combinations of the BCD code as don’t care conditions.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 14 views

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Morris Mano Edition 3 Exercise 5 Question 13 (Page No. 199)
Design a combinational circuit that compares two 4-bit numbers A and B to check if they are equal. the Circuit has one output x, so that when x = 1 if A = B and x = 0 if A and B is not equal.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 9 views

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Morris Mano Edition 3 Exercise 5 Question 12 (Page No. 199)
It is necessary to design a decimal Adder for two digits represented in Excess-3 code. Show that the correction after adding the two digits with a four-bit binary adder is as follows. The output carry is equal to the carry from ... output carry is 0 then add 1101. construct a four-bit decimal adder using two 4-bit adders and an inverter..

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 52 views

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Morris Mano Edition 3 Exercise 5 Question 11 (Page No. 198)
Construct a 4-digit BCD adder-subtractor using 4 BCD adders. Use the Block diagram for each component, showing only inputs and outputs.

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 20 views

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Morris Mano Edition 3 Exercise 5 Question 10 (Page No. 198)
Design a combinational Circuit that generates the 9’s complement of a BCD digit.?

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 27 views

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27

Morris Mano Edition 3 Exercise 5 Question 9 (Page No. 198)
How many Unused Combinations are there in BCD adder?

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 13 views

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28

Morris Mano Edition 3 Exercise 5 Question 8 (Page No. 198)
Derive the two-level Boolean expression for the output carry $C _5$ shown in the look-ahead carry generator of the figure

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 10 views

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Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
Assume that the EXCLUSIVE-OR gate has a propagation delay of 20ns and that the AND and OR gates have a Propagation delay of 10ns. What is the total Propagation delay time in the four-bit adder of the figure given below?

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 25 views

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Morris Mano Edition 3 Exercise 5 Question 6 (Page No. 198)
(a) Redefine the carry propagate and carry generate as follows: $P _i = A _i + B _ i$ $G _i = A _iB _i$ ... circuit for this IC. [Hint: use the equation substitution method and AND-OR-INVERT funtion given in part (a) for $C _{i+1}$

asked Apr 3 in Digital Logic by ajaysoni1924 Boss (10.5k points) | 38 views

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