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Recent questions tagged combinational-circuits

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Recent questions tagged combinational-circuits

1 vote
3 answers
2
NIELIT 2016 MAR Scientist B - Section C: 2
In which of the following adder circuits, the carry look ripple delay is eliminated? Half adder Full adder Parallel adder Carry-look ahead adder
In which of the following adder circuits, the carry look ripple delay is eliminated? Half adder Full adder Parallel adder Carry-look ahead adder
asked Mar 31, 2020 in Digital Logic Lakshman Patel RJIT 654 views
1 vote
3 answers
3
NIELIT 2016 MAR Scientist B - Section C: 7
How many RAM chips of size $(256K \times 1 \text{ bit})$ are required to build $1$M Byte memory? $8$ $10$ $24$ $32$
How many RAM chips of size $(256K \times 1 \text{ bit})$ are required to build $1$M Byte memory? $8$ $10$ $24$ $32$
asked Mar 31, 2020 in Digital Logic Lakshman Patel RJIT 360 views
0 votes
1 answer
4
NIELIT 2016 MAR Scientist B - Section C: 10
Disadvantage of dynamic RAM over static RAM is higher power consumption. variable speed. need to refresh the capacitor charge every once in two milliseconds. higher bit density.
Disadvantage of dynamic RAM over static RAM is higher power consumption. variable speed. need to refresh the capacitor charge every once in two milliseconds. higher bit density.
asked Mar 31, 2020 in Digital Logic Lakshman Patel RJIT 238 views
2 votes
1 answer
8
NIELIT 2017 July Scientist B (IT) - Section B: 49
Which one of the following is true? NAND gate and AND gate both are universal gates NOR gate and OR gate both are universal gates NAND gate and OR gate both are universal gates NAND gate and NOR gate both are universal gates
Which one of the following is true? NAND gate and AND gate both are universal gates NOR gate and OR gate both are universal gates NAND gate and OR gate both are universal gates NAND gate and NOR gate both are universal gates
asked Mar 30, 2020 in Digital Logic Lakshman Patel RJIT 153 views
0 votes
2 answers
9
NIELIT 2017 July Scientist B (IT) - Section B: 50
Which one of the following is the function of a multiplexer? To decode information To select $1$ out of $N$ input data sources and to transmit it to single channel To transmit data on $N$ lines To perform serial to parallel conversion
Which one of the following is the function of a multiplexer? To decode information To select $1$ out of $N$ input data sources and to transmit it to single channel To transmit data on $N$ lines To perform serial to parallel conversion
asked Mar 30, 2020 in Digital Logic Lakshman Patel RJIT 212 views
0 votes
1 answer
11
NIELIT 2017 July Scientist B (CS) - Section B: 19
To make the following circuit a tautology ‘?’ marked box should be OR gate AND gate NAND gate EX-OR gate
To make the following circuit a tautology ‘?’ marked box should be OR gate AND gate NAND gate EX-OR gate
asked Mar 30, 2020 in Digital Logic Lakshman Patel RJIT 303 views
0 votes
1 answer
13
NIELIT 2017 July Scientist B (CS) - Section B: 21
The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent? NOT OR AND XOR
The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent? NOT OR AND XOR
asked Mar 30, 2020 in Digital Logic Lakshman Patel RJIT 435 views
4 votes
3 answers
14
ISRO2020-12
If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit? BCD code Gray code $8421$ code Excess-$3$ code
If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit? BCD code Gray code $8421$ code Excess-$3$ code
asked Jan 13, 2020 in Digital Logic Satbir 579 views
2 votes
2 answers
15
ISRO2020-11
Minimum number of NAND gates required to implement the following binary equation $Y = (\overline{A}+\overline{B})(C+D)$ $4$ $5$ $3$ $6$
Minimum number of NAND gates required to implement the following binary equation $Y = (\overline{A}+\overline{B})(C+D)$ $4$ $5$ $3$ $6$
asked Jan 13, 2020 in Digital Logic Satbir 868 views
2 votes
3 answers
16
ISRO2020-77
Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\overline{E}+\overline{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\overline{E}+\overline{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
asked Jan 13, 2020 in Digital Logic Satbir 631 views
2 votes
2 answers
17
ISRO2020-10
Following Multiplexer circuit is equivalent to Sum equation of full adder Carry equation of full adder Borrow equation for full subtractor Difference equation of a full subtractor
Following Multiplexer circuit is equivalent to Sum equation of full adder Carry equation of full adder Borrow equation for full subtractor Difference equation of a full subtractor
asked Jan 13, 2020 in Digital Logic Satbir 563 views
3 votes
2 answers
18
ISRO2020-9
In a $8$-bit ripple carry adder using identical full adders, each full adder takes $34$ ns for computing sum. If the time taken for $8$-bit addition is $90$ ns, find time taken by each full adder to find carry. $6$ ns $7$ ns $10$ ns $8$ ns
In a $8$-bit ripple carry adder using identical full adders, each full adder takes $34$ ns for computing sum. If the time taken for $8$-bit addition is $90$ ns, find time taken by each full adder to find carry. $6$ ns $7$ ns $10$ ns $8$ ns
asked Jan 13, 2020 in Digital Logic Satbir 735 views
1 vote
1 answer
19
Recurrence Relation Self-Doubt
What will be solution of recurrence relation if roots are like this: r1=-2, r2=2, r3=-2, r4=2 is this the case of repetitive roots?
What will be solution of recurrence relation if roots are like this: r1=-2, r2=2, r3=-2, r4=2 is this the case of repetitive roots?
asked May 14, 2019 in Combinatory aditi19 153 views
0 votes
1 answer
20
Combination doubt
A shipping clerk has to weigh 10 distinct packets. He weighs them four at a time, weighing all the possible combinations of the packets from the ten. The average weight of all the weighing combination is found to be 800 gm. What is the combined weight of all the size packets?
A shipping clerk has to weigh 10 distinct packets. He weighs them four at a time, weighing all the possible combinations of the packets from the ten. The average weight of all the weighing combination is found to be 800 gm. What is the combined weight of all the size packets?
asked May 7, 2019 in Quantitative Aptitude aditi19 617 views
0 votes
0 answers
21
Morris Mano Edition 3 Exercise 5 Question 35,36 (Page No. 201)
List the PLA programming table for the BCD-to-excess-3-code converter whose boolean functions are given in the figure. repeat the above problem using a PAL.
List the PLA programming table for the BCD-to-excess-3-code converter whose boolean functions are given in the figure. repeat the above problem using a PAL.
asked Apr 4, 2019 in Digital Logic ajaysoni1924 174 views
0 votes
0 answers
22
Morris Mano Edition 3 Exercise 5 Question 34 (Page No. 201)
Derive the PLA Programming table for the combinational circuit that square a 3-bit number.Minimize the number of product term.
Derive the PLA Programming table for the combinational circuit that square a 3-bit number.Minimize the number of product term.
asked Apr 4, 2019 in Digital Logic ajaysoni1924 52 views
0 votes
0 answers
23
Morris Mano Edition 3 Exercise 5 Question 33 (Page No. 201)
Tabulate the PLA programming table for the four boolean functions given. Minimize the number of product terms. $A(x,y,z) = \sum (1,2,4,6)$ $B(x,y,z) = \sum (0,1,6,7)$ $C(x,y,z) = \sum (2,6)$ $D(x,y,z) = \sum (1,2,3,5,7)$
Tabulate the PLA programming table for the four boolean functions given. Minimize the number of product terms. $A(x,y,z) = \sum (1,2,4,6)$ $B(x,y,z) = \sum (0,1,6,7)$ $C(x,y,z) = \sum (2,6)$ $D(x,y,z) = \sum (1,2,3,5,7)$
asked Apr 4, 2019 in Digital Logic ajaysoni1924 330 views
0 votes
0 answers
24
Morris Mano Edition 3 Exercise 5 Question 31 (Page No. 200)
Tabulate a truth table for an $8 \times 4$ ROM that implements the following four boolean functions: $A(x,y,z) = \sum (1,2,4,6)$ $B(x,y,z) = \sum (0,1,6,7)$ $C(x,y,z) = \sum (2,6)$ $D(x,y,z) = \sum (1,2,3,5,7)$
Tabulate a truth table for an $8 \times 4$ ROM that implements the following four boolean functions: $A(x,y,z) = \sum (1,2,4,6)$ $B(x,y,z) = \sum (0,1,6,7)$ $C(x,y,z) = \sum (2,6)$ $D(x,y,z) = \sum (1,2,3,5,7)$
asked Apr 4, 2019 in Digital Logic ajaysoni1924 104 views
0 votes
0 answers
25
Morris Mano Edition 3 Exercise 5 Question 31 (Page No. 200)
specify the size of a ROM ( Number of words and number of bits per words) that will accommodate the truth table for the following combinational circuit components: A binary multiplexer that multiplies two 4-bit numbers. A 4- ... to-1 line multiplexer with common select and enable inputs. A BCD-to-seven-segment decoder with an enable input.
specify the size of a ROM ( Number of words and number of bits per words) that will accommodate the truth table for the following combinational circuit components: A binary multiplexer that multiplies two 4-bit numbers. A 4-bit adder-subtractor. A quadruple 2-to-1 line multiplexer with common select and enable inputs. A BCD-to-seven-segment decoder with an enable input.
asked Apr 4, 2019 in Digital Logic ajaysoni1924 331 views
1 vote
0 answers
26
Morris Mano Edition 3 Exercise 5 Question 30 (Page No. 200)
A ROM chip of 4096 $\times$ 8 bits has two enable inputs and operates from a 5-volt power supply. How many pins are needed for the integrated-circuit package? draw a block diagram and label all the input and output terminals in the ROM
A ROM chip of 4096 $\times$ 8 bits has two enable inputs and operates from a 5-volt power supply. How many pins are needed for the integrated-circuit package? draw a block diagram and label all the input and output terminals in the ROM
asked Apr 4, 2019 in Digital Logic ajaysoni1924 316 views
0 votes
0 answers
27
Morris Mano Edition 3 Exercise 5 Question 29 (Page No. 200)
given a $32 \times 8 $ ROM chip with the enable input, show the external connection which is necessary to construct a $128 \times 8$ ROM with 4 chips and a Decoder.
given a $32 \times 8 $ ROM chip with the enable input, show the external connection which is necessary to construct a $128 \times 8$ ROM with 4 chips and a Decoder.
asked Apr 3, 2019 in Digital Logic ajaysoni1924 168 views
1 vote
1 answer
28
Morris Mano Edition 3 Exercise 5 Question 28 (Page No. 200)
Implement the following boolean function with $4 \times 1$ multiplexer and external gates, connect A and B to selection lines. The input requirement for the four lines will be a function of C and D. These values are obtained by expressing F as a function ... be implemented with the external gates. $F(A,B,C,D) = \sum(1,3,4,11,12,13,14,15)$
Implement the following boolean function with $4 \times 1$ multiplexer and external gates, connect A and B to selection lines. The input requirement for the four lines will be a function of C and D. These values are obtained by expressing F as a function of C and D for each of the four ... These functions may have to be implemented with the external gates. $F(A,B,C,D) = \sum(1,3,4,11,12,13,14,15)$
asked Apr 3, 2019 in Digital Logic ajaysoni1924 282 views
0 votes
0 answers
29
Morris Mano Edition 3 Exercise 5 Question 27 (Page No. 200)
An $8 \times 1$ multiplexer has inputs A,B and C connected to the selection inputs $s _2,s _1$ and $s _0$ respectively.The data inputs $I _0$ through $I _7$ are as follows: $I _1 = I _2 = I _7 = 0$; $ I _3 = I _5 = 1$; $ I _0 = I _4 = D$; and $I _6 = D’$.Determine the boolean function that the multiplexer implements.
An $8 \times 1$ multiplexer has inputs A,B and C connected to the selection inputs $s _2,s _1$ and $s _0$ respectively.The data inputs $I _0$ through $I _7$ are as follows: $I _1 = I _2 = I _7 = 0$; $ I _3 = I _5 = 1$; $ I _0 = I _4 = D$; and $I _6 = D’$.Determine the boolean function that the multiplexer implements.
asked Apr 3, 2019 in Digital Logic ajaysoni1924 75 views
0 votes
0 answers
30
Morris Mano Edition 3 Exercise 5 Question 26 (Page No. 200)
Implement the boolean function $F(A,B,C,D) = \sum(0,1,3,4,8,9,15)$ with an $8 \times 1$multiplexer, but with inputs A,B and C connected to selection inputs $s _2,s _1$ and $s _0$ respectively.
Implement the boolean function $F(A,B,C,D) = \sum(0,1,3,4,8,9,15)$ with an $8 \times 1$multiplexer, but with inputs A,B and C connected to selection inputs $s _2,s _1$ and $s _0$ respectively.
asked Apr 3, 2019 in Digital Logic ajaysoni1924 28 views
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