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Recent questions tagged combinational-circuits

1 vote
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Disadvantage of dynamic RAM over static RAM is higher power consumption. variable speed. need to refresh the capacitor charge every once in two milliseconds. higher bit density.
asked Mar 31 in Digital Logic Lakshman Patel RJIT 79 views
2 votes
1 answer
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Which one of the following is true? NAND gate and AND gate both are universal gates NOR gate and OR gate both are universal gates NAND gate and OR gate both are universal gates NAND gate and NOR gate both are universal gates
asked Mar 30 in Digital Logic Lakshman Patel RJIT 72 views
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Which one of the following is the function of a multiplexer? To decode information To select $1$ out of $N$ input data sources and to transmit it to single channel To transmit data on $N$ lines To perform serial to parallel conversion
asked Mar 30 in Digital Logic Lakshman Patel RJIT 93 views
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If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit? BCD code Gray code $8421$ code Excess-$3$ code
asked Jan 13 in Digital Logic Satbir 434 views
1 vote
2 answers
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Minimum number of NAND gates required to implement the following binary equation $Y = (\overline{A}+\overline{B})(C+D)$ $4$ $5$ $3$ $6$
asked Jan 13 in Digital Logic Satbir 578 views
1 vote
3 answers
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Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\overline{E}+\overline{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
asked Jan 13 in Digital Logic Satbir 426 views
1 vote
2 answers
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Following Multiplexer circuit is equivalent to Sum equation of full adder Carry equation of full adder Borrow equation for full subtractor Difference equation of a full subtractor
asked Jan 13 in Digital Logic Satbir 408 views
1 vote
2 answers
18
In a $8$-bit ripple carry adder using identical full adders, each full adder takes $34$ ns for computing sum. If the time taken for $8$-bit addition is $90$ ns, find time taken by each full adder to find carry. $6$ ns $7$ ns $10$ ns $8$ ns
asked Jan 13 in Digital Logic Satbir 533 views
1 vote
1 answer
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What will be solution of recurrence relation if roots are like this: r1=-2, r2=2, r3=-2, r4=2 is this the case of repetitive roots?
asked May 14, 2019 in Combinatory aditi19 121 views
0 votes
1 answer
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A shipping clerk has to weigh 10 distinct packets. He weighs them four at a time, weighing all the possible combinations of the packets from the ten. The average weight of all the weighing combination is found to be 800 gm. What is the combined weight of all the size packets?
asked May 7, 2019 in Numerical Ability aditi19 366 views
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List the PLA programming table for the BCD-to-excess-3-code converter whose boolean functions are given in the figure. repeat the above problem using a PAL.
asked Apr 4, 2019 in Digital Logic ajaysoni1924 109 views
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Tabulate the PLA programming table for the four boolean functions given. Minimize the number of product terms. $A(x,y,z) = \sum (1,2,4,6)$ $B(x,y,z) = \sum (0,1,6,7)$ $C(x,y,z) = \sum (2,6)$ $D(x,y,z) = \sum (1,2,3,5,7)$
asked Apr 4, 2019 in Digital Logic ajaysoni1924 195 views
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Tabulate a truth table for an $8 \times 4$ ROM that implements the following four boolean functions: $A(x,y,z) = \sum (1,2,4,6)$ $B(x,y,z) = \sum (0,1,6,7)$ $C(x,y,z) = \sum (2,6)$ $D(x,y,z) = \sum (1,2,3,5,7)$
asked Apr 4, 2019 in Digital Logic ajaysoni1924 50 views
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specify the size of a ROM ( Number of words and number of bits per words) that will accommodate the truth table for the following combinational circuit components: A binary multiplexer that multiplies two 4-bit numbers. A 4-bit adder-subtractor. A quadruple 2-to-1 line multiplexer with common select and enable inputs. A BCD-to-seven-segment decoder with an enable input.
asked Apr 4, 2019 in Digital Logic ajaysoni1924 137 views
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A ROM chip of 4096 $\times$ 8 bits has two enable inputs and operates from a 5-volt power supply. How many pins are needed for the integrated-circuit package? draw a block diagram and label all the input and output terminals in the ROM
asked Apr 4, 2019 in Digital Logic ajaysoni1924 135 views
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27
given a $32 \times 8 $ ROM chip with the enable input, show the external connection which is necessary to construct a $128 \times 8$ ROM with 4 chips and a Decoder.
asked Apr 3, 2019 in Digital Logic ajaysoni1924 88 views
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28
Implement the following boolean function with $4 \times 1$ multiplexer and external gates, connect A and B to selection lines. The input requirement for the four lines will be a function of C and D. These values are obtained by expressing F as a function of C and D for each of the four ... These functions may have to be implemented with the external gates. $F(A,B,C,D) = \sum(1,3,4,11,12,13,14,15)$
asked Apr 3, 2019 in Digital Logic ajaysoni1924 173 views
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An $8 \times 1$ multiplexer has inputs A,B and C connected to the selection inputs $s _2,s _1$ and $s _0$ respectively.The data inputs $I _0$ through $I _7$ are as follows: $I _1 = I _2 = I _7 = 0$; $ I _3 = I _5 = 1$; $ I _0 = I _4 = D$; and $I _6 = D’$.Determine the boolean function that the multiplexer implements.
asked Apr 3, 2019 in Digital Logic ajaysoni1924 42 views
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Implement the boolean function $F(A,B,C,D) = \sum(0,1,3,4,8,9,15)$ with an $8 \times 1$multiplexer, but with inputs A,B and C connected to selection inputs $s _2,s _1$ and $s _0$ respectively.
asked Apr 3, 2019 in Digital Logic ajaysoni1924 19 views
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