search
Log In

Recent questions tagged computer

0 votes
0 answers
1
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?
asked May 21, 2019 in CO and Architecture Ritabrata Dey 108 views
1 vote
1 answer
2
Suppose a process in Host C has a UDP socket with port number 6789. Suppose both Host A and Host B each send a UDP segment to Host C with destination port number 6789. Will both of these segments be directed to the same socket at Host C? If so, how will the process at Host C know that these two segments originated from two different hosts?
asked Apr 18, 2019 in Computer Networks ajaysoni1924 121 views
1 vote
1 answer
3
In a LAN network every system is identified by (a) Name (b) MAC Address (c) IP Address (d) Serial number given by manufacturer the answer is given as IP address but according to me it should be MAC address.
asked Feb 17, 2019 in Computer Networks *p 4.8k views
0 votes
0 answers
4
In an enhanced CPU, the speed of a floating point operations has been increased by 30% and the speed of a fixed point operations has been increased by 20%. In the original design floating point operations used to take twice the time compared to fixed point operations ... number of floating point instructions to the number of fixed point instructions is 2 : 3 is ________. (Upto 2 decimal places)
asked Jan 19, 2019 in CO and Architecture balchandar reddy san 87 views
0 votes
0 answers
5
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 2 MSS and the threshold at the start of 1 st transmission is 16 MSS. Assume TCP use over a lossy link i.e., timeout occur ... given window at the start of slow start phase is 2 MSS ;so when timeout occur should'nt we start with window size of 2 MSS]
asked Jan 7, 2019 in Computer Networks newdreamz a1-z0 114 views
0 votes
0 answers
7
Consider Prof. Vamshi s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy used. If base address of array 'a is 0x0 and initially cache is ... [i] + a[1024* i]; what will be the physical memory size here?and how many bits should we assign for physical memory addressing?
asked Dec 25, 2018 in CO and Architecture newdreamz a1-z0 124 views
1 vote
1 answer
8
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided into 2 sub stages, (EX1 and ... 20% of the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825
asked Dec 25, 2018 in CO and Architecture newdreamz a1-z0 226 views
0 votes
0 answers
9
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz explain?
asked Dec 12, 2018 in CO and Architecture sushmita 50 views
0 votes
0 answers
10
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand ... we use signed 2's complement instead of unsigned integer then what will be the maximum and minimum value of the immediate operand ?
asked Nov 25, 2018 in CO and Architecture night_fury 67 views
0 votes
0 answers
12
Which addressing mode is best suited for runtime relocation. Which addressing mode is best suited for compile time relocation.
asked Aug 4, 2018 in CO and Architecture iamdeepakji 16 views
0 votes
0 answers
13
Assume there are 34 different op-codes, 64 registers in the machine. Main memory size is 256 KB and number of addressing modes for each operand is 14. Every instruction has one source operand in register and another operand in memory. Find number of bits to encode an instruction. a). 38 b). 34 c). 32 d). 30
asked Jun 29, 2018 in CO and Architecture ds2905902 17 views
0 votes
0 answers
14
In a computing center there are four types of jobs according to their arrival times (in seconds), their priorities and their run times (in seconds); see the table below: -----------------Type 1------ Type 2---- Type 3---- Type 4 arrival ... robin on every priority level - the higher the priority, the sooner they run) scheduling algorithm. [please use a quantum that provides short response time.]
asked Apr 11, 2018 in Operating System ytr567 447 views
1 vote
0 answers
15
a) Assume each router implements FIFO queuing. If each flow consists of an identical, 1-Mbps constant bit rate UDP flow with equal packet sizes, what will the resulting rate be for each flow? You can assume that FIFO drops packets with uniform probability. b) Now consider ... and each flow is assigned a weight equal to its number (i.e., flow F4 gets weight 4). What are the resulting throughputs?
asked Jan 29, 2018 in Computer Networks Balaji Jegan 60 views
1 vote
0 answers
16
Can we say any thing to computer if they haven't storage unit? Or First computer like abacas have storage unit ? What is current definition of computer:: My answer is : a system that have these 5 property is a computer::: 1.Electronic device 2.Take inputs (data ... ) 5.Storage A person said this is wrong definition.. Then what is the current definition? And he said old computer hasn't storage unit
asked Jan 18, 2018 in CO and Architecture Harikesh Kumar 67 views
1 vote
0 answers
17
why are WAR AND WAW hazards not possible in mips architecture please see this video at 17:58 youtube.com/watch?v=9mpOG9YtSLc&t=1242s
asked Jan 5, 2018 in CO and Architecture Venkat Sai 77 views
0 votes
0 answers
18
A virtual memory has a page size 1k words.there are 8 pages and 4 frames.associative memory page table contain following entries : page frame 6 0 1 1 4 2 0 3 which of following virtual address(decimal) will cause page fault? a)4098 b)5124 c)1022 d)6144
asked Nov 17, 2017 in CO and Architecture rohit vishkarma 100 views
0 votes
1 answer
19
2 votes
0 answers
20
I understand what is little endian and big endian. Suppose $\text{90AB12CD}_{16}$, this is the integer that is supposed to be stored in the memory. Then in big endian, we store like this. The most significant byte at the lower address. . But I don't understand ... Which is quite strange for me, because most of the time we think, the first byte is from the rightmost side. Please, someone, confirm.
asked Oct 22, 2017 in CO and Architecture Hemant Parihar 648 views
5 votes
2 answers
21
16 bit Floating Point Representation $(-1)^{sign}*(1.M)*2^{Exp - 63}$ Sign = 1 bit Exponent = 7 bit Mantissa = 8 bit 1) Max positive number 2) Min positive number. 3) Max negative number. 4) Min negative number. 5) What is meant by precision.
asked Sep 4, 2017 in CO and Architecture Shubhanshu 1.2k views
1 vote
0 answers
22
Message digest provides only message authentication or can it provide user authentication also? MDC is a digest for message authentication.Can i also say MAC is also a digest for sender authentication?Please explain this
asked Aug 13, 2017 in Computer Networks rahul sharma 5 108 views
3 votes
2 answers
23
The physical address size on a machine is 36 bits.The number of tag bits in the physical address format in a 256 KB, 16 way block set associative cache is____bits. What will be the ans?
asked Aug 9, 2017 in CO and Architecture avinash41 259 views
0 votes
0 answers
24
Let m be the message and c be the cipher text. public key=(e,n) and private key=(d,n) c=pe mod(n) Now, raising c to power of d mod(n), we get plain text p = cd mod(n)=ped mod(n). Now since p=ped mod(n), this condition should be true : ed=1 mod(Φ(n)). I didn't understand this equation.
asked Jun 9, 2017 in Computer Networks Bad_Doctor 120 views
0 votes
1 answer
25
What is the meaning of processing time at source and destination? Under processing time what task happens?
asked Apr 21, 2017 in Computer Networks Shubhanshu 67 views
1 vote
1 answer
26
0 votes
1 answer
27
An organization has a class C network and wants to form a subnet for four departments with hosts as follows: A:72 B:35 C:20 D:18 what is the possible arrangements? options: a) for A: 255.255.255.128 for B: 255.255.255.192 for C & D: 255.255.255.223 b)for ... are possible. so option A is not possible. But answer given is option A. I know i am lacking some concept here , please care to correct :)
asked Jan 12, 2017 in Computer Networks vishwa ratna 1k views
0 votes
0 answers
28
Assume bit error of 2*(10^-4).What maximum size block is possible if probability that a block containing an error is to be no longer than 10^-1 ?
asked Dec 25, 2016 in Computer Networks Ravi_1511 60 views
2 votes
1 answer
29
Why increase in cache size doesnt affect conflict misses?? According to me when we will increase cache size number of blocks will increase and hence lesser no of conflicts will be there because less number of main memory blocks will contend for same cache line?? But its said that conflict miss is independent of cache size how?? This seems so confusing to me.
asked Dec 12, 2016 in CO and Architecture sushmita 205 views
...