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Recent questions tagged computer
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#Self doubt COA
Çșȇ ʛấẗẻ
309
views
Çșȇ ʛấẗẻ
asked
Feb 16
CO and Architecture
computer
co-and-architecture
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–
1
votes
1
answer
2
Write regular expression to denote a language L a) String which begin or end with either 00 or 11. b) The set of all strings, when viewed as binary representation of integers, that are divisible by 2. c) The set of all strings containing 00. d) String not containing the substring 110.
Write regular expression to denote a language La) String which begin or end with either 00 or 11.b) The set of all strings, when viewed as binary representation of intege...
M_Umair_Khan42900
2.1k
views
M_Umair_Khan42900
asked
Dec 29, 2022
Theory of Computation
theory-of-computation
regular-expression
finite-automata
pushdown-automata
minimal-state-automata
computer
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–
2
votes
0
answers
3
Applied Test Series
An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate effective address if the addressing mode of the instruction is Index with R1 as the index register.
An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Eva...
LRU
881
views
LRU
asked
Oct 24, 2021
CO and Architecture
test-series
computer
co-and-architecture
addressing-modes
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–
3
votes
1
answer
4
Kurose and Ross Edition 6 Exercise 3 Question R7 (Page No 286)
Suppose a process in Host C has a UDP socket with port number 6789. Suppose both Host A and Host B each send a UDP segment to Host C with destination port number 6789. Will both of these segments be directed to the same ... Host C? If so, how will the process at Host C know that these two segments originated from two different hosts?
Suppose a process in Host C has a UDP socket with port number 6789. Suppose both Host A and Host B each send a UDP segment to Host C with destination port number 6789. Wi...
ajaysoni1924
2.2k
views
ajaysoni1924
asked
Apr 18, 2019
Computer Networks
computer
transport-layer
descriptive
udp
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–
1
votes
1
answer
5
In a LAN network every system is identified by ?
In a LAN network every system is identified by (a) Name (b) MAC Address (c) IP Address (d) Serial number given by manufacturer the answer is given as IP address but according to me it should be MAC address.
In a LAN network every system is identified by(a) Name(b) MAC Address(c) IP Address(d) Serial number given by manufacturerthe answer is given as IP address but according ...
*p
16.7k
views
*p
asked
Feb 17, 2019
Computer Networks
computer
computer-networks
ip
ip-addressing
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–
1
votes
0
answers
6
me test
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 2 MSS and the threshold at the start of 1 st transmission is 16 MSS. Assume TCP use over a lossy link i.e., timeout ... window at the start of slow start phase is 2 MSS ;so when timeout occur should'nt we start with window size of 2 MSS]
Consider an instance of TCP's Additive Increase Multiplicative Decrease (AIMD) algorithm where the window size at the start of slow start phase is 2 MSS and the threshold...
newdreamz a1-z0
480
views
newdreamz a1-z0
asked
Jan 7, 2019
Computer Networks
computer
computer-networks
congestion-control
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–
0
votes
0
answers
7
made easy mock 1 q63
ANY BODY TRY OUT I GOT 4/11 = 0.36
ANY BODY TRY OUT I GOT 4/11 = 0.36
CHïntän ÞäTël
386
views
CHïntän ÞäTël
asked
Jan 1, 2019
CO and Architecture
made-easy-test-series
computer
co-and-architecture
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–
0
votes
0
answers
8
ME TEST
Consider Prof. Vamshi s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 bits and LRU replacement policy used. If base address of array 'a is 0x0 and initially ... i] + a[1024* i]; what will be the physical memory size here?and how many bits should we assign for physical memory addressing?
Consider Prof. Vamshi‘s writes a program given below and run on system which has 2-way set associative 16 KB data cache with 32 bytes block where each word size is 32 b...
newdreamz a1-z0
457
views
newdreamz a1-z0
asked
Dec 25, 2018
CO and Architecture
computer
co-and-architecture
cache-memory
misses
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–
1
votes
1
answer
9
ME test series
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided ... the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline ...
newdreamz a1-z0
736
views
newdreamz a1-z0
asked
Dec 25, 2018
CO and Architecture
computer
co-and-architecture
pipelining
speedup
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–
0
votes
0
answers
10
General doubt.
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz explain?
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz expl...
sushmita
254
views
sushmita
asked
Dec 12, 2018
CO and Architecture
computer
co-and-architecture
cache-memory
effective-memory-access
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–
0
votes
0
answers
11
doubt
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate ... we use signed 2's complement instead of unsigned integer then what will be the maximum and minimum value of the immediate operand ?
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an...
night_fury
487
views
night_fury
asked
Nov 25, 2018
CO and Architecture
computer
co-and-architecture
doubt
numerical-answers
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–
1
votes
1
answer
12
Ace Test Series: Computer Networks - RSA Algorithm
Shankar Kakde
481
views
Shankar Kakde
asked
Nov 1, 2018
Computer Networks
computer
network-security
rsa-security-networks
ace-test-series
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–
0
votes
0
answers
13
self doubt
Which addressing mode is best suited for runtime relocation. Which addressing mode is best suited for compile time relocation.
Which addressing mode is best suited for runtime relocation.Which addressing mode is best suited for compile time relocation.
iamdeepakji
223
views
iamdeepakji
asked
Aug 4, 2018
CO and Architecture
computer
io-organization
+
–
0
votes
0
answers
14
self doubt
Assume there are 34 different op-codes, 64 registers in the machine. Main memory size is 256 KB and number of addressing modes for each operand is 14. Every instruction has one source operand in register and another operand in memory. Find number of bits to encode an instruction. a). 38 b). 34 c). 32 d). 30
Assume there are 34 different op-codes, 64 registers in the machine. Main memory size is 256 KB and number of addressing modes for each operand is 14. Every instruction h...
ds2905902
187
views
ds2905902
asked
Jun 29, 2018
CO and Architecture
computer
co-and-architecture
+
–
0
votes
0
answers
15
Computing the average turnaround time using the multilevel queues
In a computing center there are four types of jobs according to their arrival times (in seconds), their priorities and their run times (in seconds); see the table below: -----------------Type 1------ ... - the higher the priority, the sooner they run) scheduling algorithm. [please use a quantum that provides short response time.]
In a computing center there are four types of jobs according to theirarrival times (in seconds), their priorities and their run times (in seconds);see the table below: ...
ytr567
791
views
ytr567
asked
Apr 11, 2018
Operating System
runtime-environment
round-robin-scheduling
computer
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–
1
votes
0
answers
16
Univeristy of California Finals
a) Assume each router implements FIFO queuing. If each flow consists of an identical, 1-Mbps constant bit rate UDP flow with equal packet sizes, what will the resulting rate be for each flow? You can assume that FIFO drops packets with uniform probability. ... is assigned a weight equal to its number (i.e., flow F4 gets weight 4). What are the resulting throughputs?
a) Assume each router implements FIFO queuing. If each flow consists of an identical, 1-Mbps constant bit rate UDP flow with equal packet sizes, what will the resulting r...
Balaji Jegan
364
views
Balaji Jegan
asked
Jan 29, 2018
Computer Networks
routers-bridge-hubs-switches
computer-networks
computer
networking
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–
1
votes
0
answers
17
Self knowlaged
Can we say any thing to computer if they haven't storage unit? Or First computer like abacas have storage unit ? What is current definition of computer:: My answer is : a system that have these 5 property is a computer::: 1.Electronic device ... Storage A person said this is wrong definition.. Then what is the current definition? And he said old computer hasn't storage unit
Can we say any thing to computer if they haven't storage unit?Or First computer like abacas have storage unit ?What is current definition of computer::My answer is : a sy...
Harikesh Kumar
205
views
Harikesh Kumar
asked
Jan 18, 2018
CO and Architecture
operating-system
computer
io-organization
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–
2
votes
0
answers
18
nptel course
why are WAR AND WAW hazards not possible in mips architecture please see this video at 17:58 youtube.com/watch?v=9mpOG9YtSLc&t=1242s
why are WAR AND WAW hazards not possible in mips architecture please see this video at 17:58 youtube.com/watch?v=9mpOG9YtSLc&t=1242s
Venkat Sai
271
views
Venkat Sai
asked
Jan 5, 2018
CO and Architecture
nptel
computer
co-and-architecture
+
–
0
votes
0
answers
19
test book test series 2018
A virtual memory has a page size 1k words.there are 8 pages and 4 frames.associative memory page table contain following entries : page frame 6 0 1 1 4 2 0 3 which of following virtual address(decimal) will cause page fault? a)4098 b)5124 c)1022 d)6144
A virtual memory has a page size 1k words.there are 8 pages and 4 frames.associative memory page tablecontain following entries :page frame6 ...
rohit vishkarma
329
views
rohit vishkarma
asked
Nov 17, 2017
CO and Architecture
virtual-memory-
computer
io-organization
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–
0
votes
1
answer
20
ace test series 2018
rohit vishkarma
412
views
rohit vishkarma
asked
Oct 31, 2017
Computer Networks
computer
network
cidr
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–
8
votes
2
answers
21
Maximum and Minimum number in 16 bit Floating Point
16 bit Floating Point Representation $(-1)^{sign}*(1.M)*2^{Exp - 63}$ Sign = 1 bit Exponent = 7 bit Mantissa = 8 bit 1) Max positive number 2) Min positive number. 3) Max negative number. 4) Min negative number. 5) What is meant by precision.
16 bit Floating Point Representation$(-1)^{sign}*(1.M)*2^{Exp - 63}$Sign = 1 bitExponent = 7 bitMantissa = 8 bit1) Max positive number2) Min positive number.3) Max negati...
Shubhanshu
3.9k
views
Shubhanshu
asked
Sep 3, 2017
CO and Architecture
floating-point-representation
ieee-representation
co-and-architecture
computer
computer-networks
digital-logic
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–
1
votes
0
answers
22
CN Network Security
Message digest provides only message authentication or can it provide user authentication also? MDC is a digest for message authentication.Can i also say MAC is also a digest for sender authentication?Please explain this
Message digest provides only message authentication or can it provide user authentication also?MDC is a digest for message authentication.Can i also say MAC is also a dig...
rahul sharma 5
292
views
rahul sharma 5
asked
Aug 13, 2017
Computer Networks
computer-networks
computer
rsa-security-networks
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–
3
votes
2
answers
23
set associative cache
The physical address size on a machine is 36 bits.The number of tag bits in the physical address format in a 256 KB, 16 way block set associative cache is____bits. What will be the ans?
The physical address size on a machine is 36 bits.The number of tag bits in the physical address format in a 256 KB, 16 way block set associative cache is____bits.What wi...
avinash41
782
views
avinash41
asked
Aug 9, 2017
CO and Architecture
cache-memory
computer
co-and-architecture
+
–
0
votes
1
answer
24
Self Doubt
What is the meaning of processing time at source and destination? Under processing time what task happens?
What is the meaning of processing time at source and destination? Under processing time what task happens?
Shubhanshu
241
views
Shubhanshu
asked
Apr 21, 2017
Computer Networks
computer
+
–
1
votes
1
answer
25
RSA(self doubt)
gabbar
635
views
gabbar
asked
Apr 2, 2017
Computer Networks
computer
networking
+
–
0
votes
1
answer
26
Ace CN question
An organization has a class C network and wants to form a subnet for four departments with hosts as follows: A:72 B:35 C:20 D:18 what is the possible arrangements? options: a) for A: 255.255.255.128 for B: 255.255.255.192 for C & D: 255.255. ... possible. so option A is not possible. But answer given is option A. I know i am lacking some concept here , please care to correct :)
An organization has a class C network and wants to form a subnet for four departments with hosts as follows:A:72B:35C:20D:18what is the possible arrangements?options:a) f...
vishwa ratna
3.2k
views
vishwa ratna
asked
Jan 12, 2017
Computer Networks
computer
computer-networks
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–
0
votes
0
answers
27
Gate Practice Question
Assume bit error of 2*(10^-4).What maximum size block is possible if probability that a block containing an error is to be no longer than 10^-1 ?
Assume bit error of 2*(10^-4).What maximum size block is possible if probability that a block containing an error is to be no longer than 10^-1 ?
Ravi_1511
229
views
Ravi_1511
asked
Dec 25, 2016
Computer Networks
computer
network
+
–
2
votes
1
answer
28
general conceptual doubt
Why increase in cache size doesnt affect conflict misses?? According to me when we will increase cache size number of blocks will increase and hence lesser no of conflicts will be there because less number of main memory blocks will contend for same cache line?? But its said that conflict miss is independent of cache size how?? This seems so confusing to me.
Why increase in cache size doesnt affect conflict misses??According to me when we will increase cache size number of blocks will increase and hence lesser no of conflicts...
sushmita
649
views
sushmita
asked
Dec 12, 2016
CO and Architecture
computer
co-and-architecture
+
–
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