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Recent questions tagged co-and-architecture
0
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BARC 2024 CSE
How many 256 X 1K bit chips are required to build 1 MB of memory?
How many 256 X 1K bit chips are required to build 1 MB of memory?
Ayanava Dutta
85
views
Ayanava Dutta
asked
Mar 17
CO and Architecture
easy
co-and-architecture
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–
0
votes
0
answers
2
#Self doubt COA
Çșȇ ʛấẗẻ
311
views
Çșȇ ʛấẗẻ
asked
Feb 16
CO and Architecture
computer
co-and-architecture
+
–
1
votes
1
answer
3
GATE CSE 2024 | Set 2 | Question: 1
Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per ... $\text{DMA}$? $2,56,000$ $3,200$ $25,60,000$ $32,000$
Consider a computer with a $4 \mathrm{MHz}$ processor. Its $\text{DMA}$ controller can transfer $8$ bytes in $1$ cycle from a device to main memory through cycle...
Arjun
2.2k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set2
co-and-architecture
+
–
1
votes
1
answer
4
GATE CSE 2024 | Set 2 | Question: 21
An instruction format has the following structure: Instruction Number: Opcode destination reg, source reg-$1$, source reg-$2$ Consider the following sequence of instructions to be executed in a pipelined processor: $\text{I 1: DIV R3, R1, R2}$ ... $\text{I 3}$ There is a WAW dependency on $\text{R 3}$ between $\text{I 3}$ and $\text{I 4}$
An instruction format has the following structure:Instruction Number: Opcode destination reg, source reg-$1$, source reg-$2$ Consider the following sequenc...
Arjun
1.7k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set2
co-and-architecture
multiple-selects
+
–
2
votes
1
answer
5
GATE CSE 2024 | Set 2 | Question: 47
A processor with $16$ general purpose registers uses a $32$-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a $16$-bit scalar field. If $8$ addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ___________.
A processor with $16$ general purpose registers uses a $32$-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two regi...
Arjun
1.5k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set2
numerical-answers
co-and-architecture
+
–
2
votes
0
answers
6
GATE CSE 2024 | Set 2 | Question: 48
A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ cycles to execute an instruction of a program $\text{P}$. The unit is then redesigned to operate on a $5$ ... hazards. The speedup (rounded off to one decimal place) obtained by the pipelined design over the non-pipelined design is ____________.
A non-pipelined instruction execution unit operating at $2 \mathrm{GHz}$ takes an average of $6$ cycles to execute an instruction of a program $\text{P}$. The unit is the...
Arjun
1.5k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set2
numerical-answers
co-and-architecture
pipelining
+
–
1
votes
1
answer
7
GATE CSE 2024 | Set 2 | Question: 51
A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instructions are equally divided into two types, namely $\text{R}$ ... the number of bits used to encode the immediate value/address field. The value of $\text{X+2Y+Z}$ is __________.
A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instruc...
Arjun
1.6k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set2
numerical-answers
co-and-architecture
+
–
0
votes
2
answers
8
GATE CSE 2024 | Set 1 | Question: 5
Which one of the following statements is FALSE? In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle For bulk data transfer, the burst mode of ... driven I/O mechanism The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts
Which one of the following statements is FALSE?In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a s...
Arjun
2.0k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set1
co-and-architecture
+
–
2
votes
2
answers
9
GATE CSE 2024 | Set 1 | Question: 20
Consider a $5$-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are ... cannot prevent all pipeline stalls Forwarding does not require any extra hardware to retrieve the data from the pipeline stages
Consider a $5$-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Whic...
Arjun
3.7k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set1
multiple-selects
co-and-architecture
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–
1
votes
2
answers
10
GATE CSE 2024 | Set 1 | Question: 43
Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy. Both of them use the $\text{LRU}$ (Least Recently Used) block ... write miss in $\text{WTC}$ always writes the victim cache block to main memory before loading the missed block to the cache
Consider two set-associative cache memory architectures: $\text{WBC}$, which uses the write back policy, and $\text{WTC}$, which uses the write through policy...
Arjun
1.9k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set1
co-and-architecture
cache-memory
multiple-selects
+
–
0
votes
2
answers
11
GATE CSE 2024 | Set 1 | Question: 45
The baseline execution time of a program on a $2 \mathrm{GHz}$ single core machine is $100$ nanoseconds ( $n s)$. The code corresponding to $90 \%$ of the execution time can be fully parallelized. The overhead for using an ... the parallelized code for an equal amount of time. The number of cores that minimize the execution time of the program is __________.
The baseline execution time of a program on a $2 \mathrm{GHz}$ single core machine is $100$ nanoseconds ( $n s)$. The code corresponding to $90 \%$ of the execution time ...
Arjun
1.5k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set1
numerical-answers
co-and-architecture
+
–
1
votes
2
answers
12
GATE CSE 2024 | Set 1 | Question: 46
A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program exhibits $2 \%$ miss rate on instruction cache and $8 \%$ miss rate on data ... rounded off to two decimal places) achieved with a perfect cache (i.e., with NO data or instruction cache misses) is __________.
A given program has $25 \%$ load/store instructions. Suppose the ideal $\text{CPI}$ (cycles per instruction) without any memory stalls is $2$. The program exhibits $2 \%$...
Arjun
2.4k
views
Arjun
asked
Feb 16
CO and Architecture
gatecse2024-set1
numerical-answers
co-and-architecture
+
–
0
votes
0
answers
13
COA Self doubt
Çșȇ ʛấẗẻ
83
views
Çșȇ ʛấẗẻ
asked
Feb 15
Mathematical Logic
co-and-architecture
self-doubt
+
–
4
votes
1
answer
14
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 55
Consider the cache of size 512 bytes that is direct-mapped? Suppose the size of integer is 4 bytes and block size is 16 bytes. Assume cache is initially empty and all data except for the array x are stored in registers, and that the ... ) { sum += x[i]; } What is the miss rate for the above loop? (roundoff to two decimal places)
Consider the cache of size 512 bytes that is direct-mapped?Suppose the size of integer is 4 bytes and block size is 16 bytes. Assume cache is initially empty and all data...
GO Classes
390
views
GO Classes
asked
Feb 5
CO and Architecture
goclasses2024-mockgate-14
numerical-answers
co-and-architecture
cache-memory
page-fault
2-marks
+
–
5
votes
1
answer
15
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 62
At a particular point in time, the buffer cache has dirty data that needs to be flushed to disk. Suppose that the identities of these blocks can be listed in [track:sector] form as follows: ... Shortest Seek Time First Scan (initially moving upwards) Look (initially moving upwards) C-SCAN (initially moving upwards)
At a particular point in time, the buffer cache has dirty data that needs to be flushed to disk. Suppose that the identities of these blocks can be listed in [track:secto...
GO Classes
391
views
GO Classes
asked
Feb 5
CO and Architecture
goclasses2024-mockgate-14
co-and-architecture
disk-scheduling
multiple-selects
2-marks
+
–
11
votes
1
answer
16
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 63
Assume an instruction mix of $15 \%$ conditional branches, $1 \%$ unconditional branches, $84 \%$ all others, and $60 \%$ of the conditional branches are taken. We have a 4-stage pipeline where branch target locations ... $1.38$ For both "predict taken", "predict not taken" branch predictions, CPI is the $1.30$
Assume an instruction mix of $15 \%$ conditional branches, $1 \%$ unconditional branches, $84 \%$ all others, and $60 \%$ of the conditional branches are taken. We have a...
GO Classes
706
views
GO Classes
asked
Feb 5
CO and Architecture
goclasses2024-mockgate-14
co-and-architecture
branch-conditional-instructions
2-marks
+
–
2
votes
1
answer
17
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 34
In typical RISC ISA, delayed branch executes which instruction irrespective of whether the branch condition is true or false? Instruction immediately following the branch condition Instruction immediately preceding the branch condition Instruction that belongs to a different a subroutine It waits till the branch condition is evaluated
In typical RISC ISA, delayed branch executes which instruction irrespective of whether the branch condition is true or false?Instruction immediately following the branch ...
GO Classes
373
views
GO Classes
asked
Jan 28
CO and Architecture
goclasses2024-mockgate-13
goclasses
co-and-architecture
branch-conditional-instructions
1-mark
+
–
7
votes
1
answer
18
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 35
Consider a processor with an in-order five-stage pipeline (IF, ID, EX, MEM, and WB) with clock cycle time $10 \mathrm{~ns}$. This processor is executing a program in which $30 \%$ of the instructions are ... is always started and ignored if the branch is taken. What is the throughput (Million instructions per second) of the system?
Consider a processor with an in-order five-stage pipeline (IF, ID, EX, MEM, and WB) with clock cycle time $10 \mathrm{~ns}$. This processor is executing a program in whic...
GO Classes
630
views
GO Classes
asked
Jan 28
CO and Architecture
goclasses2024-mockgate-13
goclasses
co-and-architecture
pipelining
numerical-answers
1-mark
+
–
9
votes
2
answers
19
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 53
Suppose we use $\textsf{IEEE-754}$ single precision floating point format to represent the numbers in binary. What will be the hexadecimal representation of $-2^{-146}?$ $\textsf{0x80000004}$ $\textsf{0x80000008}$ $\textsf{0x80000010}$ $\textsf{0x80000002}$
Suppose we use $\textsf{IEEE-754}$ single precision floating point format to represent the numbers in binary. What will be the hexadecimal representation of $-2^{-146}?$$...
GO Classes
729
views
GO Classes
asked
Jan 28
CO and Architecture
goclasses2024-mockgate-13
goclasses
co-and-architecture
number-representation
ieee-representation
2-marks
+
–
6
votes
1
answer
20
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 54
Assume a cache memory with the following properties: The cache size $\text{(C)}$ is 512 bytes (contains $512$ data bytes) The cache uses an LRU (least recently used) policy for eviction. The cache is initially empty. Suppose that for the following ... cache? $\text{B}=4$ bytes $\text{B}=8$ bytes $\text{B}=16$ bytes None of the above.
Assume a cache memory with the following properties:The cache size $\text{(C)}$ is 512 bytes (contains $512$ data bytes)The cache uses an LRU (least recently used) policy...
GO Classes
696
views
GO Classes
asked
Jan 28
CO and Architecture
goclasses2024-mockgate-13
goclasses
co-and-architecture
cache-memory
2-marks
+
–
4
votes
1
answer
21
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 58
Your code is required to perform the function $(\text{M}\%16) \ast 3.$ What should you do to eliminate multiplication ($\ast$) and mod($\%$), assuming $\mathrm{M}$ is $32$ bits wide? shift $\text{M}$ right by $4,$ ... $0000000 \mathrm{Fh}$, save the result, shift result left by $2,$ and add the saved result to current result.
Your code is required to perform the function $(\text{M}\%16) \ast 3.$ What should you do to eliminate multiplication ($\ast$) and mod($\%$), assuming $\mathrm{M}$ is $32...
GO Classes
381
views
GO Classes
asked
Jan 28
CO and Architecture
goclasses2024-mockgate-13
goclasses
co-and-architecture
number-representation
2-marks
+
–
1
votes
3
answers
22
MADE EASY TEST SERIES 2024 #COA
Consider 16 bit CPU with 4 GB RAM supports 2 Address Instruction with Address 1 uses direct addressing mode Address2 uses indirect addressing mode. Opcode is designed as ADD operation with Address 1 used as Source1 and Destination, Address2 used ... operation consumes 4 cycles. Memory reference consumes 6 cycles. Time required to complete the instruction is in (ns).
Consider 16 bit CPU with 4 GB RAM supports 2 Address Instruction with Address 1 uses direct addressing mode Address2 uses indirect addressing mode. Opcode is designed as ...
Shaikh727
369
views
Shaikh727
asked
Jan 24
CO and Architecture
co-and-architecture
made-easy-test-series
addressing-modes
+
–
3
votes
2
answers
23
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 5
Suppose we have a four-way set associative physically addressed cache of size $256 \mathrm{KB}$ and $\text{16B}$ blocks, on a machine that uses $32$-bit physical addresses. How many bits will be used for the index?
Suppose we have a four-way set associative physically addressed cache of size $256 \mathrm{KB}$ and $\text{16B}$ blocks, on a machine that uses $32$-bit physical addresse...
GO Classes
482
views
GO Classes
asked
Jan 21
CO and Architecture
goclasses2024-mockgate-12
goclasses
numerical-answers
co-and-architecture
cache-memory
1-mark
+
–
6
votes
1
answer
24
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 20
The clock rate for Machine $\mathrm{A}$ is $2.4 \mathrm{GHz}$, and the clock rate for machine $\text{B}$ is $3.0 \mathrm{GHz}$. For a particular program, the average CPI on machine $\text{A}$ is $1.2.$ For the same program, the average ... Machine $\text{B}$, with respect to this program. What is $\mathrm{K}?$ $1$ $4 / 3$ $2$ $3 / 4$
The clock rate for Machine $\mathrm{A}$ is $2.4 \mathrm{GHz}$, and the clock rate for machine $\text{B}$ is $3.0 \mathrm{GHz}$. For a particular program, the average CPI ...
GO Classes
602
views
GO Classes
asked
Jan 21
CO and Architecture
goclasses2024-mockgate-12
goclasses
co-and-architecture
machine-instruction
1-mark
+
–
7
votes
3
answers
25
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 48
Consider a processor with a branch-if-equal instruction that is $32$ bits long$\textsf{: BEQ R12, R11, X.}$ $6$ bits are used to encode the opcode, $6$ bits are used to encode one register number, $6$ bits ... $4$ bytes long. How many instructions away (the number of instructions) from the $\textsf{BEQ}$ instruction could we reach?
Consider a processor with a branch-if-equal instruction that is $32$ bits long$\textsf{: BEQ R12, R11, X.}$ $6$ bits are used to encode the opcode, $6$ bits are used to e...
GO Classes
610
views
GO Classes
asked
Jan 21
CO and Architecture
goclasses2024-mockgate-12
goclasses
numerical-answers
co-and-architecture
branch-conditional-instructions
2-marks
+
–
7
votes
1
answer
26
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 49
Consider the following code fragment: Identify all data dependencies (potential data hazards) in the given code snippet within one loop iteration. Let the number of true data dependencies be $\mathrm{X}$ ... output dependencies be $\text{Z}$. What is $\mathrm{X}+2 \mathrm{Y}+3 \mathrm{Z}?$
Consider the following code fragment:Identify all data dependencies (potential data hazards) in the given code snippet within one loop iteration. Let the number of true d...
GO Classes
942
views
GO Classes
asked
Jan 21
CO and Architecture
goclasses2024-mockgate-12
goclasses
numerical-answers
co-and-architecture
data-hazards
data-dependency
2-marks
+
–
8
votes
1
answer
27
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 50
A computer has a $32$-bit address bus with a direct mapped cache, using $4$ bits for block offset, $16$ tag bits, and $12$ index bits. Which of the following address pairs can be placed in the cache simultaneously? $\textsf{3AC6 F45 6}$ ... $\textsf{5E3C 768 0}$ and $\textsf{8F3C 768 A}$ $\textsf{2233 445 5}$ and $\textsf{2233 445 C}$
A computer has a $32$-bit address bus with a direct mapped cache, using $4$ bits for block offset, $16$ tag bits, and $12$ index bits.Which of the following address pairs...
GO Classes
772
views
GO Classes
asked
Jan 21
CO and Architecture
goclasses2024-mockgate-12
goclasses
co-and-architecture
cache-memory
multiple-selects
2-marks
+
–
0
votes
1
answer
28
computer architecture
a computer has 32-bit instructions and 12-bit addressing if there are already 250 two address instruction how many one address instruction can be formulated
a computer has 32-bit instructions and 12-bit addressing if there are already 250 two address instruction how many one address instruction can be formulated
junior hacker
151
views
junior hacker
asked
Jan 15
CO and Architecture
co-and-architecture
+
–
0
votes
0
answers
29
Made easy
In it’s solution how are they obtaining x with the given operation? Should we not have 1 more register to keep x separate?
In it’s solution how are they obtaining x with the given operation? Should we not have 1 more register to keep x separate?
Mrityudoot
127
views
Mrityudoot
asked
Jan 14
CO and Architecture
made-easy-test-series
test-series
co-and-architecture
+
–
3
votes
1
answer
30
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 14
Which kind of data dependence can cause data hazards in a single-core, pipelined, in-order processor? (Mark all that apply.) read-after-write dependence write-after-read dependence write-after-write dependence read-after-read dependence
Which kind of data dependence can cause data hazards in a single-core, pipelined, in-order processor? (Mark all that apply.)read-after-write dependencewrite-after-read de...
GO Classes
555
views
GO Classes
asked
Jan 13
CO and Architecture
goclasses2024-mockgate-11
goclasses
co-and-architecture
pipelining
multiple-selects
1-mark
+
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