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MadeEasy Subject Test: CO & Architecture - Conflict Misses
A computer system contains a main memory of 32 K size with 16-bit words. It also has a 4 K word cache divided into 4 slot sets with 64 words per slot. Assume that the cache is initially empty. The processor fetches ... ...4351 in that order repeatedly 10 times. Assume a LRU policy for block replacement. How many miss operations will occur?

asked Sep 14, 2017 in CO and Architecture by Chandramani Adil (145 points) | 132 views

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GATE2017-1-51
Consider a $2-$way set associative cache with $256$ blocks and uses $LRU$ replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first ... $10$ times. The number of conflict misses experienced by the cache is _________ .

asked Feb 14, 2017 in CO and Architecture by Arjun Veteran (418k points) | 11.3k views

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