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Recent questions tagged control
1
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answers
1
Control Dependencies
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Lakshmi kittur
708
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Lakshmi kittur
asked
Nov 14, 2018
CO and Architecture
co-and-architecture
pipelining
control
dependencies
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–
0
votes
1
answer
2
Control dependencies
Consider a pipelined processor having 5 stages. The stage delays are 2, 3, 2.5, 3.2, 2.5ns and interstage buffer delays are 1ns. The 3rd stage is capable of deciding branch target address. Processor starts fetching new instruction when the conditional branch outcome is known. 20% of instructions are conditional branch, then calculate the execution time for 1000 instructions?
Consider a pipelined processor having 5 stages. The stage delays are 2, 3, 2.5, 3.2, 2.5ns and interstage buffer delays are 1ns. The 3rd stage is capable of deciding bran...
Lakshmi kittur
1.5k
views
Lakshmi kittur
asked
Nov 14, 2018
CO and Architecture
control
dependencies
pipelining
co-and-architecture
+
–
0
votes
0
answers
3
test-series
If k-bit maximum frame sequence numbers is available. What is the maximum window size for data transmission using the selective repeat protocol and Go Back N protocol ?
If k-bit maximum frame sequence numbers is available. What is the maximum window size for data transmission using the selective repeat protocol and Go Back N protocol ?
Rudra Pratap
557
views
Rudra Pratap
asked
Dec 5, 2017
Computer Networks
flow
control
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–
0
votes
1
answer
4
Computer Network
Is there any difference between Maximum no of bits and Maximum number of sequence? or they are both same?
Is there any difference between Maximum no of bits and Maximum number of sequence? or they are both same?
vishwa ratna
209
views
vishwa ratna
asked
Jan 17, 2017
Computer Networks
flow
control
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