Recent questions tagged control-unit / GATE Overflow for GATE CSE

2 votes

2 answers

31

Micro Instruction
Conditional bit(Flag) Micro-opn. Next Address Micro-Instruction Format If a micro program supports 46μ operations with a parallelism of 2,how many and what size of field exists in micro operation field? Given size of micro-opn field is 9bits. Answer: Total 9 bis divided in 4 and 5 bit. Can anyone explain how this division is being done.

Conditional bit(Flag)Micro-opn.Next Address Micro-Instruction FormatIf a micro program supports 46μ operations with a parallel...

Sourajit25

2.4k views

Sourajit25 asked Nov 24, 2017

1 votes

0 answers

32

general doubt
Can someone refer a good resource to study about bus architecture? I think a few questions ask you to calculate minimum cpu cycles where u need to know some details about bus. i read the bus architecture part from carl hamacher. Also watched nptel ... we assume single system bus or should we consider system bus and separate internal bus. Please provide some resources on this topic.

Can someone refer a good resource to study about bus architecture?I think a few questions ask you to calculate minimum cpu cycles where u need to know some details about...

Tridhara Chakrabarti

264 views

Tridhara Chakrabarti asked Nov 20, 2017

7 votes

1 answer

33

vertical microprogrammed
A vertical microprogrammed control unit supports 256 instructions. The system is using 8 flag conditions and contains 48 control signals. Each instruction on average requires 1 micro operation. What is the approximate size of control memory in bytes?

A vertical microprogrammed control unit supports 256 instructions. The system is using 8 flag conditions and contains 48 control signals. Each instruction on average requ...

Supremo

6.1k views

Supremo asked Jan 28, 2017

2 votes

0 answers

34

Control Unit
How many clock cycle are needed in index addressing for getting memory content and effective address?

How many clock cycle are needed in index addressing for getting memory content and effective address?

Wanted

583 views

Wanted asked Jan 6, 2017

8 votes

2 answers

35

GATE CSE 1987 | Question: 1-vi
A microprogrammed control unit Is faster than a hard-wired control unit. Facilitates easy implementation of new instruction. Is useful when very small programs are to be run. Usually refers to the control unit of a microprocessor.

A microprogrammed control unitIs faster than a hard-wired control unit.Facilitates easy implementation of new instruction.Is useful when very small programs are to be run...

makhdoom ghaya

7.4k views

makhdoom ghaya asked Nov 8, 2016

0 votes

1 answer

36

Memory-Control Unit
If size of MAR &MBR are $32$ bit and $16$ bit respectively then what is the main memory size. if memory is byte addressable .

If size of MAR &MBR are $32$ bit and $16$ bit respectively then what is the main memory size.if memory is byte addressable .

saurabh rai

2.2k views

saurabh rai asked Sep 5, 2016

0 votes

0 answers

37

Hardware Operation Chart of one digital system, anyone can help?
I try to figure out one of the tests that adopted from GATE exams, but nothing founds, anyone can describe it for me? Question: We shown the Hardware Operation Chart of one digital system in the following figure: activity of control signals for each operational ... unit how many and, or gate is needed? A) 4, 5 B) 4, 4 C) 5,3 D)4, 3

I try to figure out one of the tests that adopted from GATE exams, but nothing founds, anyone can describe it for me?Question: We shown the Hardware Operation Chart of on...

Sara Nimlon

873 views

Sara Nimlon asked Jun 30, 2016

6 votes

1 answer

38

Jump instruction
Question Part- I If the program below, the number of times the FIRST and SECOND JNZ instruction cause the control to be transferred to LOOP respectively MVI H,02H MVI L,05H LOOP : DCR L FIRST : JNZ LOOP DCR H SECOND : JNZ LOOP A. 5 and 2 B. 21 and ... the FIRST and SECOND JNZ instruction cause the control to be transferred to LOOP respectively 5 and 2 260 and 1 259 and 1 6 and 1

QuestionPart- IIf the program below, the number of times the FIRST and SECOND JNZ instruction cause the control to be transferred to LOOP respectivelyMVI H,02HMVI L,05HLO...

navi

5.2k views

navi asked Jun 17, 2016

0 votes

3 answers

39

Surprised Nano Memory (VERTICAL Micro Instruction) Reduced bits?!
Hi to all, This is an Challenging Interview Question that I see lots of this example in GATE Exams. In a digital system with micro-programmed control circuit, We have 32 Control Signal and total distinct pattern is 450. if the micro-programmed ... to 23kbits but the solution is (a). (i.e 22K bits). any EXPERT can say why 22K is true?

Hi to all, This is an Challenging Interview Question that I see lots of this example in GATE Exams. In a digital system with micro-programmed control circuit, We have 32...

asambeladi

2.7k views

asambeladi asked Jun 16, 2016

4 votes

2 answers

40

ISRO2009-34
The microinstructions stored in the control memory of a processor have a width of $26$ bits. Each microinstruction is divided into three fields. a micro operation field of $13$ bits, a next address field $\text{(X)},$ and a MUX select field $\text{(Y)}.$ There are $8$ status bits ... the size of the control memory in number of words? $10, 3, 1024$ $8, 5, 256$ $5, 8, 2048$ $10, 3, 512$

The microinstructions stored in the control memory of a processor have a width of $26$ bits. Each microinstruction is divided into three fields. a micro operation field o...

Desert_Warrior

2.8k views

Desert_Warrior asked Jun 3, 2016

1 votes

1 answer

41

Vertical Instruction in Control MEmory?
In a digital system we have 120 control signals.In Operating Chart of this system (ASM Chart) we have 8 distinct condition. with inspecting the activity of micro operation shows we have reduced control memory bits with vertical micro instruction (nano memory ... *120 3- in size of micro memory we can saved 2^10*110 Who can help in this previous exam question.

In a digital system we have 120 control signals.In Operating Chart of this system (ASM Chart) we have 8 distinct condition. with inspecting the activity of micro operatio...

DrMhmd

1.6k views

DrMhmd asked May 13, 2016

0 votes

0 answers

42

GATE CSE 1991 | Question: 07b
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. Assume ... bits of an instruction constitute the operand field. Draw the logic schematic of the hardwired controller including the data path.

It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed ...

go_editor

814 views

go_editor asked Apr 24, 2016

2 votes

0 answers

43

GATE CSE 1991 | Question: 07a
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. ... bits of an instruction constitute the operand field. Give the register transfer sequence for realizing the above instruction fetch cycle.

It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed ...

Kathleen

698 views

Kathleen asked Sep 12, 2014

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