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Recent questions tagged cycle
0
votes
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NIELIT 2017 DEC Scientist B - Section B: 23
Let $G$ be a complete undirected graph on $8$ vertices. If vertices of $G$ are labelled, then the number of distinct cycles of length $5$ in $G$ is equal to: $15$ $30$ $56$ $60$
Let $G$ be a complete undirected graph on $8$ vertices. If vertices of $G$ are labelled, then the number of distinct cycles of length $5$ in $G$ is equal to:$15$$30$$56$$...
admin
2.4k
views
admin
asked
Mar 30, 2020
Graph Theory
nielit2017dec-scientistb
discrete-mathematics
graph-theory
cycle
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–
2
votes
0
answers
2
DMA Doubt
can someone explain what is preparation time in DMA exactly? and why is it multiplied by CPU cycle time in most of the questions here? does preparation time means that a word is brought into disk controller buffer from hard disk and it utilizes CPU? PS-DMA is giving me headaches!!!
can someone explain what is preparation time in DMA exactly?and why is it multiplied by CPU cycle time in most of the questions here?does preparation time means that a wo...
aditi19
606
views
aditi19
asked
Dec 8, 2018
CO and Architecture
dma
co-and-architecture
cycle
burst-mode
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–
0
votes
1
answer
3
Clock per instruction
What is the difference between Effective CPI and Average CPI ? A program is run on 40 MHZ with instruction mix and corresponding clock cycle count. Determine : * Effective CPI * Average CPI Instruction Clock Cycle Instruction Count Arithmetic 1 45000 Floating Point 2 32000 Data Transfer 2 15000 Control Transfer 2 8000
What is the difference between Effective CPI and Average CPI ?A program is run on 40 MHZ with instruction mix and corresponding clock cycle count.Determine : * Effecti...
Na462
1.4k
views
Na462
asked
Oct 12, 2018
CO and Architecture
co-and-architecture
stall
cycle
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0
votes
0
answers
4
Memory cycles
Na462
495
views
Na462
asked
Sep 24, 2018
CO and Architecture
co-and-architecture
cycle
numerical-answers
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–
1
votes
0
answers
5
Test Series
Choose the correct option, from the following: I) We can find the cycle in the graph using BFS. II) We can find the cycle in the graph using DFS. III)Both Correct IV)Both wrong
Choose the correct option, from the following:I) We can find the cycle in the graph using BFS.II) We can find the cycle in the graph using DFS.III)Both CorrectIV)Both wro...
ankit_thawal
413
views
ankit_thawal
asked
Jan 10, 2018
Programming in C
depth-first-search
cycle
+
–
8
votes
4
answers
6
Avg stall cycles per instruction
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache to memory is $100$ cycles. The hit time of $L_{2}$ cache is $20$ ... $L_{1}$ cache is $10$ cycles. If there are $2.5$ memory references per instruction. How many average stall cycle per instruction?
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache t...
Parshu gate
4.7k
views
Parshu gate
asked
Dec 25, 2017
CO and Architecture
co-and-architecture
stall
cache-memory
cycle
+
–
3
votes
1
answer
7
Number of Memory Access in Fetch and Execute State in Instruction Cycles
Consider a 32 bit hypothetical processor used to execute the following programme segement INST // MEANING // SIZE(IN WORDS) MOV R0, @3000 // R0 <- M[[3000]] // 2 MOV R1, [2000] // R1 ... executinion time of the program? Determine the number of memory referneces required in Instruction Fetch Phase and Execution Phase state.
Consider a 32 bit hypothetical processor used to execute the following programme segement INST // MEANING // SIZE(IN WORDS)MOV R0, @3000 // R0 <- M[[3000]] // 2MOV R1,...
Shubhanshu
2.2k
views
Shubhanshu
asked
Sep 4, 2017
CO and Architecture
co-and-architecture
cycle
+
–
3
votes
2
answers
8
How many maximum cycles possible in any Complete graph? (Unlabelled nodes)
smartmeet
1.8k
views
smartmeet
asked
Jan 14, 2017
Graph Theory
graph-theory
cycle
+
–
5
votes
3
answers
9
CO Cache stall cycles
Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory is 100 cycles.The hit time of L2 cache is 20 cycle.The hit time of the L1 cache is 10 cycles. If there are 2.5 memory references per instruction.How many average stall cycles per instructions are there?
Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory...
Prajwal Bhat
3.9k
views
Prajwal Bhat
asked
Jan 7, 2017
CO and Architecture
co-and-architecture
stall
cycle
cache-memory
+
–
1
votes
1
answer
10
Stall Cycles-Without Forwarding
anyone elaborate the reason for each stall cycles.
anyone elaborate the reason for each stall cycles.
Shashank Chandekar
2.0k
views
Shashank Chandekar
asked
Oct 26, 2016
CO and Architecture
stall
cycle
+
–
1
votes
1
answer
11
Graphs
Rahul Jain25
372
views
Rahul Jain25
asked
Oct 10, 2016
Graph Theory
graph-theory
cycle
euler-graph
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–
3
votes
1
answer
12
DMA CONTROLLER CYCLE STEALING
Please explain DMA cycle stealing mode with a timeline diagram. Does the DMA wait for 1 byte before aquiring the bus control and is this the same time when CPU utilizes the bus for it's own purpose ?
Please explain DMA cycle stealing mode with a timeline diagram.Does the DMA wait for 1 byte before aquiring the bus control and is this the same time when CPU utilizes th...
Ashish Singh 3
1.1k
views
Ashish Singh 3
asked
Sep 1, 2016
CO and Architecture
co-and-architecture
dma
cycle
stealing
+
–
11
votes
3
answers
13
Cycle Stealing(DMA)
In Cycle Stealing, does the DMA interrupt the processor everytime, or it uses the cycle while the processor remains unknown of the fact?
In Cycle Stealing, does the DMA interrupt the processor everytime, or it uses the cycle while the processor remains unknown of the fact?
prasitamukherjee
17.6k
views
prasitamukherjee
asked
Aug 9, 2016
CO and Architecture
co-and-architecture
dma
cycle
+
–
0
votes
0
answers
14
DAM cycle stealing
How cycle stealing maximize i/o rate
How cycle stealing maximize i/o rate
Pradip Nichite
452
views
Pradip Nichite
asked
Jan 22, 2016
CO and Architecture
co-and-architecture
dma
cycle
+
–
1
votes
0
answers
15
DMA
https://gateoverflow.in/3547/gate2006-it_8 Arjun Sir plz anwser it.
https://gateoverflow.in/3547/gate2006-it_8Arjun Sir plz anwser it.
sonu
775
views
sonu
asked
Oct 16, 2015
CO and Architecture
cycle
stealing
+
–
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