Recent questions tagged data-path / GATE Overflow for GATE CSE

1 votes

1 answer

1

NIELIT 2016 DEC Scientist B (IT) - Section B: 47
The ________ is the physical path over which a message travels. Path Protocol Route Medium

The ________ is the physical path over which a message travels.PathProtocolRouteMedium

admin

941 views

admin asked Mar 31, 2020

15 votes

4 answers

2

GATE CSE 2020 | Question: 4
Consider the following data path diagram. Consider an instruction: $R0 \leftarrow R1 +R2$. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts $r$ and $w$ ... of the above steps? $2,1,4,5,3$ $1,2,4,3,5$ $3,5,2,1,4$ $3,5,1,2,4$

Consider the following data path diagram. Consider an instruction: $R0 \leftarrow R1 +R2$. The following steps are used to execute it over the given data...

Arjun

8.6k views

Arjun asked Feb 12, 2020

0 votes

0 answers

3

Doubt on Data Path
In Single bus Architecture for a simple add operation ,we know there are 8 cycles required, where 1st three for Fetch cycle and Others are for execution cycle Steps Action 1. $PC_{out},MAR_{in},Read, Clear-Y,Set Carry Into ALU,Add,Z_{in}$ 2. ... T? 3) Question is only asking clock cycles for execution cycle. Then why we are considering Fetch and Execution cycles in our answer?

In Single bus Architecture for a simple add operation ,we know there are 8 cycles required, where 1st three for Fetch cycle and Others are for execution cycleStepsAction1...

srestha

529 views

srestha asked Sep 13, 2018

0 votes

1 answer

4

virtual gate

Manoja Rajalakshmi A

344 views

Manoja Rajalakshmi A asked Nov 9, 2017

1 votes

0 answers

5

GATE CSE 1988 | Question: 4i
An $8$-bit data path is to be set up using two $4$-bit ALU's and suitable multiplexers. The ALU's accept two operands $A$ and $B$ on which a total of $16$ operations can be performed. The operand $A$ is from one of two ... a bus. List the data path control signals, and estimate the minimum width of a signal microcode word needed for the generation of these signals.

An $8$-bit data path is to be set up using two $4$-bit ALU’s and suitable multiplexers. The ALU’s accept two operands $A$ and $B$ on which a total of $16$ operations ...

go_editor

536 views

go_editor asked Dec 19, 2016

10 votes

1 answer

6

GATE CSE 1990 | Question: 8a
A single bus CPU consists of four general purpose register, namely, $R0, \ldots, R3, \text{ALU}, \text{MAR}, \text{MDR}, \text{PC}, \text{SP}$ and $\text{IR}$ (Instruction Register). Assuming suitable microinstructions, write a microroutine for the instruction, $\text{ADD }R0, R1$.

A single bus CPU consists of four general purpose register, namely, $R0, \ldots, R3, \text{ALU}, \text{MAR}, \text{MDR}, \text{PC}, \text{SP}$ and $\text{IR}$ (Instructio...

makhdoom ghaya

2.0k views

makhdoom ghaya asked Nov 24, 2016

55 votes

12 answers

7

GATE CSE 2005 | Question: 80
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in ... $2$ $3$ $4$ $5$

Consider the following data path of a $\text{CPU}.$The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including increm...

go_editor

24.2k views

go_editor asked Apr 24, 2016

99 votes

12 answers

8

GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement ... $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.

Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two...

Akash Kanase

22.6k views

Akash Kanase asked Feb 12, 2016

4 votes

1 answer

9

The ALU, the bus and all the register are identical in size. the instruction "memory write"
The ALU, the bus and all the register are identical in size. The instruction "memory write" has the register transfer interpretation M[(R1)] ← R2. The minimum number of clock cycles needed for execution cycle of this instruction if memory write completion takes 1 cycle is a) 2 b)3 c)4 d)5

The ALU, the bus and all the register are identical in size. The instruction "memory write" has the register transfer interpretation M[(R1)] ← R2. The minimum number...

yes

877 views

yes asked Nov 20, 2015

47 votes

6 answers

10

GATE CSE 2005 | Question: 79
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the ... $2$ $3$ $4$ $5$

Consider the following data path of a $\text{CPU}.$The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including increm...

Kathleen

24.4k views

Kathleen asked Sep 22, 2014

54 votes

11 answers

11

GATE CSE 2001 | Question: 2.13
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$ wide. $\textsf{SP}$ and $\textsf{MAR}$ are $16$-$bit$ registers. The ... $\textsf{CPU}$ clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$

Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$...

Kathleen

21.2k views

Kathleen asked Sep 14, 2014

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