Recent questions tagged data-path - GATE Overflow

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Doubt on Data Path
In Single bus Architecture for a simple add operation ,we know there are 8 cycles required, where 1st three for Fetch cycle and Others are for execution cycle Steps Action 1. $PC_{out},MAR_{in},Read, Clear-Y,Set Carry Into ALU,Add,Z_{in}$ 2. ... T? 3) Question is only asking clock cycles for execution cycle. Then why we are considering Fetch and Execution cycles in our answer?

asked Sep 13, 2018 in CO and Architecture by srestha Veteran (117k points) | 49 views

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1 answer

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asked Nov 9, 2017 in CO and Architecture by Manoja Rajalakshmi A Boss (11.5k points) | 58 views

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0 answers

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GATE1988-4i
An $8-bit$ data path is to be set up using two $4-bit$ ALU's and suitable multiplexers. The ALU's accept two operands $A$ and $B$ on which a total of $16$ operations can be performed. The operand $A$ is from one of two register-arrays ... on a bus. List the data path control signals, and estimate the minimum width of a signal microcode word needed for the generation of these signals.

asked Dec 19, 2016 in CO and Architecture by jothee Veteran (105k points) | 110 views

+28 votes

10 answers

4

GATE2005-80
The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in ... $2$ $3$ $4$ $5$

asked Apr 24, 2016 in CO and Architecture by jothee Veteran (105k points) | 6.2k views

+61 votes

10 answers

5

GATE2016-2-30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement the computation $F(G(X_{i}))$ for $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.

asked Feb 12, 2016 in CO and Architecture by Akash Kanase Boss (41.6k points) | 7.7k views

+4 votes

1 answer

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The ALU, the bus and all the register are identical in size. the instruction "memory write"

asked Nov 20, 2015 in CO and Architecture by yes Active (1.2k points) | 381 views

+25 votes

6 answers

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GATE2005-79
Consider the following data path of a CPU. The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation ... = R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is: $2$ $3$ $4$ $5$

asked Sep 22, 2014 in CO and Architecture by Kathleen Veteran (52.2k points) | 7.1k views

+30 votes

7 answers

8

GATE2001-2.13
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1}$, $A_{2}$, MDR, the bus and the ALU are $8$-$bit$ wide. SP and MAR are $16$-$bit$ registers. The MUX is of size $8 \times (2:1)$ ... $SP ← SP - 1$ How many CPU clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$

asked Sep 15, 2014 in CO and Architecture by Kathleen Veteran (52.2k points) | 5.7k views

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