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Recent questions tagged data-path

3 votes
6 answers
1
Consider the following data path diagram. Consider an instruction: $R0 \leftarrow R1 +R2$. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts $r$ and $w$ ... of execution of the above steps? $2,1,4,5,3$ $1,2,4,3,5$ $3,5,2,1,4$ $3,5,1,2,4$
asked Feb 12 in CO and Architecture Arjun 1.5k views
0 votes
0 answers
2
In Single bus Architecture for a simple add operation ,we know there are 8 cycles required, where 1st three for Fetch cycle and Others are for execution cycle Steps Action 1. $PC_{out},MAR_{in},Read, Clear-Y,Set Carry Into ALU,Add,Z_{in}$ ... instruction for T? 3) Question is only asking clock cycles for execution cycle. Then why we are considering Fetch and Execution cycles in our answer?
asked Sep 13, 2018 in CO and Architecture srestha 151 views
0 votes
1 answer
3
0 votes
0 answers
4
An $8-bit$ data path is to be set up using two $4-bit$ ALU's and suitable multiplexers. The ALU's accept two operands $A$ and $B$ on which a total of $16$ operations can be performed. The operand $A$ is from one of two register-arrays each ... placed on a bus. List the data path control signals, and estimate the minimum width of a signal microcode word needed for the generation of these signals.
asked Dec 19, 2016 in CO and Architecture jothee 152 views
35 votes
11 answers
5
The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR ... $2$ $3$ $4$ $5$
asked Apr 24, 2016 in CO and Architecture jothee 9.1k views
74 votes
10 answers
6
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement the computation $F(G(X_{i}))$ for $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.
asked Feb 12, 2016 in CO and Architecture Akash Kanase 9.9k views
4 votes
1 answer
7
The ALU, the bus and all the register are identical in size. The instruction "memory write" has the register transfer interpretation M[(R1)] ← R2. The minimum number of clock cycles needed for execution cycle of this instruction if memory write completion takes 1 cycle is a) 2 b)3 c)4 d)5
asked Nov 20, 2015 in CO and Architecture yes 432 views
31 votes
6 answers
8
Consider the following data path of a CPU. The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the ... <= R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is: $2$ $3$ $4$ $5$
asked Sep 22, 2014 in CO and Architecture Kathleen 9.1k views
36 votes
9 answers
9
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1}$, $A_{2}$, MDR, the bus and the ALU are $8$-$bit$ wide. SP and MAR are $16$-$bit$ registers. The MUX is of size $8 \times (2:1)$ ... specification $M[SP] ← r $ $SP ← SP - 1$ How many CPU clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$
asked Sep 15, 2014 in CO and Architecture Kathleen 8.2k views
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