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Recent questions tagged data-path
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Doubt on Data Path
In Single bus Architecture for a simple add operation ,we know there are 8 cycles required, where 1st three for Fetch cycle and Others are for execution cycle Steps Action 1. $PC_{out},MAR_{in},Read, Clear-Y,Set Carry Into ALU,Add,Z_{in}$ 2. ... T? 3) Question is only asking clock cycles for execution cycle. Then why we are considering Fetch and Execution cycles in our answer?
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Sep 13, 2018
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CO and Architecture
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srestha
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data-path
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answer
2
virtual gate
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Nov 9, 2017
in
CO and Architecture
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Manoja Rajalakshmi A
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data-path
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3
GATE1988-4i
An $8-bit$ data path is to be set up using two $4-bit$ ALU's and suitable multiplexers. The ALU's accept two operands $A$ and $B$ on which a total of $16$ operations can be performed. The operand $A$ is from one of two register-arrays ... on a bus. List the data path control signals, and estimate the minimum width of a signal microcode word needed for the generation of these signals.
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Dec 19, 2016
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CO and Architecture
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jothee
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gate1988
descriptive
co-and-architecture
data-path
unsolved
+28
votes
10
answers
4
GATE2005-80
The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in ... $2$ $3$ $4$ $5$
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Apr 24, 2016
in
CO and Architecture
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jothee
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co-and-architecture
normal
gate2005
data-path
machine-instructions
+61
votes
10
answers
5
GATE2016-2-30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement the computation $F(G(X_{i}))$ for $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.
asked
Feb 12, 2016
in
CO and Architecture
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Akash Kanase
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41.6k
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gate2016-2
co-and-architecture
data-path
normal
numerical-answers
+4
votes
1
answer
6
The ALU, the bus and all the register are identical in size. the instruction "memory write"
asked
Nov 20, 2015
in
CO and Architecture
by
yes
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1.2k
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381
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co-and-architecture
data-path
+25
votes
6
answers
7
GATE2005-79
Consider the following data path of a CPU. The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation ... = R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is: $2$ $3$ $4$ $5$
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Sep 22, 2014
in
CO and Architecture
by
Kathleen
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7.1k
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gate2005
co-and-architecture
machine-instructions
data-path
normal
+30
votes
7
answers
8
GATE2001-2.13
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1}$, $A_{2}$, MDR, the bus and the ALU are $8$-$bit$ wide. SP and MAR are $16$-$bit$ registers. The MUX is of size $8 \times (2:1)$ ... $SP ← SP - 1$ How many CPU clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$
asked
Sep 15, 2014
in
CO and Architecture
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Kathleen
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52.2k
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gate2001
co-and-architecture
data-path
machine-instructions
normal
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Not really. It was excluding shipping I guess....
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