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Recent questions tagged data-path

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NIELIT 2016 DEC Scientist B (IT) - Section B: 47
The ________ is the physical path over which a message travels. Path Protocol Route Medium

Lakshman Patel RJIT asked in Computer Networks Mar 31, 2020

by Lakshman Patel RJIT

687 views

8 votes

4 answers

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GATE CSE 2020 | Question: 4
Consider the following data path diagram. Consider an instruction: $R0 \leftarrow R1 +R2$. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts $r$ and $w$ ... of the above steps? $2,1,4,5,3$ $1,2,4,3,5$ $3,5,2,1,4$ $3,5,1,2,4$

Arjun asked in CO and Architecture Feb 12, 2020

by Arjun

5.9k views

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0 answers

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Doubt on Data Path
In Single bus Architecture for a simple add operation ,we know there are 8 cycles required, where 1st three for Fetch cycle and Others are for execution cycle Steps Action 1. $PC_{out},MAR_{in},Read, Clear-Y,Set Carry Into ALU,Add,Z_{in}$ 2. ... T? 3) Question is only asking clock cycles for execution cycle. Then why we are considering Fetch and Execution cycles in our answer?

srestha asked in CO and Architecture Sep 13, 2018

403 views

0 votes

1 answer

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Manoja Rajalakshmi A asked in CO and Architecture Nov 9, 2017

by Manoja Rajalakshmi A

210 views

1 vote

0 answers

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GATE CSE 1988 | Question: 4i
An $8$-bit data path is to be set up using two $4$-bit ALU's and suitable multiplexers. The ALU's accept two operands $A$ and $B$ on which a total of $16$ operations can be performed. The operand $A$ is from one of two ... a bus. List the data path control signals, and estimate the minimum width of a signal microcode word needed for the generation of these signals.

go_editor asked in CO and Architecture Dec 19, 2016

384 views

7 votes

1 answer

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GATE CSE 1990 | Question: 8a
A single bus CPU consists of four general purpose register, namely, $R0, \ldots, R3, \text{ALU}, \text{MAR}, \text{MDR}, \text{PC}, \text{SP}$ and $\text{IR}$ (Instruction Register). Assuming suitable microinstructions, write a microroutine for the instruction, $\text{ADD }R0, R1$.

makhdoom ghaya asked in CO and Architecture Nov 24, 2016

by makhdoom ghaya

1.4k views

50 votes

12 answers

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GATE CSE 2005 | Question: 80
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in ... $2$ $3$ $4$ $5$

go_editor asked in CO and Architecture Apr 24, 2016

19.9k views

94 votes

11 answers

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GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement ... $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.

Akash Kanase asked in CO and Architecture Feb 12, 2016

by Akash Kanase

17.7k views

4 votes

1 answer

9

The ALU, the bus and all the register are identical in size. the instruction "memory write"
The ALU, the bus and all the register are identical in size. The instruction "memory write" has the register transfer interpretation M[(R1)] ← R2. The minimum number of clock cycles needed for execution cycle of this instruction if memory write completion takes 1 cycle is a) 2 b)3 c)4 d)5

yes asked in CO and Architecture Nov 20, 2015

by yes

646 views

42 votes

6 answers

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GATE CSE 2005 | Question: 79
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the ... $2$ $3$ $4$ $5$

Kathleen asked in CO and Architecture Sep 22, 2014

19.7k views

48 votes

10 answers

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GATE CSE 2001 | Question: 2.13
Consider the following data path of a simple non-pipelined CPU. The registers $A, B$, $A_{1},A_{2}, \textsf{MDR},$ the $\textsf{bus}$ and the $\textsf{ALU}$ are $8$-$bit$ wide. $\textsf{SP}$ and $\textsf{MAR}$ are $16$-$bit$ registers. The ... $\textsf{CPU}$ clock cycles are required to execute the "push r" instruction? $2$ $3$ $4$ $5$

Kathleen asked in CO and Architecture Sep 15, 2014

16.9k views

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