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Recent questions tagged descriptive
19
votes
3
answers
2701
GATE CSE 1991 | Question: 10a
Consider the following grammar for arithmetic expressions using binary operators $-$ and $/$ which are not associative $E \rightarrow E -T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) Is the grammar ... what is the relative precedence between $-$ and $/$? If not, give an unambiguous grammar that gives $/$ precedence over $-$.
Consider the following grammar for arithmetic expressions using binary operators $-$ and $/$ which are not associative$E \rightarrow E -T\mid T$$T \rightarrow T/F\mid F$ ...
Kathleen
4.4k
views
Kathleen
asked
Sep 12, 2014
Compiler Design
gate1991
grammar
compiler-design
normal
descriptive
+
–
27
votes
3
answers
2702
GATE CSE 1991 | Question: 09a
Consider the following pseudo-code (all data items are of type integer): procedure P(a, b, c); a := 2; c := a + b; end {P} begin x := 1; y := 5; z := 100; P(x, x*y, z); Write ('x = ', x, 'z = ', z); end Determine its output, if the parameters are passed to the Procedure $\text{P}$ by value reference name
Consider the following pseudo-code (all data items are of type integer): procedure P(a, b, c); a := 2; c := a + b; end {P} begin x := 1; y := 5; z := 100; P(x, x*y, z); W...
Kathleen
3.5k
views
Kathleen
asked
Sep 12, 2014
Compiler Design
gate1991
compiler-design
parameter-passing
normal
runtime-environment
descriptive
+
–
2
votes
0
answers
2703
GATE CSE 1991 | Question: 07a
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. ... bits of an instruction constitute the operand field. Give the register transfer sequence for realizing the above instruction fetch cycle.
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed ...
Kathleen
683
views
Kathleen
asked
Sep 12, 2014
CO and Architecture
gate1991
co-and-architecture
control-unit
hardwired-controller
normal
unsolved
descriptive
+
–
6
votes
2
answers
2704
GATE CSE 1991 | Question: 06,a
Using $\text{D}$ flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines: Clock $\text{CLK}$ Three parallel data inputs $A, B, C$ Serial input $S$ Control input $\text{LOAD} / \overline{\text{SHIFT}}$.
Using $\text{D}$ flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines:Clock $\text{CLK}$Thre...
Kathleen
1.5k
views
Kathleen
asked
Sep 12, 2014
Digital Logic
gate1991
digital-logic
difficult
sequential-circuit
flip-flop
shift-registers
descriptive
+
–
27
votes
1
answer
2705
GATE CSE 1991 | Question: 5-a
Analyse the circuit in Fig below and complete the following table ${\begin{array}{|c|c|c|}\hline \textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline 0&0\\\ 0&1 \\ 1&0 \\ 1&1 \\ \hline \end{array}}$
Analyse the circuit in Fig below and complete the following table$${\begin{array}{|c|c|c|}\hline\textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline0&0\\\ 0&1 \\ 1&0 \\ 1...
Kathleen
3.8k
views
Kathleen
asked
Sep 12, 2014
Digital Logic
gate1991
digital-logic
normal
circuit-output
sequential-circuit
descriptive
+
–
20
votes
5
answers
2706
GATE CSE 1991 | Question: 1,ix
If the binary tree in figure is traversed in inorder, then the order in which the nodes will be visited is ______
If the binary tree in figure is traversed in inorder, then the order in which the nodes will be visited is ______
Kathleen
5.4k
views
Kathleen
asked
Sep 12, 2014
DS
gate1991
binary-tree
easy
data-structures
descriptive
+
–
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