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Recent questions tagged digital-circuits

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1
UGCNET-Jan2017-II: 7
ECL is the fastest of all logic families. High speed in ECL is possible because transistors are used in difference amplifier configuration, in which they are never driven into ________. Race condition Saturation Delay High impedance
ECL is the fastest of all logic families. High speed in ECL is possible because transistors are used in difference amplifier configuration, in which they are never driven into ________. Race condition Saturation Delay High impedance
asked Mar 24 in Digital Logic jothee 60 views
3 votes
2 answers
2
ISRO2020-66
The following circuit compares two $2$-bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bits) Under what conditions $Z$ will be $1$? $X>Y$ $X<Y$ $X=Y$ $X!=Y$
The following circuit compares two $2$-bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bits) Under what conditions $Z$ will be $1$? $X>Y$ $X<Y$ $X=Y$ $X!=Y$
asked Jan 13 in Digital Logic Satbir 596 views
2 votes
2 answers
3
Logic Gates and switching circuits
The gates G1 & G2 in the figure have propagation delays of 10ns and 20ns respectively. If the input Vi makes an abrupt change from logic 0 to 1 at time t=t0 , then what's the output waveform V0 is ? Also please explain how to handle such kinds of questions of waveform? ​​​​
The gates G1 & G2 in the figure have propagation delays of 10ns and 20ns respectively. If the input Vi makes an abrupt change from logic 0 to 1 at time t=t0 , then what's the output waveform V0 is ? Also please explain how to handle such kinds of questions of waveform? ​​​​
asked Jun 14, 2019 in Digital Logic Gitika Babbar 626 views
0 votes
0 answers
5
Morris Mano Edition 3 Exercise 9 Question 2 (Page No. 392)
Derive a transition table for the asynchronous sequential circuit given in the figure. Determine the sequence of the internal states $y _1Y _2$ for the following sequence of the input $x _1x _2$: 00,10,11,01,11,10,00. ​
Derive a transition table for the asynchronous sequential circuit given in the figure. Determine the sequence of the internal states $y _1Y _2$ for the following sequence of the input $x _1x _2$: 00,10,11,01,11,10,00. ​
asked Apr 7, 2019 in Digital Logic ajaysoni1924 50 views
0 votes
0 answers
7
Morris Mano Edition 3 Exercise 5 Question 4 (Page No. 197)
The adder-subtractor circuit of figure has the following values for mode input M and data inputs A and B. In each case, determine the values of the outputs: $S _ 4 S _3 S _2 S _1$ and $C _5$. M A B 0 0111 0110 0 1000 1001 1 0101 1000 1 0000 1010
The adder-subtractor circuit of figure has the following values for mode input M and data inputs A and B. In each case, determine the values of the outputs: $S _ 4 S _3 S _2 S _1$ and $C _5$. M A B 0 0111 0110 0 1000 1001 1 0101 1000 1 0000 1010
asked Apr 3, 2019 in Digital Logic ajaysoni1924 372 views
0 votes
0 answers
8
Morris Mano Edition 3 Exercise 5 Question 3 (Page No. 197)
The adder-subtractor of the figure is used to subtract the following unsigned 4-bit number: 0110 – 1001(6 – 9) What are the binary values in the nine inputs of the circuit $?$ what are the binary values of the five outputs of the circuit$?$ Explain How the output is related to the operation of 6 – 9.
The adder-subtractor of the figure is used to subtract the following unsigned 4-bit number: 0110 – 1001(6 – 9) What are the binary values in the nine inputs of the circuit $?$ what are the binary values of the five outputs of the circuit$?$ Explain How the output is related to the operation of 6 – 9.
asked Apr 3, 2019 in Digital Logic ajaysoni1924 150 views
1 vote
0 answers
9
Morris Mano Edition 3 Exercise 5 Question 2 (Page No. 197)
Construct a BCD-to-Excess-3-code converter with a 4-bit adder.remember that the Excess-3 code digits obtained by adding 3 to the corresponding BCD Digit. what must be done to change the circuit to an excess-3-to-BCD-code converter
Construct a BCD-to-Excess-3-code converter with a 4-bit adder.remember that the Excess-3 code digits obtained by adding 3 to the corresponding BCD Digit. what must be done to change the circuit to an excess-3-to-BCD-code converter
asked Apr 3, 2019 in Digital Logic ajaysoni1924 100 views
0 votes
0 answers
10
Morris Mano Edition 3 Exercise 4 Question 28 (Page No. 151)
Design a combinational Circuit that converts a 4-bit gray code number to a 4-bit straight binary number. Implement the circuit with Exclusive OR gates.
Design a combinational Circuit that converts a 4-bit gray code number to a 4-bit straight binary number. Implement the circuit with Exclusive OR gates.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 38 views
0 votes
0 answers
11
Morris Mano Edition 3 Exercise 4 Question 29 (Page No. 151)
Design a circuit of a three-bit parity generator and the circuit of the four-bit parity checker using an odd parity bit.
Design a circuit of a three-bit parity generator and the circuit of the four-bit parity checker using an odd parity bit.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 20 views
1 vote
0 answers
12
Morris Mano Edition 3 Exercise 4 Question 30 (Page No. 151)
Manipulate the following Boolean Expression in such a way so that it can be implemented using exclusive-OR and AND gates only. $AB’CD’ + A’BCD’ + AB’C’D + A’BC’D$
Manipulate the following Boolean Expression in such a way so that it can be implemented using exclusive-OR and AND gates only. $AB’CD’ + A’BCD’ + AB’C’D + A’BC’D$
asked Apr 2, 2019 in Digital Logic ajaysoni1924 37 views
0 votes
0 answers
14
Morris Mano Edition 3 Exercise 4 Question 19 (Page No. 151)
Draw the NAND Gate Logic Diagram for each of the following Expressions using multilevel NAND gate Circuits. (AB’ + CD’)E + BC(A + B) w(x + y + z) + xyz
Draw the NAND Gate Logic Diagram for each of the following Expressions using multilevel NAND gate Circuits. (AB’ + CD’)E + BC(A + B) w(x + y + z) + xyz
asked Apr 2, 2019 in Digital Logic ajaysoni1924 20 views
1 vote
1 answer
15
Morris Mano Edition 3 Exercise 4 Question 16 (Page No. 150)
A BCD to seven segment decoder is a combinational circuit that converts a decimal digit in BCD to an appropriate code for the selection of the segments in the display indicator used for displaying the decimal digit in the ... decoder using the minimum number of the NAND gates. the Six invalid combinations should result in a blank display.
A BCD to seven segment decoder is a combinational circuit that converts a decimal digit in BCD to an appropriate code for the selection of the segments in the display indicator used for displaying the decimal digit in the familiar form. The seven output of the ... to Seven-segment decoder using the minimum number of the NAND gates. the Six invalid combinations should result in a blank display.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 78 views
0 votes
0 answers
16
Morris Mano Edition 3 Exercise 4 Question 15 (Page No. 150)
Design a combinational Circuit that converts a binary number of 4-bits to decimal number in BCD. Note that the BCD number is the same as the binary number as long as the digit is 9 or less than 9. binary numbers from 1010 to 1111 converts into BCD numbers from 1 0000 to 1 0101.
Design a combinational Circuit that converts a binary number of 4-bits to decimal number in BCD. Note that the BCD number is the same as the binary number as long as the digit is 9 or less than 9. binary numbers from 1010 to 1111 converts into BCD numbers from 1 0000 to 1 0101.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 55 views
0 votes
0 answers
19
Morris Mano Edition 3 Exercise 4 Question 12 (Page No. 149)
Design a combinational circuit that detects an error in the representation of a decimal digit in BCD. The output of the circuit must be equal to logic -1 when the input contains any one of the six unused bit combinations in the BCD code.
Design a combinational circuit that detects an error in the representation of a decimal digit in BCD. The output of the circuit must be equal to logic -1 when the input contains any one of the six unused bit combinations in the BCD code.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 95 views
0 votes
0 answers
20
Morris Mano Edition 3 Exercise 4 Question 11 (Page No. 149)
Design a combinational Circuit with the four inputs and four outputs.The output generates the 2’s complement of the input number.
Design a combinational Circuit with the four inputs and four outputs.The output generates the 2’s complement of the input number.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 52 views
0 votes
0 answers
21
Morris Mano Edition 3 Exercise 4 Question 10 (Page No. 149)
Design a combinational Circuit with four inputs that represent a decimal digit in BCD and the four outputs that Produce the 9’s complement of the input digit. Six unused combinations can be treated as Don’t care conditions.
Design a combinational Circuit with four inputs that represent a decimal digit in BCD and the four outputs that Produce the 9’s complement of the input digit. Six unused combinations can be treated as Don’t care conditions.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 69 views
0 votes
0 answers
22
Morris Mano Edition 3 Exercise 4 Question 7 (Page No. 149)
Design a combinational Circuit with four inputs that represent a decimal digit in BCD and the four outputs that Produce the 9’s complement of the input digit. Six unused combinations can be treated as Don’t care conditions.
Design a combinational Circuit with four inputs that represent a decimal digit in BCD and the four outputs that Produce the 9’s complement of the input digit. Six unused combinations can be treated as Don’t care conditions.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 21 views
0 votes
0 answers
23
Morris Mano Edition 3 Exercise 4 Question 9 (Page No. 149)
Design a combinational circuit with three inputs and six outputs. The output binary number should be the square of the input binary numbers.
Design a combinational circuit with three inputs and six outputs. The output binary number should be the square of the input binary numbers.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 51 views
0 votes
0 answers
25
Morris Mano Edition 3 Exercise 4 Question 7 (Page No. 149)
Design a combinational Circuit that multiplies two-bit numbers $a _1a _0$ and $b _1b _0$, to produce a four-bit product, $c _3c _2c _1c _0$. Use AND gates and Half Adders
Design a combinational Circuit that multiplies two-bit numbers $a _1a _0$ and $b _1b _0$, to produce a four-bit product, $c _3c _2c _1c _0$. Use AND gates and Half Adders
asked Apr 2, 2019 in Digital Logic ajaysoni1924 14 views
0 votes
0 answers
26
Morris Mano Edition 3 Exercise 4 Question 6 (Page No. 149)
A combination circuit produces the binary sum of two bits numbers, $x _1x _0$ and $y _1 y _0$. the outputs are C, $S _1 $ and $S _0$. Design a combinational Circuit of problem using two full adders.
A combination circuit produces the binary sum of two bits numbers, $x _1x _0$ and $y _1 y _0$. the outputs are C, $S _1 $ and $S _0$. Design a combinational Circuit of problem using two full adders.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 20 views
0 votes
0 answers
27
Morris Mano Edition 3 Exercise 4 Question 5 (Page No. 149)
A combinational circuit produces the binary sum of 2-bit numbers, $x _1x _0 and y _1y _0$. the outputs are C. s1. and s0. Provide the truth table of the combinational circuit
A combinational circuit produces the binary sum of 2-bit numbers, $x _1x _0 and y _1y _0$. the outputs are C. s1. and s0. Provide the truth table of the combinational circuit
asked Apr 2, 2019 in Digital Logic ajaysoni1924 35 views
0 votes
0 answers
28
Morris Mano Edition 3 Exercise 4 Question 4 (Page No. 149)
Design a combinational circuit that adds 1 to a 4-bit binary number, $ A _3A _2A _1A _0$. For example, if the input of the circuit is, $ A _3A _2A _1A _0$ = 1101, the output is 1110, The circuit can be designed using 4 Half Adder.
Design a combinational circuit that adds 1 to a 4-bit binary number, $ A _3A _2A _1A _0$. For example, if the input of the circuit is, $ A _3A _2A _1A _0$ = 1101, the output is 1110, The circuit can be designed using 4 Half Adder.
asked Apr 2, 2019 in Digital Logic ajaysoni1924 23 views
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