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Recent questions tagged digital-circuits

1 votes
2 answers
153
K MAP
what will be the k Map for- $(P+Q'+R').(P+Q'+R).(P+Q+R')$ and the simplified SOP (Sum of Product) for the above the Boolean expression? Please try to make a k map in this format-
what will be the k Map for-$(P+Q'+R').(P+Q'+R).(P+Q+R')$and the simplified SOP (Sum of Product) for the above the Boolean expression?Please try to make a k map in this fo...
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1 votes
3 answers
154
k map
Consider the Karnaugh map given below, where X represents "don't care" and blank represents 0. what will be the SOP?
Consider the Karnaugh map given below, where X represents "don't care" and blank represents 0. what will be the SOP?
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1 votes
2 answers
155
k map minimization digital logic
What is the minimal $Sum-Of-Products$ of the map? ($X$ is a don't care)
What is the minimal $Sum-Of-Products$ of the map? ($X$ is a don't care)
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0 votes
2 answers
156
CIRCUIT OUTUT
I/P TO NAND GATE IS - A,B I/P TO NOT GATE IS - C WHAT WIL BE THE O/P - F?
I/P TO NAND GATE IS - A,B I/P TO NOT GATE IS - C WHAT WIL BE THE O/P - F?
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0 votes
3 answers
157
digital circuit output
$\text{what is the o/p of this circuit ?}$
$\text{what is the o/p of this circuit ?}$
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1 votes
0 answers
158
digital logic
Can a 4:1 MUX operate as 2:1? (I understand 4:1 can be realized using 2:1 Mux but is reverse possible, may be by grounding?)
Can a 4:1 MUX operate as 2:1? (I understand 4:1 can be realized using 2:1 Mux but is reverse possible, may be by grounding?)
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0 votes
0 answers
159
doubt in digital
Why carry and borrow are complemented in unsigned number? Please explain clearly
Why carry and borrow are complemented in unsigned number?Please explain clearly
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1 votes
3 answers
160
Digital Circuit
Can P) and Q) could be answer same time (Number of NAND and NOR gates could be same)?
Can P) and Q) could be answer same time (Number of NAND and NOR gates could be same)?
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2 votes
1 answer
161
[ACE test Serieis] DL
The answer given is B Shouldn't the answer be A ?
The answer given is BShouldn't the answer be A ?
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3 votes
1 answer
162
Digital circuit
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4 votes
1 answer
163
Digital logic design
Explain each term in detailed
Explain each term in detailed
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1 votes
0 answers
164
Digital logic gateforum
A MOD-12 and a MOD-10 counter are cascaded. If the input clock frequency is 60 MHz, the output frequency is ________ (KHz).
A MOD-12 and a MOD-10 counter are cascaded. If the input clock frequency is 60 MHz, the output frequency is ________ (KHz).
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2 votes
0 answers
165
Digital logic design
Provide the solution in detail
Provide the solution in detail
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10 votes
2 answers
167
Digital logic design
How many Boolean functions of three variables $\textsf{f(x,y,z)}$ have the property that $\textsf{f(x,y,z)=(f(x’,y’,z’))}$? $64$ $16$ $256$ $8$
How many Boolean functions of three variables $\textsf{f(x,y,z)}$ have the property that $\textsf{f(x,y,z)=(f(x’,y’,z’))}$?$64$$16$$256$$8$
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1 votes
1 answer
168
Digital
Simplify F(ABCD) = ∑m (0,1,5,9,13,14,15) +d(3,4,7,10,11) .
Simplify F(ABCD) = ∑m (0,1,5,9,13,14,15) +d(3,4,7,10,11) .
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3 votes
1 answer
170
MadeEasy Test Series: Digital Logic - Multiplexer
A 32 : 1 MUX has to be designed using a 16 : 1 MUX. It was found that for this task we require ‘X ’ number of 16 : 1 MUX and “Y ” number of two input OR gates, then the value of X + Y = __________.
A 32 : 1 MUX has to be designed using a 16 : 1 MUX. It was found that for this task we require ‘X ’ number of 16 : 1 MUX and “Y ” number of two input OR gates, th...
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0 votes
0 answers
171
digital logic
Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be Q1 Q0 = 00 For an input sequence X = 1010, the respective output sequence will be _______.
Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be Q1 Q0 = 00 For an input sequence X = 1010, the respective output sequence...
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0 votes
0 answers
173
No of 2 input NOR gates
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0 votes
1 answer
174
Counters
Is this statement true? Nonbinary counter means synchronous counter?
Is this statement true?Nonbinary counter means synchronous counter?
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3 votes
4 answers
176
Gate CS 1996 Question no. 47
f implements, A) (ABC)' + A'BC' + ABC B) A + B + C C) A ⊕ B ⊕ C D) AB + BC + CA
f implements,A) (ABC)' + A'BC' + ABCB) A + B + CC) A ⊕ B ⊕ CD) AB + BC + CA
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7 votes
1 answer
177
digital logic dual negation of circuits
A positive level logic digital circuit is shown below. The negative level logic digital circuit for the given circuit is:
A positive level logic digital circuit is shown below.The negative level logic digital circuit for the given circuit is:
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1 votes
1 answer
178
counters
mod 1 mod 3 mod 4 mod 2
mod 1 mod 3 mod 4 mod 2
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