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Recent questions tagged digital-counter
2
votes
1
answer
121
Digital Logic
reena_kandari
495
views
reena_kandari
asked
Jan 11, 2017
Digital Logic
combinational-circuit
digital-counter
digital-logic
+
–
2
votes
2
answers
122
Virtual Gate Test Series: Digital Logic - Counter
smartmeet
633
views
smartmeet
asked
Jan 10, 2017
Digital Logic
digital-logic
flip-flop
digital-counter
virtual-gate-test-series
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0
votes
0
answers
123
MadeEasy Subject Test: Digital Logic - Digital Counter
How to decide whether it synchronous or asynchronous?
How to decide whether it synchronous or asynchronous?
vaishali jhalani
312
views
vaishali jhalani
asked
Jan 10, 2017
Digital Logic
digital-logic
made-easy-test-series
digital-counter
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–
0
votes
1
answer
124
doubt
Prateek kumar
338
views
Prateek kumar
asked
Jan 3, 2017
Digital Logic
digital-counter
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–
1
votes
1
answer
125
doubt
Prateek kumar
370
views
Prateek kumar
asked
Jan 3, 2017
Digital Logic
digital-counter
+
–
1
votes
1
answer
126
doubt
Prateek kumar
262
views
Prateek kumar
asked
Jan 2, 2017
Digital Logic
digital-logic
digital-counter
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–
0
votes
1
answer
127
doubt
Prateek kumar
394
views
Prateek kumar
asked
Jan 2, 2017
Digital Logic
digital-logic
digital-counter
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1
votes
0
answers
128
Counter problem - Digital Logic
Anup patel
292
views
Anup patel
asked
Dec 31, 2016
Digital Logic
digital-logic
digital-counter
+
–
1
votes
1
answer
129
Positive Edge Triggered and negative Edge Triggerd
Suppose we have a ripple counter then what will be the difference in output if we use 1) Positive Edge Triggered Clock pulse 2) Negative Edge Triggered Clock pulse
Suppose we have a ripple counter then what will be the difference in output if we use 1) Positive Edge Triggered Clock pulse2) Negative Edge Triggered Clock pulse
Anup patel
651
views
Anup patel
asked
Dec 31, 2016
Digital Logic
digital-logic
digital-counter
+
–
0
votes
1
answer
130
Ace Test Series: Digital Logic - Digital Counter
sourojit
288
views
sourojit
asked
Dec 24, 2016
Digital Logic
ace-test-series
digital-logic
digital-counter
clock-frequency
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–
0
votes
0
answers
131
Digital logic asynchronous counter
Is it possible to use asynchronous /ripple counter to design random sequence?
Is it possible to use asynchronous /ripple counter to design random sequence?
rahul sharma 5
366
views
rahul sharma 5
asked
Dec 23, 2016
Digital Logic
digital-counter
digital-logic
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–
0
votes
2
answers
132
Frequency of output signal?
I got the ans as 1/(5*25) = 1/125. None of the, match
I got the ans as 1/(5*25) = 1/125. None of the, match
prasitamukherjee
657
views
prasitamukherjee
asked
Dec 18, 2016
Digital Logic
digital-logic
clock-frequency
digital-counter
+
–
0
votes
3
answers
133
MadeEasy Test Series: Digital Logic - Digital Counter
my doubt is how decade counter and how it takes 10??? plz explain??
my doubt is how decade counter and how it takes 10??? plz explain??
Hradesh patel
922
views
Hradesh patel
asked
Dec 5, 2016
Digital Logic
made-easy-test-series
digital-logic
digital-counter
+
–
2
votes
1
answer
134
MadeEasy Test Series: Digital Logic - Digital Counter
santhoshdevulapally
725
views
santhoshdevulapally
asked
Nov 29, 2016
Digital Logic
made-easy-test-series
digital-logic
digital-counter
+
–
15
votes
4
answers
135
ME test
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of the MOD256 counter ? (in MHz)
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the...
Lokesh .
3.8k
views
Lokesh .
asked
Nov 25, 2016
Digital Logic
digital-logic
digital-counter
flip-flop
+
–
21
votes
5
answers
136
GATE CSE 1990 | Question: 5-c
For the synchronous counter shown in Fig$.3,$ write the truth table of $Q_{0}, Q_{1}$, and $Q_{2}$ after each pulse, starting from $Q_{0}=Q_{1}=Q_{2}=0$ and determine the counting sequence and also the modulus of the counter.
For the synchronous counter shown in Fig$.3,$ write the truth table of $Q_{0}, Q_{1}$, and $Q_{2}$ after each pulse, starting from $Q_{0}=Q_{1}=Q_{2}=0$ and determine the...
makhdoom ghaya
6.3k
views
makhdoom ghaya
asked
Nov 23, 2016
Digital Logic
gate1990
descriptive
digital-logic
sequential-circuit
flip-flop
digital-counter
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–
7
votes
1
answer
137
Self Doubt | Modulus Counter
Q1. How many flip-flops are required to construct mod 4 counter? Ans - 2 right ? Alway it should be 2 or it may not be 2. Q2 . If We want to design a synchronous counter that counts the sequence 0−1−0−2−0−3 and then repeats. A) What ... design-modulo-272-counter https://gateoverflow.in/82111/is-bcd-or-mod-10-counter-are-same https://gateoverflow.in/39670/gate-2016-1-8
Q1. How many flip-flops are required to construct mod 4 counter? Ans - 2 right ? Alway it should be 2 or it may not be 2.Q2 . If We want to design a synchronous counter ...
vijaycs
1.4k
views
vijaycs
asked
Nov 22, 2016
Digital Logic
digital-logic
digital-counter
flip-flop
+
–
18
votes
3
answers
138
GATE CSE 1987 | Question: 13-a
The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ ... $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is $0000$ $1111$ $1001$ $1000$
The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ gate. The initial state and three subsequent states for three cl...
makhdoom ghaya
3.7k
views
makhdoom ghaya
asked
Nov 15, 2016
Digital Logic
gate1987
digital-logic
circuit-output
sequential-circuit
digital-counter
shift-registers
+
–
6
votes
1
answer
139
GATE CSE 1987 | Question: 10c
Give a minimal DFA that performs as a $\mod - 3,\;$ $1$'s counter, i.e. outputs a $1$ each time the number of $1$'s in the input sequence is a multiple of $3$.
Give a minimal DFA that performs as a $\mod - 3,\;$ $1$'s counter, i.e. outputs a $1$ each time the number of $1$'s in the input sequence is a multiple of $3$.
makhdoom ghaya
2.4k
views
makhdoom ghaya
asked
Nov 14, 2016
Digital Logic
gate1987
digital-logic
digital-counter
descriptive
+
–
29
votes
1
answer
140
Doubt regarding minimum FF's required?
In previous two year's a question has been asked for finding number of flip flop's for counting sequence $\color{navy}{0-1-0-2-0-3}$ in 2016 and $\color{navy}{0-0-1-1-2-2-3-3-0-0}$ in 2015. But still, the approach discussed in these questions hasn't arrived at Common answer ( ... $2). 0-1-0-2-0-2-0-3-0-2-...$ $3). 1-2-3-0-0-1-0-2-2-...$
In previous two year's a question has been asked for finding number of flip flop's for counting sequence $\color{navy}{0-1-0-2-0-3}$ in 2016 and $\color{navy}{0-0-1-1-2-2...
mcjoshi
2.5k
views
mcjoshi
asked
Nov 12, 2016
Digital Logic
digital-logic
digital-counter
+
–
6
votes
1
answer
141
GATE CSE 1987 | Question: 1-III
The above circuit produces the output sequence: $1111\quad 1111\quad0000\quad0000$ $1111 \quad 0000\quad1111\quad0000$ $1111 \quad 0001\quad0011\quad0101$ $1010\quad1010\quad1010\quad1010$
The above circuit produces the output sequence:$1111\quad 1111\quad0000\quad0000$$1111 \quad 0000\quad1111\quad0000$$1111 \quad 0001\quad0011\quad0101$$1010\quad1010\quad...
makhdoom ghaya
4.9k
views
makhdoom ghaya
asked
Nov 7, 2016
Digital Logic
gate1987
digital-logic
sequential-circuit
flip-flop
digital-counter
+
–
3
votes
1
answer
142
Digital Counters
Q..A 4 bit Counter having flip-flops with identical propagation delay time of 50ns will have maximum frequency limit of ____ MHZ??? My question is how to know wheather the question is talking about Synchronous counter or Asynchronous counter??? For Sync. it will be 1/50ns for Async. it will be 1/(4*50)ns which obe to take?????
Q..A 4 bit Counter having flip-flops with identical propagation delay time of 50ns will have maximum frequency limit of ____ MHZ???My question is how to know wheather the...
bad_engineer
735
views
bad_engineer
asked
Oct 26, 2016
Digital Logic
digital-logic
digital-counter
flip-flop
testbook-test-series
+
–
3
votes
1
answer
143
Counter
For a Mod-10 counter, Jhonson counter uses X FF′s, ring counter uses y FF′s, and ripple counter uses Z FF′s. Then X + Y + Z will ________.
For a Mod-10 counter, Jhonson counter uses X FF′s, ring counter uses y FF′s, and ripple counter uses Z FF′s. Then X + Y + Z will ________.
srestha
2.3k
views
srestha
asked
Oct 25, 2016
Digital Logic
digital-counter
+
–
2
votes
1
answer
144
Clock frequency required for proper operation of ripple counter
An 8 stage ripple counter uses a flip flop with propagation delay of 75 ns. The pulse width of strobe is 50ns. The frequency of input signal which can be used for proper operation of counter is? (A) 1 MHz (B) 500 MHz (C) 1.5 MHz (D) 2 MHz
An 8 stage ripple counter uses a flip flop with propagation delay of 75 ns. The pulse width of strobe is 50ns. The frequency of input signal which can be used for proper ...
GateAspirant999
7.9k
views
GateAspirant999
asked
Oct 17, 2016
Digital Logic
digital-logic
clock-frequency
digital-counter
+
–
9
votes
1
answer
145
Counters+Frequency
___________ $\text{kHz}$ is the sum of frequencies at the points $a, b,c \text{ and } d$.
___________ $\text{kHz}$ is the sum of frequencies at the points $a, b,c \text{ and } d$.
Rahul Jain25
6.7k
views
Rahul Jain25
asked
Oct 13, 2016
Digital Logic
digital-logic
digital-counter
clock-frequency
+
–
1
votes
3
answers
146
Virtual Gate Test Series: Digital Logic - Asynchronous Counter
Hradesh patel
900
views
Hradesh patel
asked
Oct 8, 2016
Digital Logic
digital-logic
synchronous-asynchronous-circuits
digital-counter
virtual-gate-test-series
+
–
1
votes
1
answer
147
Counter
4-bit 16 module ripple counter uses JK-flip flop.propagation delay of each flip flop is 50ns find max clock frequncy.
4-bit 16 module ripple counter uses JK-flip flop.propagation delay of each flip flop is 50ns find max clock frequncy.
papesh
1.2k
views
papesh
asked
Oct 4, 2016
Digital Logic
digital-counter
flip-flop
+
–
2
votes
1
answer
148
MadeEasy Workbook: Digital Logic - Digital Counter
Q. if a counter having 10 FF's is initially at 0 ,what count will it hold after 2060 pulses??? a) 000 000 1100 b) 000 001 1100 c) 000 001 1000 d) 000 000 1110
Q. if a counter having 10 FF's is initially at 0 ,what count will it hold after 2060 pulses???a) 000 000 1100b) 000 001 1100c) 000 001 1000d) 000 000 1110
Hradesh patel
514
views
Hradesh patel
asked
Oct 1, 2016
Digital Logic
made-easy-booklet
digital-logic
digital-counter
+
–
0
votes
1
answer
149
GATE Overflow | Digital Logic | Test 1 | Question: 22
On the fifth clock pulse, a 4-bit Johnson sequence is $Q_0 = 0, Q_1 = 1, Q_2 = 1,$ and $Q_3 = 1$. On the sixth clock pulse, the sequence is ________. $Q_0 = 1, Q_1 = 0, Q_2 = 0, Q_3 = 0$ $Q_0 = 1, Q_1 = 1, Q_2 = 1, Q_3 = 0$ $Q_0 = 0, Q_1 = 0, Q_2 = 1, Q_3 = 1$ $Q_0 = 0, Q_1 = 0, Q_2 = 0, Q_3 = 1$
On the fifth clock pulse, a 4-bit Johnson sequence is $Q_0 = 0, Q_1 = 1, Q_2 = 1,$ and $Q_3 = 1$. On the sixth clock pulse, the sequence is ________.$Q_0 = 1, Q_1 = 0, Q_...
Bikram
134
views
Bikram
asked
Sep 20, 2016
Digital Logic
digital-logic
go-digital-logic-1
digital-counter
+
–
1
votes
3
answers
150
GATE Overflow | Digital Logic | Test 1 | Question: 6
The minimum number of Flip-Flops required to construct a binary Modulo $n$ counter is ________ $n$ $n-1$ $2^n – 1$ $\lceil \log_2 n \rceil$
The minimum number of Flip-Flops required to construct a binary Modulo $n$ counter is ________$n$$n-1$$2^n – 1$$\lceil \log_2 n \rceil$
Bikram
816
views
Bikram
asked
Sep 20, 2016
Digital Logic
digital-logic
go-digital-logic-1
flip-flop
digital-counter
+
–
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