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Recent questions tagged digital-logic
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GATE CSE 2024 | Set 2 | Question: 4
The format of a single-precision floating-point number as per the $\text{IEEE 754}$ standard is: Sign Exponent Mantissa $(1 \mathrm{bit})$ $(8 \mathrm{bits})$ $(23 \mathrm{bits})$ Choose the largest floating- ... $0$ $11111111$ $11111111111111111111111$ Sign Exponent Mantissa $0$ $01111111$ $00000000000000000000000$
Arjun
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Digital Logic
Feb 16
by
Arjun
2.2k
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gatecse2024-set2
digital-logic
number-representation
ieee-representation
2
votes
2
answers
2
GATE CSE 2024 | Set 2 | Question: 20
For a Boolean variable $x$, which of the following statements is/are FALSE? $x .1=x$ $x+1=x$ $x \cdot x=0$ $x+\bar{x}=1$
Arjun
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Digital Logic
Feb 16
by
Arjun
1.8k
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gatecse2024-set2
digital-logic
boolean-algebra
easy
multiple-selects
1
vote
1
answer
3
GATE CSE 2024 | Set 2 | Question: 39
Which of the following is/are EQUAL to $224$ in radix - $5$ (i.e., base - $5$) notation? $64$ in radix -10 $100$ in radix -8 $50$ in radix -16 $121$ in radix -7
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Digital Logic
Feb 16
by
Arjun
1.5k
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gatecse2024-set2
digital-logic
number-representation
multiple-selects
2
votes
1
answer
4
GATE CSE 2024 | Set 2 | Question: 40
Consider $4$-variable functions $f 1, f 2, f 3, f 4$ expressed in sum-of-minterms form as given below. \[ \begin{array}{l} f 1=\sum(0,2,3,5,7,8,11,13) \\ f 2=\sum(1,3,5,7,11,13,15) \\ f 3=\sum(0,1,4,11) \\ f 4=\sum(0,2,6,13) \end{array} \] With ... $\boldsymbol{Y}=\sum(0,1,2,3,4,5,6,7)$ $\boldsymbol{Y}=\Pi(8,9,10,11,12,13,14,15)$
Arjun
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Digital Logic
Feb 16
by
Arjun
1.5k
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gatecse2024-set2
digital-logic
canonical-normal-form
multiple-selects
2
votes
5
answers
5
GATE CSE 2024 | Set 1 | Question: 3
Consider a system that uses $5$ bits for representing signed integers in $2$ 's complement format. In this system, two integers $A$ and $B$ are represented as $A$=$01010$ and $B$=$11010$. Which one of the following operations will result in either an arithmetic overflow or an arithmetic underflow? $A+B$ $A-B$ $B-A$ $2 * B$
Arjun
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in
Digital Logic
Feb 16
by
Arjun
3.3k
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gatecse2024-set1
digital-logic
2
votes
1
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6
GATE CSE 2024 | Set 1 | Question: 18
Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT? With no propagation ... , the output $Y$ can have a transient logic Zero after $X$ transitions from logic One to logic Zero
Arjun
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Digital Logic
Feb 16
by
Arjun
2.0k
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gatecse2024-set1
multiple-selects
digital-logic
0
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2
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7
GATE CSE 2024 | Set 1 | Question: 37
Consider a Boolean expression given by $\text{F(X, Y, Z)}=\sum(3,5,6,7)$. Which of the following statements is/are CORRECT? $\text{F(X, Y, Z)}=\Pi(0,1,2,4)$ $\text{F(X, Y, Z)=X Y+Y Z+X Z}$ $\text{F(X, Y, Z)}$ is independent of input $\text{Y}$ $\text{F(X, Y, Z)}$ is independent of input $\text{X}$
Arjun
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Digital Logic
Feb 16
by
Arjun
1.7k
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gatecse2024-set1
multiple-selects
digital-logic
1
vote
3
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8
GATE CSE 2024 | Set 1 | Question: 54
Consider a digital logic circuit consisting of three $2$-to-$1$ multiplexers $\text{M1, M2}$, and $\text{M3}$ as shown below. $\mathrm{X} 1$ and $\mathrm{X} 2$ are inputs of $\mathrm{M} 1$. $\text{X3}$ and $\text{X4}$ are inputs ... the number of combinations of $\mathrm{A}, \mathrm{B}, \mathrm{C}$ that give the output $\mathbf{Y}=\mathbf{1}$ is ____________.
Arjun
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Digital Logic
Feb 16
by
Arjun
1.8k
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gatecse2024-set1
numerical-answers
digital-logic
multiplexer
2
votes
1
answer
9
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 28
Consider function $\mathbf{G}(\mathbf{A}, \mathbf{B}, \mathbf{C})=\mathbf{A B}+\mathbf{B C}$. Let $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ ... input to a 2-to-1 multiplexer. The correct implementation of $\mathbf{F}(\mathbf{A}, \mathbf{B}, \mathbf{C})$ is shown in:
GO Classes
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in
Digital Logic
Feb 5
by
GO Classes
424
views
goclasses2024-mockgate-14
digital-logic
combinational-circuit
multiplexer
1-mark
3
votes
1
answer
10
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 29
The largest positive number in 2's complement format represented with 8-bits is: $(\mathrm{FF})_{16}$ $(128)_{10}$ $(777)_8$ $(01111111)_2$
GO Classes
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in
Digital Logic
Feb 5
by
GO Classes
411
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goclasses2024-mockgate-14
digital-logic
number-representation
1-mark
4
votes
1
answer
11
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 30
Consider the function $f\left(x_1, x_2, x_3\right)=x_1 \cdot x_2 \cdot x_3+\bar{x}_1 \cdot \bar{x}_2 \cdot \bar{x}_3+\bar{x}_1 \cdot x_2 \cdot \bar{x}_3+\bar{x}_1 \cdot x_2 \cdot x_3$, what is the product of sum(POS) expression ...
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Digital Logic
Feb 5
by
GO Classes
410
views
goclasses2024-mockgate-14
digital-logic
boolean-algebra
1-mark
2
votes
1
answer
12
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 59
Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register using the parallel load mechanism (i.e., shift=0 ... consecutive positive edges of the clock signal we need to keep shift=1 such that zero detect is activated to a 1?
GO Classes
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in
Digital Logic
Feb 5
by
GO Classes
431
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goclasses2024-mockgate-14
numerical-answers
digital-logic
sequential-circuit
shift-registers
2-marks
3
votes
0
answers
13
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 60
The logic circuit above is used to compare two unsigned 2-bit numbers, $X_1 X_0=X$ and $Y_1 Y_0=Y$, where $X_0$ and $Y_0$ are the least significant bits. (A small circle on any line in a logic diagram indicates logical NOT.) Which of the following always makes the output $Z$ have the value 1? $X\gt Y$ $X\lt Y$ $X=Y$ $X \neq Y$
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in
Digital Logic
Feb 5
by
GO Classes
278
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goclasses2024-mockgate-14
digital-logic
combinational-circuit
digital-circuits
2-marks
5
votes
2
answers
14
GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 61
According to the IEEE standard, a 32-bit, single-precision, floating-point number $N$ is defined to be $ N=(-1)^S \times 1 . F \times 2^{E-127} $ where $S$ is the sign bit, $F$ the fractional mantissa, and $E$ the biased exponent. A floating- ... $\left(1-2^{-23}\right) * 2^{128}$ $\left(1+\left(1-2^{-23}\right)\right) * 2^{128}$
GO Classes
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in
Digital Logic
Feb 5
by
GO Classes
502
views
goclasses2024-mockgate-14
digital-logic
number-representation
ieee-representation
floating-point-representation
2-marks
3
votes
1
answer
15
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 25
A garage door opens if it ever sees the password $011$ in a transmission. More formally, this FSM takes a bitstring consisting of $\text{0's}$ and $\text{1's}$ as its input, and continually outputs $\text{0's}$ until it sees the substring $011,$ after which ... ? Arrow $1 - (0/0)$ Arrow $3 - (1/0)$ Arrow $4 - (1/0)$ Arrow $5 - (1/1)$
GO Classes
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in
Digital Logic
Jan 28
by
GO Classes
323
views
goclasses2024-mockgate-13
goclasses
digital-logic
sequential-circuit
finite-automata
multiple-selects
1-mark
4
votes
1
answer
16
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 26
The figure below represents the Karnaugh map for a function $\text{F(A,B,C,D).}$ Note, $\text{ X'}$ stands for don't care. The simplified logical expression in the sum-of-products (SOP) form (i.e., the minimum number of ... can be converted into a circuit implementation using only NAND gates, which is shown in: a b c d
GO Classes
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in
Digital Logic
Jan 28
by
GO Classes
295
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goclasses2024-mockgate-13
goclasses
digital-logic
boolean-algebra
k-map
1-mark
2
votes
1
answer
17
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 27
What statement is correct for $f(A, B)$ in the following circuit? $f(A, B)=\overline{\overline{A \cdot B} \cdot(A+B)}$ when Control $=1$ $f(A, B)=A \cdot B$ when Control $=0$ $f(A, B)=\overline{A}+\overline{B}$ when Control $=1$ $f(A, B)=\overline{A} \cdot \overline{B}$ when Control $=0$
GO Classes
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in
Digital Logic
Jan 28
by
GO Classes
295
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goclasses2024-mockgate-13
goclasses
digital-logic
digital-circuits
multiple-selects
1-mark
5
votes
1
answer
18
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 29
In two's complement, what is the minimum number of bits needed to represent the numbers $-1$ and the number $1$ respectively? $1$ and $2$ $2$ and $2$ $2$ and $1$ $1$ and $1$
GO Classes
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Digital Logic
Jan 28
by
GO Classes
445
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goclasses2024-mockgate-13
goclasses
digital-logic
number-representation
1-mark
2
votes
3
answers
19
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 59
For the circuit in the figure below, if the current state $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0$ is $6$ (in decimal) i.e. $\text{Q}_3\text{Q}_2\text{Q}_1\text{Q}_0=0110,$ then after the next positive edge of the clock signal the new state will be (in decimal)? (the flip-flops are positive edge triggered)
GO Classes
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Digital Logic
Jan 28
by
GO Classes
473
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goclasses2024-mockgate-13
goclasses
numerical-answers
digital-logic
sequential-circuit
digital-counter
2-marks
4
votes
2
answers
20
GO Classes Test Series 2024 | Mock GATE | Test 13 | Question: 60
You are asked to implement the following four functions with half-adders: ... of half-adders required to implement all four functions simultaneously? (You are not allowed to use any other logic element but half-adder)
GO Classes
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in
Digital Logic
Jan 28
by
GO Classes
438
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goclasses2024-mockgate-13
goclasses
numerical-answers
digital-logic
combinational-circuit
adder
2-marks
0
votes
1
answer
21
how is the minimum number of NOR gates required is 5?
pcla
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Digital Logic
Jan 28
by
pcla
145
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digital-logic
made-easy-test-series
3
votes
1
answer
22
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 21
How many $\text{4-to-1}$ multiplexers are needed to implement a $\text{64-to-1}$ multiplexer?
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Digital Logic
Jan 21
by
GO Classes
353
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goclasses2024-mockgate-12
goclasses
numerical-answers
digital-logic
combinational-circuit
multiplexer
1-mark
easy
2
votes
1
answer
23
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 22
What is the output for the following circuit? $w=\overline{b} c$ $w=b \oplus c$ $w=\overline{b \oplus c}$ $w=\overline{b}+\overline{c}$
GO Classes
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in
Digital Logic
Jan 21
by
GO Classes
340
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goclasses2024-mockgate-12
goclasses
digital-logic
combinational-circuit
multiplexer
1-mark
2
votes
1
answer
24
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 51
We would like to use a $\text{T}$ flip-flop and design a circuit that works like a $\text{J-K}$ flip-flop. The simplified input to the $\text{T}$ flip-flop should be: $\mathrm{T}=\mathrm{J}=\mathrm{K}$ $\text{T}=\text{JQ}^{\prime}+\text{K}^{\prime} Q$ $\text{T}=\text{JQ}^{\prime}+K Q$ $\text{T}=\text{JQ}+\text{KQ}'$
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Digital Logic
Jan 21
by
GO Classes
428
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goclasses2024-mockgate-12
goclasses
digital-logic
sequential-circuit
flip-flop
2-marks
3
votes
1
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25
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 52
Consider the sequential circuit shown below. Consider the following state assignment: $\text{A}$ stands for $\text{Q = 0, B}$ stands for $\text{Q = 1}.$ The state transition diagram for the circuit above is shown in: a b c d
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Digital Logic
Jan 21
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GO Classes
571
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goclasses2024-mockgate-12
goclasses
digital-logic
sequential-circuit
flip-flop
2-marks
5
votes
2
answers
26
GO Classes Test Series 2024 | Mock GATE | Test 12 | Question: 53
Consider the following $4$-bit adder circuit. Note, $\text{C}_0$ is carry in and $\text{C}_4$ is carry out for the $4$-bit adder. The given circuit operates on $\text{2's}$ ... $\text{S}=1$
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Jan 21
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GO Classes
593
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goclasses
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adder
multiple-selects
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0
votes
0
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27
Byjus Mock Test
I am unable to understand the language of the question , can someone help me??
Dadu
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in
Digital Logic
Jan 15
by
Dadu
120
views
digital-logic
multiplexer
3
votes
1
answer
28
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 16
Which one of the following options is CORRECT for the given logic circuit? $P=1, Q=1 ; X=0$ $P=1, Q=0 ; X=1$ $P=0, Q=1 ; X=0$ $P=0, Q=0 ; X=1$
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Jan 13
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GO Classes
332
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goclasses2024-mockgate-11
goclasses
digital-logic
combinational-circuit
digital-circuits
multiple-selects
1-mark
4
votes
1
answer
29
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 17
Consider the bit pattern $10110110.$ Interpret this bit pattern as a $8$-bit $2$'s complement number. What is the largest magnitude negative number that can be added to this value without causing $8$-bit $2$'s complement overflow? (Write your answer in decimal, only the magnitude, not the sign)
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Digital Logic
Jan 13
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GO Classes
516
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goclasses2024-mockgate-11
goclasses
numerical-answers
digital-logic
number-representation
1-mark
2
votes
2
answers
30
GO Classes Test Series 2024 | Mock GATE | Test 11 | Question: 39
The circuit shown below is designed using two multiplexers. This circuit is equivalent to: a positive edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\mathrm{T}$ flip flop a negative edge triggered $\text{D}$ flip flop a positive edge triggered $\mathrm{D}$ flip flop
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Jan 13
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GO Classes
739
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flip-flop
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