search
Log In

Recent questions tagged digital-logic

0 votes
1 answer
1
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
asked Aug 28 in Digital Logic Lakshman Patel RJIT 200 views
0 votes
1 answer
2
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28 in Digital Logic Lakshman Patel RJIT 102 views
0 votes
1 answer
3
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
asked Aug 28 in Digital Logic Lakshman Patel RJIT 103 views
0 votes
0 answers
4
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28 in Digital Logic Lakshman Patel RJIT 63 views
0 votes
1 answer
6
0 votes
2 answers
9
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip flops Clock input of one flip-flop
asked Apr 1 in Digital Logic Lakshman Patel RJIT 92 views
0 votes
1 answer
10
3 votes
2 answers
11
1 vote
3 answers
12
0 votes
2 answers
13
3 votes
10 answers
15
1 vote
3 answers
16
1 vote
2 answers
17
1 vote
1 answer
18
In a ripple counter using edge triggered $JK$ flip-flops, the pulse input is applied to the clock input of all flip-flops clock input of one flip-flop $J$ and $K$ inputs of all flip-flops $J$ and $K$ inputs of one flip flop
asked Mar 31 in Digital Logic Lakshman Patel RJIT 239 views
1 vote
1 answer
19
0 votes
2 answers
20
1 vote
3 answers
21
0 votes
1 answer
22
Disadvantage of dynamic RAM over static RAM is higher power consumption. variable speed. need to refresh the capacitor charge every once in two milliseconds. higher bit density.
asked Mar 31 in Digital Logic Lakshman Patel RJIT 112 views
1 vote
5 answers
26
1 vote
1 answer
28
1 vote
2 answers
29
...