Recent questions tagged digital-logic

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Test Book digital logic
I think option A is also correct ! if we take minterm and complement it to get POS then option A can also be the answer

asked Apr 9 in Digital Logic by Shawn Frost (19 points) | 54 views

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Morris Mano Edition 3 Exercise 9 Question 24 (Page No. 396)
The boolean functions for the input of SR latch are as follows. Obtain the circuit diagram using a minimum number of NAND gates. $S = x _1’x _2’x _3 + x _1x _2x _3$. $R = x _1x _2’ + x _2x _3’$

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 14 views

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Morris Mano Edition 3 Exercise 9 Question 23 (Page No. 396)
Draw the logic diagram of the product of sum expression $ Y = (x _1 + x _2’)(x _2 + x _3)$ Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero and $x _2$ goes from 0 to 1.Find a way to remove hazard by adding one more OR gate.

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 4 views

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Morris Mano Edition 3 Exercise 9 Question 22 (Page No. 396)
Find a circuit that has no static hazard and implements the boolean function: F(A,B,C,D) = $\sum(0,2,6,7,8,10,12)$

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 6 views

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Morris Mano Edition 3 Exercise 9 Question 18 (Page No. 395)
Merge each of the primitive flow table shown in the figure. Proceed as follows: Find all compatible pairs by means of implication table. Find the maximal compatibles by means of a merger diagram FInd the minimal set of compatibles that covers all the states and is closed.

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 16 views

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Morris Mano Edition 3 Exercise 9 Question 17 (Page No. 395)
Reduce the number of states in the state table listed below. Use an implication table.

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 11 views

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Morris Mano Edition 3 Exercise 9 Question 16 (Page No. 395)
Using the implication table method, show that the state table listed in the figure cannot be reduced any further.

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 11 views

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Morris Mano Edition 3 Exercise 9 Question 15 (Page No. 395)
Assign output values to the don’t care states in the flow tables in the figure below in such a way as to avoid transient output places

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 6 views

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Morris Mano Edition 3 Exercise 9 Question 14 (Page No. 394)
It is necessary to design an asynchronous sequential circuit with two inputs, $x _1 and x _2$, and one output $z$. Initially, both input and output are zero. when $x _1 and x _2$ becomes 1, z becomes 1. when the ... for the circuit and show that it can be reduced to the flow table shown in the figure complete the design of the circuit.

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 6 views

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Morris Mano Edition 3 Exercise 9 Question 13,25 (Page No. 394)
A traffic light is installed at the junction of the railroad and a road. The traffic light is controlled by two switches in the rails placed one mile apart on either side of the junction. A switch is turned on when a ... circuit. show that the flow table can be reduced to four rows Complete the circuit specified in the above problem.

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 9 views

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Morris Mano Edition 3 Exercise 9 Question 12 (Page No. 394)
Obtain a primitive flow table for a circuit with two inputs, $x _1 and x _2$ and two outputs $y _1 and y _2$, that satisfy the following four conditions. When $x _1x _2 = 00$, the output is $z _1z _2 = 00$. when $x _1 = 1$ and ... $x _1$ changes from 0 to 1, the output is $z _1z _2$ = 10. otherwise the output does not change.

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 3 views

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Morris Mano Edition 3 Exercise 9 Question 11 (Page No. 394)
Implement the circuit defined below with NAND SR latch. An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are as follows. $Y _1 = x _1x _2 + x _1y _2’ + x _2’y _1$ $Y _2 = x _2 + x _1y _1’y _2 + x _1’y _1$ $z = x _2 + y _1$

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 4 views

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Morris Mano Edition 3 Exercise 9 Question 10 (Page No. 394)
Implement the circuit with defined below with NOR SR latch. an asynchronous circuit is described by the following excitation and output functions: $Y = x _1x _2’ + (x _1 + x _2’)y$ $z = y$

asked Apr 8 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 6 views

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ISI2017-PCB-B-8(b)
Consider a simple code C for error detection and correction. Each codeword in C consists of 2 data bits $[d_1, d_0]$ followed by check bits $[c_2, c_1, c_0]$ ... '+' is a modulo-2 addition. Write down all the codewords for C Determine the minimum Hamming distance between any two distinct codewords of C

asked Apr 8 in Digital Logic by akash.dinkar12 Boss (39.2k points) | 14 views

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ISI2017-PCB-B-7(b)
Define a Boolean function $F(X_1, X_2, X_3, X_4, X_5, X_6)$ of six variables such that $\\ \begin{matrix} F & = & \text{1, when three or more input variables are at logic 1} \\ \: & = & \text{0, otherwise} \end{matrix} $ How many essential prime implicants does $F$ have? Justify they are essential.

asked Apr 8 in Digital Logic by akash.dinkar12 Boss (39.2k points) | 12 views

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Morris Mano Edition 3 Exercise 9 Question 9 (Page No. 394)
For the asynchronous sequential circuit shown in the figure: Derive the boolean functions for the outputs of two SR latches $Y _1 and Y _2$. Note that the S input of the second latch is $x _1’y _1’$. Derive the transition table and output map of the circuit.

asked Apr 7 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 7 views

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Morris Mano Edition 3 Exercise 9 Question 8 (Page No. 394)
Convert the circuit of the figure to the asynchronous sequential circuit by removing the clock-pulse(CP) and changes the flip-flops to the SR latches. Derive the transition table and output map of the modified circuit.

asked Apr 7 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 6 views

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Morris Mano Edition 3 Exercise 9 Question 7 (Page No. 394)
Analyze the T flip-flop shown in the figure. Obtain the transition table and show that the circuit is unstable when both T and CP are equal to 1.

asked Apr 7 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 6 views

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Morris Mano Edition 3 Exercise 9 Question 6 (Page No. 393)
Investigate the transition table of the figure and determine all the race conditions whether they are critical or not critical. Also, determine whether there are any cycles.

asked Apr 7 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 6 views

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Morris Mano Edition 3 Exercise 9 Question 5 (Page No. 393)
Convert the flow table of the figure into a transition table by assigning the following binary values to the states: a = 00, b = 11, and c = 10. Assign values to the extra fourth state to avoid critical races. Assign output to the don’t care states to avoid momentary false output. Derive the logic diagram of the circuit.

asked Apr 7 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 4 views

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Morris Mano Edition 3 Exercise 9 Question 4 (Page No. 392)
An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are as follows. $Y _1 = x _1x _2 + x _1y _2' + x _2'y _1$ ... Draw the logic diagram of the circuit. Derive the transition table and the output map. Obtain a flow table for the circuit.

asked Apr 7 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 6 views

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Morris Mano Edition 3 Exercise 9 Question 3 (Page No. 392)
an asynchronous circuit is described by the following excitation and output functions: $Y = x _1x _2’ + (x _1 + x _2’)y$ $z = y$ Draw the logic diagram of the circuit. Derive the transition table and the output map. obtain a two-state flow table. Describe in the words the behavior of the circuit.

asked Apr 7 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 5 views

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23

Morris Mano Edition 3 Exercise 9 Question 2 (Page No. 392)
Derive a transition table for the asynchronous sequential circuit given in the figure. Determine the sequence of the internal states $y _1Y _2$ for the following sequence of the input $x _1x _2$: 00,10,11,01,11,10,00.

asked Apr 7 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 4 views

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24

Morris Mano Edition 3 Exercise 9 Question 1 (Page No. 392)
Explain the difference between synchronous and asynchronous sequential circuits. Define fundamental mode operation. Explain the difference between stable and unstable states. what is the difference between an internal state or a total state?

asked Apr 7 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 5 views

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25

Morris Mano Edition 3 Exercise 7 Question 42 (Page No. 306)
It is necessary to formulate the hamming code for four data bits $D _3, D _5, D _6 and D _7$ together with three parity bits $P _1, P _2 and P _3$. evaluate the 7-bit composite code word for the data word 0010. Evaluate ... error detection in the code. Assume that error occurs in the bit $D _5 and P _2$. Show how the error is detected.

asked Apr 6 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 13 views

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Morris Mano Edition 3 Exercise 7 Question 41 (Page No. 306)
How many parity check bits must be included with the data word to achieve single-bit error correction and double error correction when data words are as follows: 16 bits 32 bits 48 bits

asked Apr 6 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 17 views

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27

Morris Mano Edition 3 Exercise 7 Question 40 (Page No. 306)
A 12-bit hamming code word 8-bits of data and 4 parity bits are read from the memory. What was the original 8-bit data word that was written into the memory if the 12-bits word read out are as follows: 000011101010 101110000110 101111110100

asked Apr 6 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 7 views

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28

Morris Mano Edition 3 Exercise 7 Question 39 (Page No. 305)
Given that 11-bit data word 11001001010, generate the 15-bit hamming code word.

asked Apr 6 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 5 views

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29

Morris Mano Edition 3 Exercise 7 Question 38 (Page No. 305)
Given the 8-bit data word 01011011, generate the 13-bit composite word for the Hamming code that corrects the single bit error and detects double bit errors.

asked Apr 6 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 13 views

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30

Morris Mano Edition 3 Exercise 7 Question 37 (Page No. 305)
An integrated circuit ram chip has a capacity of 1024 words of 8 bits each ($1K \times 8$) How many addresses and the data lines are there in the chips? How many chips are needed to construct a $16K \times 16$ ram? How many ... $1 \times 8$ chips? What are the input to the decoder and where are its output connected?

asked Apr 6 in Digital Logic by ajaysoni1924 Loyal (9.6k points) | 8 views

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