Recent questions tagged digital-logic

Recent questions tagged digital-logic

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1

ISI2021-PCB-C10
Suppose instead of a decoder with n input bits (n is even) to access a memory of size 2^n, one uses two decoders of input sizes k bits and (n-k) bits. Explain how these two decoders can be used to access the memory of size 2^N. ... address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.

jatin29 asked in Digital Logic May 3

25 views

0 votes

1 answer

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simplify the following logic functionf(ABC)USING k-MAP f(ABC)=(A+B+C') .(A+B'+C')

saba780 asked in Digital Logic Apr 26

41 views

0 votes

1 answer

3

How to find a range of float,double,long in c programming?
How to find a range of float,double,long in c programming? just like we find the range in case of int (signed,unsigned),char (signed ,unsigned) in c programming language ? like integer unsigned range is 0 to 65535 and so on for other data types ? Thank you ahead

ykrishnay asked in Programming Apr 23

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0 answers

4

How to convert (0.75) base 10 to base 5?
I have tried solving it using the following 0.75 × 5 = 3.75 3.75 × 5 = 18.75 18.75 × 5 = 93.75 But the answer is 0.33333.... I don't understand how did this happen... Please someone explain me

Sk Jamil Ahemad asked in Digital Logic Mar 23

by Sk Jamil Ahemad

63 views

2 votes

2 answers

5

GATE CSE 2022 | Question: 8
Let $\text{R1}$ and $\text{R2}$ be two $4 - \text{bit}$ registers that store numbers in $2\text{'s}$ complement form. For the operation $\text{R1 + R2},$ which one of the following values of $\text{R1}$ and $\text{R2}$ ... and $\text{R2 = 1010}$ $\text{R1 = 0011}$ and $\text{R2 = 0100}$ $\text{R1 = 1001}$ and $\text{R2 = 1111}$

Arjun asked in Digital Logic Feb 15

by Arjun

855 views

3 votes

1 answer

6

GATE CSE 2022 | Question: 30
Consider a digital display system $\text{(DDS)}$ shown in the figure that displays the contents of register $\text{X}.$ A $16 - \text{bit}$ code word is used to load a word in $\text{X},$ either from $\text{S}$ or from $\text{R}.$ $\text{S}$ is a $1024-$ ... $1:10$ de-multiplexer$; \quad \; \;\text{Q}$ is $1:5$ de-multiplexer$; \quad \text{T}$ is $2:1$ multiplexer

Arjun asked in Digital Logic Feb 15

by Arjun

479 views

1 vote

2 answers

7

GATE CSE 2022 | Question: 31
Consider three floating point numbers $\textit{A, B}$ and $\textit{C}$ stored in registers $\text{R}_{\text{A}}, \text{R}_{\text{B}}$ and $\text{R}_{\text{C}},$ respectively as per $\textsf{IEEE-754}$ single precision floating point format. The $\text{32-bit}$ content stored in ... $\textit{A + C} = 0$ $\textit{C = A + B}$ $\textit{B =3C}$ $\textit{(B - C)} > 0$

Arjun asked in Digital Logic Feb 15

by Arjun

592 views

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1 answer

8

CSE EXAM 2022
how to solve it

rsansiya111 asked in Digital Logic Feb 12

158 views

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0 answers

9

(Solved now) Gateoverflow test doubt
In https://gateoverflow.in/356090/Gate-overflow-mock-test-4-56 Aren't asynchronous flip-flops supposed to update output sequentially due to delay? I am getting answer Q0 Q1 as 11 → 00 → 10 → 01 → 11

o asked in Digital Logic Feb 2

by o

152 views

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0 answers

10

Morris Morin digital Logic Combinatioal Logic #GATE CSE
Using four half-adders (HDL—see Problem 4.52), (a) Design a full-subtractor circuit incrementer. (A circuit that adds one to a four-bit binary number.) (b)* Design a four-bit combinational decrementer (a circuit that subtracts 1 from a fourbit binary num

Ashit Verma asked in Digital Logic Jan 29

98 views

0 votes

1 answer

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BCD Correction | Made Easy Test Series
why is C incorrect? addition of any two nibbles such as 1000 1000 --------- 0000 Will generate a final carry as 1 0000, which will require the addition of 0110 as 1 0110 to make it correct.

palashbehra5 asked in Digital Logic Jan 29

by palashbehra5

106 views

0 votes

1 answer

12

Applied Gate Test Series : T-Flip and D flip flop with xor
Here At the time t0 the initial state is 00 and after first clock the state become 10 (Q1,Q0) here Q1 is clock to D flip – flop and because of that we are getting the output of d in next state/time so currently we output should remain 1 0 not become 1 1 at time 1 , but ans here is 1 1 , is anything i am during here is wrong?

niks77 asked in Digital Logic Jan 11

by niks77

182 views

0 votes

1 answer

13

DESIGN A COUNTER WITH THE FOLLOWING BINARY SEQUENCE 0,4,2,1,6 AND REPEAT. USE JK FLIP FLOP

Aman27104 asked in Digital Logic Jan 7

576 views

0 votes

0 answers

14

Made Easy Test Series Question
The output frequency of a decade counter that is clocked from a 50 kHz signal is _________ kHz.

prnv28 asked in Digital Logic Dec 31, 2021

by prnv28

299 views

0 votes

1 answer

15

gate book test series output waveform
Please post The solution.

Amit puri asked in Digital Logic Dec 23, 2021

168 views

0 votes

1 answer

16

Topic - Number Systems (Digital Logic)
What is the difference between 2’s complement and 2’s complement representation of a number? Please can you do 2’s complement of (43) and (-43) and also represent 43 and (-43) in two’s complement form. Also, write binary of 43 and (-43).

99Monish asked in Digital Logic Dec 18, 2021

233 views

0 votes

0 answers

17

#boolean algebra #ex-or #functionally complete

jayadev asked in Digital Logic Dec 16, 2021

79 views

1 vote

3 answers

18

Nptel Assignment Question
if 93 /4 = 23, the base of the number system is 8 9 10 11

rsansiya111 asked in Digital Logic Dec 2, 2021

254 views

1 vote

1 answer

19

Nptel Assignment Question
what is the decimal equivalent of ${{(1221)}}_{3}$ ${{(50)}}_{10}$ ${{(53)}}_{10}$ ${{(52)}}_{10}$ ${{(51)}}_{10}$

rsansiya111 asked in Digital Logic Dec 2, 2021

88 views

0 votes

1 answer

20

Made Easy Test Series
A 3 to 8 decoder is shown below: All output lines of decoder will be high when all the input I1, I2, I3 are; are high and G1 , G2 are low are high and G1 is high , G2 is low are high and G1 is low , G2 is high are high and G1 , G2 are high Please someone help to understand the logic behind this question. Why we have to disable the Decoder to make all the outputs high ?

Rajat Agrawal007 asked in Digital Logic Nov 23, 2021

by Rajat Agrawal007

153 views

1 vote

1 answer

21

Applied Test Series
The number of minterms in the function F is _______

LRU asked in Digital Logic Nov 2, 2021

by LRU

118 views

2 votes

2 answers

22

Applied Test Series
What will be the output ?

LRU asked in Digital Logic Oct 21, 2021

by LRU

189 views

3 votes

1 answer

23

Applied Test Series
The minimum number of literal obtained on simplifying the expression ABC + A’C + AB’C + A’BC are _______

LRU asked in Digital Logic Oct 21, 2021

by LRU

388 views

1 vote

1 answer

24

Gate applied test series 2022
Given 2 functions X and Y, we can say function X covers function Y iff all the minterms of function Y are covered by function X ( i.e X should be superset of Y). Let Y be a function of 3 ternary variables, Y(a,b) having 15 minterms. The number of functions covering Y are ______

anwesha-me asked in Digital Logic Oct 5, 2021

103 views

3 votes

1 answer

25

Digital design_Morris
Simplify the following function using Boolean algebra and design logic circuit using basic logic gates

r4kib asked in Digital Logic Sep 29, 2021

by r4kib

134 views

0 votes

0 answers

26

3 to 8 line Decoder (Combinational Circuit)
If F1 = ∑m(1,2,4,7) and F2 = ∑m(3,5,6,7), implement them using 3 to 8 line decoder. Comment on their logic operations.

gikovi asked in Digital Logic Sep 26, 2021

by gikovi

202 views

1 vote

1 answer

27

Logic Function
Why do we use Canonical form in logic circuits? What is the need for minterm and max term?

Subhadeeppathak asked in Digital Logic Sep 16, 2021

by Subhadeeppathak

160 views

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