Recent questions tagged digital-logic

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1

Made Easy Test Series
A 3*8 decoder with 2 enable inputs is to be used to address 8 blocks of memory. what will be the size of each of memory block when addressed from a 16-bit bus with 2 MSBs to enable decoder. given answer: 2K My answer: 16K approach: since 2 MSBs are ... thing we can find out is the number of memory addresses . which will be 2^14.=16K. please tell me where have i gone wrong?

asked 15 hours ago in Digital Logic by aambazinga Active (2.1k points) | 19 views

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previous
https://gateoverflow.in/17235/gate1993-6-2 Explanation is not provided in the answer. Can anyone please give explanation for the answer.

asked 23 hours ago in Digital Logic by Swapnil Naik Active (2.3k points) | 22 views

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ME-FT1 JK flip-flop
The input to the LED is connected to the output $\overline{Q}$ of the master slave flip-flop. The duration for which the LED will be ON in the time duration of T is _____ sec.

asked 1 day ago in Digital Logic by Mk Utkarsh Boss (29.7k points) | 45 views

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4

GATE ECE digital logic
A 16-bit ripple carry adder is realized using 16 identical full adders (FA) as shown in the figure. The carry-propagation delay of each FA is 12 ns and the sum propagation delay of each FA is 15 ns. The worst case delay (in ns) of this 16-bit adder will be __________

asked 4 days ago in Digital Logic by aditi19 Active (2.1k points) | 23 views

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#TarGATE
The MOD value (or) number of states in the ripple counter as shown in the figure is? Answer given: Mod 7 counter. My doubt is that won't it go till 111 and then the counter is cleared as the input to NAND gate is taken from the output of the flipflops?

asked 4 days ago in Digital Logic by Parth Shah (363 points) | 12 views

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#TarGATE
The circuit shown in figure is using one 4-bit BCD counter and one 4-bit binary counter. The MOD value for the counter is ?

asked 4 days ago in Digital Logic by Parth Shah (363 points) | 17 views

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7

Digital Electronics: Minterms & Maxterms

asked Dec 8 in Digital Logic by chauhansunil20th Active (1.9k points) | 41 views

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Sequential Circuit
The delay of NAND and Not gate is 3 and 1ns respectively. And counter is assumed to be 0. If the clock frequency is 500 MHZ,then counter behave as Mod 5 counter Mod 7 counter Mod 6 Counter None

asked Dec 8 in Digital Logic by Na462 Loyal (7.5k points) | 24 views

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9

Kohavi
A certain 4 input gate called LEMON gate realizes the switching function LEMON(A,B,C,D) = BC(A+D) Assuming that the input variables are available in both primed and unprimed form: i. show a realization of the function f(w,x,y,z)= P(0,1,6,9,10,11,14,15) with only three LEMON gates and one OR gate.

asked Dec 8 in Digital Logic by RahulRoy31 (217 points) | 12 views

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Nielit STA 2018
Minimum number of Full adders and half adders required by the BCD adder to add two decimal digits.

asked Dec 5 in Digital Logic by Robert Soram (41 points) | 26 views

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11

GATE ECE 2014
Above question modification. This is the actual question Boolean expression$:(x+y)(x+\bar{y})+\overline{{(x\bar{y}+\bar{x})}}$ $(A) x$ $(B)y$ $(C)xy$ $(D)x+y$

asked Dec 4 in Digital Logic by aditi19 Active (2.1k points) | 39 views

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12

Minimum number of Flip Flops required
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN, GREEN to RED. In each cycle RED is turned on for 100 seconds,YELLOW is turned on for 40 seconds and GREEN is turned on for 80 seconds. The traffic signal has to be implemented ... only input to FSM is clock of 10 seconds period.The minimum number of Flip Flops required to implement this FSM is .

asked Dec 2 in Digital Logic by Na462 Loyal (7.5k points) | 20 views

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13

Digital systems- need help building a 4 bit subtractor

asked Dec 2 in Digital Logic by joshsept (7 points) | 19 views

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14

IEEE 754 Implicit and Explicit 1 Representation

asked Dec 1 in CO & Architecture by Shubhanshu Boss (17k points) | 34 views

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15

Complementary Number Systems
If N = 670 in base 9 system. Then find the radix complement of N.

asked Nov 28 in Digital Logic by saptarshiDey (37 points) | 36 views

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GATE-ECE-2016
answer is 6 but I’m getting 5(delay of NOR gate+delay of 1st MUX+delay of 2nd MUX)=2+1.5+1.5=5 ns where is extra 1 ns delay coming from?

asked Nov 25 in Digital Logic by aditi19 Active (2.1k points) | 52 views

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1 answer

17

Floating point
Consider the following bit pattern represents the floating point number in IEEE 754 single precision format: 1 10000111 11100000000000000000000 Which of the following represents the decimal value of above floating number? A) -192 B) -320 C) -384 D) -448

asked Nov 24 in Digital Logic by kapilbk1996 (407 points) | 79 views

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18

Morris Mano
Implement the function using PLA

asked Nov 22 in Digital Logic by kd..... (481 points) | 22 views

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19

GATE-ECE-2017
answer is D but I'm getting A. pls tell where am I going wrong?

asked Nov 20 in Digital Logic by aditi19 Active (2.1k points) | 63 views

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20

digital logic
....

asked Nov 19 in Digital Logic by Gurdeep Saini Active (5.2k points) | 48 views

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1 answer

21

GB DL - Test 1 - Question 19
If decimal value of is less than that of then possible values of x and y in octal number system respectively are: (A) 11, 16 (B) 15, 9 (C) 9, 12 (D) 17, 11

asked Nov 19 in Digital Logic by Sandy Sharma Active (1.1k points) | 47 views

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22

GB DL - Test 1 - Question 16
The gray code for a decimal number N is . This number N is converted into P which belongs to 84 − 2 − 1 code system. What is the Hexadecimal representation for P? (A) ABC (B) F55 (C) 170 (D) 790

asked Nov 19 in Programming by Sandy Sharma Active (1.1k points) | 42 views

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23

GB DL - Test 1 - Question 7
The Gray code representation of 11710 is: (A) 1111001 (B) 1001111 (C) 1110110 (D) 1110101

asked Nov 19 in Digital Logic by Sandy Sharma Active (1.1k points) | 52 views

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24

Self doubt
Once we have assumed a don't care as '1' in SOP we can't use the same don't care for grouping zeros in POS and vice versa. Whether this statement is true or false.

asked Nov 16 in Digital Logic by Nivedita Singh (25 points) | 32 views

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25

Functional Completeness Doubt
Is Ex-NOR functionally complete? pls explain in details

asked Nov 16 in Digital Logic by aditi19 Active (2.1k points) | 22 views

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26

Boolean logic implementation

asked Nov 16 in Digital Logic by Na462 Loyal (7.5k points) | 53 views

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27

Boolean logic

asked Nov 16 in Digital Logic by Na462 Loyal (7.5k points) | 39 views

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1 answer

28

Full adder

asked Nov 15 in Digital Logic by Na462 Loyal (7.5k points) | 45 views

+1 vote

1 answer

29

Made Easy Test Series

asked Nov 15 in Digital Logic by Shamim Ahmed Active (1k points) | 62 views

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30

GATE-ECE-2018
Consider a binary channel code in which each codeword has a fixed length of 5 bits. The Hamming distance between any pair of distinct codewords in this code is at least 2. The maximum number of codewords such a code can contain is _________.

asked Nov 14 in Digital Logic by aditi19 Active (2.1k points) | 87 views

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