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Recent questions tagged digital-logic
0
votes
1
answer
1
Digital Logic Question
rsansiya111
asked
in
Digital Logic
10 hours
ago
by
rsansiya111
25
views
digital-logic
flip-flop
sequential-circuit
0
votes
0
answers
2
Digital Logic Question
Consider the following statements regarding the logic circuits: 1. In combinational logic circuits, the outputs at any instant of time are entirely dependent upon the inputs present at that time. 2. The behavior of synchronous sequential circuit depends upon the order in which its input signals change and ... ? (a) 1, 2 and 3 (b) 1 and 2 only (c) 2 and 3 only (d) 1 and 3 only
rsansiya111
asked
in
Digital Logic
10 hours
ago
by
rsansiya111
13
views
digital-logic
combinational-circuit
sequential-circuit
0
votes
0
answers
3
Digital Logic
To design n input NOR gate, the number of 2 input NOR gate =2n - 3. Somebody please verify and explain with example ( diagram).
GateOverflow04
asked
in
Digital Logic
Sep 22
by
GateOverflow04
46
views
digital-logic
self-doubt
0
votes
1
answer
4
Digital Logic | Doubt
Hamming Distance: We can calculate how much Hamming Distance should be there so that we can correct any wrong bit Hamming Code: By Hamming Code we can correct any wrong bit. Questions: 1] Are they both different techniques or there is relation ... Hamming Distance in any two numbers). 2] Why should anybody use Hamming Code where we can correct error by Hamming Distance?
anupamsworld
asked
in
Digital Logic
Sep 18
by
anupamsworld
41
views
digital-logic
hamming-code
0
votes
1
answer
5
Applied test series question
A 4-bit carry lookahead adder adds two 4-bit numbers. The adder is designed without making use of the EX-OR gates. The propagation delay for all gates is given as 2.4 time units. What will be the overall delay of adder if we assume that inputs ... AND, Or gates. can someone explain me this in a deatiled manner as i am not able to find the appropriate solution for it ?
shikhar500
asked
in
Digital Logic
Sep 14
by
shikhar500
83
views
test-series
digital-logic
adder
0
votes
1
answer
6
Computer architecture
Represent +42 and -42 in sign-magnitude, 1’s complement and 2’s complement representation. Find the result of 42 - 20 using 2’s complement.
Karthi2003
asked
in
Digital Logic
Sep 11
by
Karthi2003
63
views
digital-logic
number-representation
0
votes
0
answers
7
Number representation
Does the formula(2^(k-1)) used for caculating the biasing value is correct?
GateOverflow04
asked
in
Digital Logic
Sep 3
by
GateOverflow04
49
views
digital-logic
ace-test-series
number-representation
0
votes
1
answer
8
Computer Architecture and Organisation
1. Assume a Bus System constructed to connect 7 registers and memory unit of 32 word length using multiplexer. So: a) How many multiplexer is needed? b) What type of multiplexer is required i.e size of multiplexer? c) Describe decoder used to select address of memory unit
kidussss
asked
in
CO and Architecture
Sep 1
by
kidussss
34
views
co-and-architecture
memory-interfacing
branch-conditional-instructions
reference-book
digital-logic
0
votes
0
answers
9
#gate #digital logic #neutral function #derivation
How formula of neutral function is derived? I get that it has equal number of max and min terms but didnt get derivation
Aditi Thakur
asked
in
Digital Logic
Aug 24
by
Aditi Thakur
71
views
digital-logic
neutral-function
0
votes
0
answers
10
Made easy 2022 Test Series
Please Explain How to Solve this type question in detail if any source Please share.
Amit Mehta
asked
in
Digital Logic
Aug 9
by
Amit Mehta
111
views
digital-logic
1
vote
1
answer
11
ISI2020-PCB-CS: 8.1
Simplify the following Boolean function in product-of-sums form: $ F(A, B, C, D)=\sum(0,1,2,5,8,9,10) . $
Lakshman Patel RJIT
asked
in
Digital Logic
Aug 8
by
Lakshman Patel RJIT
74
views
isi2020-pcb-cs
descriptive
digital-logic
boolean-algebra
0
votes
0
answers
12
ISI2020-PCB-CS: 10
Suppose instead of a decoder with $n$ input bits ( $n$ is even) to access a memory of size $2^{n}$, one uses two decoders of input sizes $k$ bits and $(n-k)$ bits. Explain how these two decoders can be used to access the ... address decoding time. Justify your answer. Assume that the time complexity of the decoder is measured by the number of output lines of that decoder.
Lakshman Patel RJIT
asked
in
Digital Logic
Aug 8
by
Lakshman Patel RJIT
26
views
isi2020-pcb-cs
digital-logic
combinational-circuit
decoder
descriptive
0
votes
0
answers
13
Digital Logic - Gray Code Representation
Hi, Can someone please tell if gray code representation can also work for negative binary number? I’ve seen examples of gray code for only positive binary number not sure about negative , can someone pls clear the doubt ?
krish71
asked
in
Digital Logic
Aug 1
by
krish71
84
views
digital-logic
binary-codes
general-topic-doubt
1
vote
1
answer
14
Floating point representation
What is the 16 bits pattern which represent (-13.5) in normalized signed magnitude fraction . S = 1 bit , Exponent = 7 bits , Mantissa = 8 bits . Represent it in hexadecimal also.
Manisha Jaishwal
asked
in
Digital Logic
Jul 16
by
Manisha Jaishwal
151
views
digital-logic
floating-point-representation
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