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Recent questions tagged digitallogic
Webpage for Digital Logic:
+2
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1
answer
1
ISRO202066
The following circuit compares two $2$bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bits) Under what conditions $Z$ will be $1$? $X>Y$ $X<Y$ $X=Y$ $X!=Y$
asked
Jan 13
in
Digital Logic
by
Satbir
Boss
(
23.8k
points)

225
views
isro2020
digitallogic
digitalcircuits
normal
+1
vote
1
answer
2
ISRO202052
To send same bit sequence, NRZ encoding require Same clock frequency as Manchester encoding Half the clock frequency as Manchester encoding Twice the clock frequency as Manchester encoding A clock frequency which depends on number of zeroes and ones in the bit sequence
asked
Jan 13
in
Digital Logic
by
Satbir
Boss
(
23.8k
points)

115
views
isro2020
digitallogic
normal
+1
vote
1
answer
3
ISRO202080
A new flipflop with inputs $X$ and $Y$ ... $(X\wedge \overline{Q })\vee (Y \wedge Q)$ $(X\wedge \overline{Q })\vee (\overline{Y } \wedge Q)$
asked
Jan 13
in
Digital Logic
by
Satbir
Boss
(
23.8k
points)

109
views
isro2020
digitallogic
sequentialcircuit
flipflop
normal
+2
votes
2
answers
4
ISRO202012
If $ABCD$ is a $4$bit binary number, then what is the code generated by the following circuit? BCD code $8421$ code Gray code Excess$3$ code
asked
Jan 13
in
Digital Logic
by
Satbir
Boss
(
23.8k
points)

141
views
isro2020
digitallogic
combinationalcircuits
normal
+1
vote
1
answer
5
ISRO202011
Minimum number of NAND gates required to implement the following binary equation $Y = (\bar{A}+\bar{B})(C+D)$ $4$ $5$ $3$ $6$
asked
Jan 13
in
Digital Logic
by
Satbir
Boss
(
23.8k
points)

151
views
isro2020
digitallogic
combinationalcircuits
normal
+1
vote
2
answers
6
ISRO202077
Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\bar{E}+\bar{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
asked
Jan 13
in
Digital Logic
by
Satbir
Boss
(
23.8k
points)

131
views
isro2020
digitallogic
combinationalcircuits
normal
+1
vote
1
answer
7
ISRO202010
Following Multiplexer circuit is equivalent to Sum equation of full adder Carry equation of full adder Borrow equation for full subtractor Difference equation of a full subtractor
asked
Jan 13
in
Digital Logic
by
Satbir
Boss
(
23.8k
points)

120
views
isro2020
digitallogic
combinationalcircuits
normal
+1
vote
1
answer
8
ISRO20209
In a $8$bit ripple carry adder using identical full adders, each full adder takes $34$ns for computing sum. If the time taken for $8$bit addition is $90$ ns, find time taken by each full adder to find carry. $6$ ns $7$ ns $10$ ns $8$ ns
asked
Jan 13
in
Digital Logic
by
Satbir
Boss
(
23.8k
points)

108
views
isro2020
digitallogic
combinationalcircuits
normal
+2
votes
3
answers
9
ISI2017DCG10
The value of the Boolean expression (with usual definitions) $(A’BC’)’ +(AB’C)’$ is $0$ $1$ $A$ $BC$
asked
Sep 18, 2019
in
Digital Logic
by
gatecse
Boss
(
17.5k
points)

116
views
isi2017dcg
digitallogic
booleanalgebra
booleanexpression
+3
votes
1
answer
10
Digital logic nptel assignment
Suppose we are using 4bit carry lookahead adder modules to build a 64 bit adder with twolevel carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worstcase delay of the 64bit adder will be ……….. nanoseconds.
asked
Aug 13, 2019
in
Digital Logic
by
ajaysoni1924
Boss
(
10.8k
points)

203
views
nptelquiz
digitallogic
+2
votes
1
answer
11
Logic Gates and switching circuits
The gates G1 & G2 in the figure have propagation delays of 10ns and 20ns respectively. If the input Vi makes an abrupt change from logic 0 to 1 at time t=t0 , then what's the output waveform V0 is ? Also please explain how to handle such kinds of questions of waveform?
asked
Jun 14, 2019
in
Digital Logic
by
Gitika Babbar
(
157
points)

278
views
digitallogic
digitalcircuits
0
votes
4
answers
12
Minimization doubt in DIGITAL LOGIC
asked
Jun 14, 2019
in
Digital Logic
by
Gitika Babbar
(
157
points)

118
views
digitallogic
kmap
digitalcircuits
0
votes
2
answers
13
Gray Code (Self Doubt)
Was solving the GO 2019 pdf when I encountered this question asked in TIFR 2017. Although I have understood this question, I have one doubt It is mentioned in the question that for a 3bit number, the ordering (000, 100, 101, 111, 110, 010, 011, 001) is one of the possible Gray codes. Then, how many such orders are there for an nbit number?
asked
Jun 13, 2019
in
Digital Logic
by
Debargha Bhattacharj
Junior
(
831
points)

142
views
digitallogic
graycode
usertifr2017
usermod
0
votes
0
answers
14
MADE EASY ELECTRONICS
The number of Essential Prime implicants are ______________.
asked
May 25, 2019
in
Digital Logic
by
Hirak
Active
(
3.6k
points)

125
views
digitallogic
primeimplicants
0
votes
1
answer
15
carry look ahead adder vs ripple carry
$ExclusiveOR$ gate has a propagation delay of $10$ ns and that the $AND$ or $OR$ gates have a propagation delay of $5$ ns.What is the total propagation delay time in the fourbit adder.Assume $FANIN =2$ $1)$ ripple adder $2)$ carry look ahead adder
asked
May 16, 2019
in
Digital Logic
by
val_pro20
Active
(
1.2k
points)

129
views
digitallogic
+1
vote
1
answer
16
Made Easy Test Series:FlipFlop
A Finite State Machine(FSM) is implemented using the DFFs A and B with logic gates as shown below. The four possible states of FSM are $Q_{A}Q_{B}=00,01,10,11$. Assume that $X_{in}$ is held at constant logic level throughout the operation of FSM. ... states if $X_{in}=0$ How do we check $X_{in}$ here? Can we check it arbitrarily, or checked with prev states??
asked
May 16, 2019
in
Digital Logic
by
srestha
Veteran
(
118k
points)

119
views
digitallogic
flipflop
madeeasytestseries
+3
votes
3
answers
17
GateBook Test Series: Digital Logic  Boolean Algebra
What is the time complexity for checking whether an assignment of truth values to variables $x_1,\dots ,x_n$ satisfies a given formula $f(x_1\dots,x_n)$? $O(2^n)$ $O(g(n))$ where $g$ is a polynomial $O(log(n))$ None of the above
asked
May 15, 2019
in
Digital Logic
by
val_pro20
Active
(
1.2k
points)

249
views
gatebook
digitallogic
booleanalgebra
0
votes
1
answer
18
Made Easy Test Series: Digital Logic Master Slave FF
$1)$ MasterSlave FF is designed to avoid race around condition $2)$ MasterSlave FF is used to store $2$ bit information Which of the following statement is correct? What is meaning of $2bit $ information??
asked
May 15, 2019
in
Digital Logic
by
srestha
Veteran
(
118k
points)

152
views
digitallogic
madeeasytestseries
flipflop
+1
vote
2
answers
19
Made Easy Test Series: Digital Logic
A $3\times 8$ decoder with $2$ enable inputs is used to address $8$ block of memory. What will be the size of each memory block when addressed from a $16$ bit bus with $2$ MSB’s used to enable the decoder?
asked
May 15, 2019
in
Digital Logic
by
srestha
Veteran
(
118k
points)

136
views
digitallogic
madeeasytestseries
decoder
+2
votes
1
answer
20
Boolean algebradigital logic
$(a) A = 101010$ and $B = 011101$ are $1’s$ complement numbers. Perform the following operations and indicate whether overflow occurs. $(i) A + B$ $(ii) A − B$ $(b)$ Repeat part $(a)$ assuming the numbers are $2’s$ complement numbers.
asked
May 11, 2019
in
Digital Logic
by
val_pro20
Active
(
1.2k
points)

130
views
digitallogic
booleanalgebra
0
votes
1
answer
21
BOOLEAN FUNCTION (Morris Mano)
asked
May 6, 2019
in
Digital Logic
by
altamash
(
445
points)

56
views
digitallogic
+2
votes
4
answers
22
Boolean algebra expression Floyd Digital Logic
Simplify the following expression AB’C + A’BC + A’B’C Solution given is A’C + B’C can someone show me how?
asked
May 2, 2019
in
Digital Logic
by
vupadhayayx86
Active
(
1.7k
points)

203
views
digitallogic
booleanalgebra
0
votes
1
answer
23
Test Book digital logic
I think option A is also correct ! if we take minterm and complement it to get POS then option A can also be the answer
asked
Apr 9, 2019
in
Digital Logic
by
Shawn Frost
(
31
points)

81
views
digitallogic
logic
0
votes
0
answers
24
Morris Mano Edition 3 Exercise 9 Question 24 (Page No. 396)
The boolean functions for the input of SR latch are as follows. Obtain the circuit diagram using a minimum number of NAND gates. $S = x _1’x _2’x _3 + x _1x _2x _3$. $R = x _1x _2’ + x _2x _3’$
asked
Apr 8, 2019
in
Digital Logic
by
ajaysoni1924
Boss
(
10.8k
points)

54
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
minnogates
0
votes
0
answers
25
Morris Mano Edition 3 Exercise 9 Question 23 (Page No. 396)
Draw the logic diagram of the product of sum expression $ Y = (x _1 + x _2’)(x _2 + x _3)$ Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero and $x _2$ goes from 0 to 1.Find a way to remove hazard by adding one more OR gate.
asked
Apr 8, 2019
in
Digital Logic
by
ajaysoni1924
Boss
(
10.8k
points)

27
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
hazards
0
votes
0
answers
26
Morris Mano Edition 3 Exercise 9 Question 22 (Page No. 396)
Find a circuit that has no static hazard and implements the boolean function: F(A,B,C,D) = $\sum(0,2,6,7,8,10,12)$
asked
Apr 8, 2019
in
Digital Logic
by
ajaysoni1924
Boss
(
10.8k
points)

34
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
hazards
0
votes
0
answers
27
Morris Mano Edition 3 Exercise 9 Question 18 (Page No. 395)
Merge each of the primitive flow table shown in the figure. Proceed as follows: Find all compatible pairs by means of implication table. Find the maximal compatibles by means of a merger diagram FInd the minimal set of compatibles that covers all the states and is closed.
asked
Apr 8, 2019
in
Digital Logic
by
ajaysoni1924
Boss
(
10.8k
points)

33
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
28
Morris Mano Edition 3 Exercise 9 Question 17 (Page No. 395)
Reduce the number of states in the state table listed below. Use an implication table.
asked
Apr 8, 2019
in
Digital Logic
by
ajaysoni1924
Boss
(
10.8k
points)

22
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
29
Morris Mano Edition 3 Exercise 9 Question 16 (Page No. 395)
Using the implication table method, show that the state table listed in the figure cannot be reduced any further.
asked
Apr 8, 2019
in
Digital Logic
by
ajaysoni1924
Boss
(
10.8k
points)

24
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
30
Morris Mano Edition 3 Exercise 9 Question 15 (Page No. 395)
Assign output values to the don’t care states in the flow tables in the figure below in such a way as to avoid transient output places
asked
Apr 8, 2019
in
Digital Logic
by
ajaysoni1924
Boss
(
10.8k
points)

13
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
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