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Recent questions tagged digital-logic

0 votes
1 answer
1
The period of a signal is $100$ ms, then the frequency of this signal in kilohertz is ______ $10$ $10^{-1}$ $10^{-2}$ $10^{-3}$
asked Nov 20, 2020 in Digital Logic jothee 107 views
0 votes
2 answers
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Simplified expression/s for following Boolean function $F(A,B,C,D)=\Sigma(0,1,2,3,6,12,13,14,15)$ is/are $A’B’+AB+A’C’D’$ $A’B’+AB+A’CD’$ $A’B’+AB+BC’D’$ $A’B’+AB+BCD’$ Choose the correct answer from the options given below: $(a)$ only $(b)$ only $(a)$ and $(b)$ only $(b)$ and $(d)$ only
asked Nov 20, 2020 in Digital Logic jothee 121 views
1 vote
1 answer
3
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
asked Aug 28, 2020 in Digital Logic Lakshman Patel RJIT 774 views
0 votes
3 answers
4
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28, 2020 in Digital Logic Lakshman Patel RJIT 262 views
0 votes
1 answer
5
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
asked Aug 28, 2020 in Digital Logic Lakshman Patel RJIT 237 views
0 votes
0 answers
6
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
asked Aug 28, 2020 in Digital Logic Lakshman Patel RJIT 142 views
0 votes
1 answer
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1 vote
1 answer
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A sequential circuit outputs a $\text{ONE}$ when an even number$(>0)$ of one’s are input; otherwise the output is $\text{ZERO}.$ The minimum number of states required is $0$ $1$ $2$ $3$
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 255 views
0 votes
2 answers
9
If a clock with time period $“T”$ is used with $n$ stage shift register, then output of final stage will be delayed by $nT$ sec $(n-1)T$ sec $n/T$ sec $(2n-1)T$ sec
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 192 views
0 votes
1 answer
10
If the input $\text{J}$ is connected through $\text{K}$ input of $\text{J-K}$, then flip-flop will behave as a D type flip-flop T type flip-flop S-R flip-flop Toggle switch
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 106 views
0 votes
1 answer
11
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Which of the following conditions must be met to avoid race around problem? $\Delta t< t_{p}< T$ $T>\Delta t> t_{p}$ $2t_{p}< \Delta t< T$ none of these
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 121 views
0 votes
1 answer
13
The excess $3$ code is also called cyclic redundancy code weighted code self complimenting code algebraic code
asked Apr 2, 2020 in Digital Logic Lakshman Patel RJIT 121 views
1 vote
2 answers
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2 answers
15
1 vote
1 answer
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1 answer
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In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip-flops Clock input of one flip-flop
asked Apr 1, 2020 in Digital Logic Lakshman Patel RJIT 118 views
0 votes
1 answer
19
0 votes
2 answers
20
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip flops Clock input of one flip-flop
asked Apr 1, 2020 in Digital Logic Lakshman Patel RJIT 173 views
0 votes
1 answer
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