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Recent questions tagged digital-logic

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Recent questions tagged digital-logic

0 votes
1 answer
1
UGCNET-Jan2017-II: 7
ECL is the fastest of all logic families. High speed in ECL is possible because transistors are used in difference amplifier configuration, in which they are never driven into ________. Race condition Saturation Delay High impedance
ECL is the fastest of all logic families. High speed in ECL is possible because transistors are used in difference amplifier configuration, in which they are never driven into ________. Race condition Saturation Delay High impedance
asked Mar 24 in Digital Logic jothee 58 views
0 votes
1 answer
2
UGCNET-Jan2017-II: 8
A binary $3$-bit down counter uses $J$-$K$ flip-flops, $FF_{i}$ with inputs $J_{i}$, $K_{i}$ and outputs $Q_{i}$, $i$ = $0, 1, 2$ respectively. The minimized expression for the input from following is : $J_{0} = K_{0} = 0$ $J_{0} = K_{0} = 1$ $J_{1} = K_{1} = Q_{0}$ ... $J_{2} = K_{2} =\overline{Q}_{1} \overline{Q}_{0}$ I, III, V I, IV, VI II, III, V II, IV, VI
A binary $3$-bit down counter uses $J$-$K$ flip-flops, $FF_{i}$ with inputs $J_{i}$, $K_{i}$ and outputs $Q_{i}$, $i$ = $0, 1, 2$ respectively. The minimized expression for the input from following is : $J_{0} = K_{0} = 0$ $J_{0} = K_{0} = 1$ $J_{1} = K_{1} = Q_{0}$ ... $J_{2} = K_{2} =\overline{Q}_{1} \overline{Q}_{0}$ I, III, V I, IV, VI II, III, V II, IV, VI
asked Mar 24 in Digital Logic jothee 72 views
0 votes
3 answers
3
UGCNET-Jan2017-II: 9
Convert the octal number $0.4051$ into its equivalent decimal number. $0.5100098$ $0.2096$ $0.52$ $0.4192$
Convert the octal number $0.4051$ into its equivalent decimal number. $0.5100098$ $0.2096$ $0.52$ $0.4192$
asked Mar 24 in Digital Logic jothee 64 views
0 votes
3 answers
4
UGCNET-Jan2017-II: 10
The hexadecimal equivalent of the octal number $2357$ is : $2EE$ $2FF$ $4EF$ $4FE$
The hexadecimal equivalent of the octal number $2357$ is : $2EE$ $2FF$ $4EF$ $4FE$
asked Mar 24 in Digital Logic jothee 72 views
0 votes
1 answer
5
UGCNET-Jan2017-II: 15
If $X$ is a binary number which is power of $2$, then the value of $X \& (X-1)$ is : $11\dots11$ $00\dots00$ $100\dots0$ $000\dots1$
If $X$ is a binary number which is power of $2$, then the value of $X \& (X-1)$ is : $11\dots11$ $00\dots00$ $100\dots0$ $000\dots1$
asked Mar 24 in Digital Logic jothee 50 views
4 votes
3 answers
6
GATE2020-CS-19
A multiplexer is placed between a group of $32$ registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is ______.
A multiplexer is placed between a group of $32$ registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is ______.
asked Feb 12 in Digital Logic Arjun 1.3k views
4 votes
4 answers
7
GATE2020-CS-20
If there are $m$ input lines $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .
If there are $m$ input lines $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .
asked Feb 12 in Digital Logic Arjun 1.7k views
3 votes
3 answers
8
GATE2020-CS-28
Consider the Boolean function $z(a,b,c)$. Which one of the following minterm lists represents the circuit given above? $z=\sum (0,1,3,7)$ $z=\sum (1,4,5,6,7)$ $z=\sum (2,4,5,6,7)$ $z=\sum (2,3,5)$
Consider the Boolean function $z(a,b,c)$. Which one of the following minterm lists represents the circuit given above? $z=\sum (0,1,3,7)$ $z=\sum (1,4,5,6,7)$ $z=\sum (2,4,5,6,7)$ $z=\sum (2,3,5)$
asked Feb 12 in Digital Logic Arjun 1.2k views
7 votes
6 answers
9
GATE2020-CS-29
Consider three registers $R1$, $R2$, and $R3$ that store numbers in $IEEE-754$ single precision floating point format. Assume that $R1$ and $R2$ contain the values (in hexadecimal notation) $0x42200000$ and $0xC1200000$, respectively. If $R3=\frac{R1}{R2}$, what is the value stored in $R3$? $0x40800000$ $0xC0800000$ $0x83400000$ $0xC8500000$
Consider three registers $R1$, $R2$, and $R3$ that store numbers in $IEEE-754$ single precision floating point format. Assume that $R1$ and $R2$ contain the values (in hexadecimal notation) $0x42200000$ and $0xC1200000$, respectively. If $R3=\frac{R1}{R2}$, what is the value stored in $R3$? $0x40800000$ $0xC0800000$ $0x83400000$ $0xC8500000$
asked Feb 12 in CO and Architecture Arjun 1.8k views
1 vote
1 answer
10
TIFR2020-B-3
Consider the (decimal) number $182$, whose binary representation is $10110110$. How many positive integers are there in the following set?$\{n\in \mathbb{N}: n\leq 182 \text{ and n has } \textit{exactly four} \text{ ones in its binary representation}\}$ $91$ $70$ $54$ $35$ $27$
Consider the (decimal) number $182$, whose binary representation is $10110110$. How many positive integers are there in the following set?$\{n\in \mathbb{N}: n\leq 182 \text{ and n has } \textit{exactly four} \text{ ones in its binary representation}\}$ $91$ $70$ $54$ $35$ $27$
asked Feb 11 in Digital Logic Lakshman Patel RJIT 149 views
3 votes
2 answers
11
ISRO2020-66
The following circuit compares two $2$-bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bits) Under what conditions $Z$ will be $1$? $X>Y$ $X<Y$ $X=Y$ $X!=Y$
The following circuit compares two $2$-bit binary numbers, $X$ and $Y$ represented by $X_1X_0$ and $Y_1Y_0$ respectively. ($X_0$ and $Y_0$ represent Least Significant Bits) Under what conditions $Z$ will be $1$? $X>Y$ $X<Y$ $X=Y$ $X!=Y$
asked Jan 13 in Digital Logic Satbir 594 views
1 vote
2 answers
12
ISRO2020-52
To send same bit sequence, $\text{NRZ}$ encoding require Same clock frequency as Manchester encoding Half the clock frequency as Manchester encoding Twice the clock frequency as Manchester encoding A clock frequency which depend on number of zeroes and ones in the bit sequence
To send same bit sequence, $\text{NRZ}$ encoding require Same clock frequency as Manchester encoding Half the clock frequency as Manchester encoding Twice the clock frequency as Manchester encoding A clock frequency which depend on number of zeroes and ones in the bit sequence
asked Jan 13 in Digital Logic Satbir 378 views
1 vote
1 answer
13
ISRO2020-80
A new flipflop with inputs $X$ and $Y$ ... $(X\wedge \overline{Q })\vee (Y \wedge Q)$ $(X\wedge \overline{Q })\vee (\overline{Y } \wedge Q)$
A new flipflop with inputs $X$ and $Y$, has the following property $\begin{array}{|c|c|c|}\hline \bf{X}& \bf{Y}& \bf{Current\ state}&\bf{ Next\ state} \\\hline 0&0&Q&1 \\ 0&1&Q&\overline{Q}\\ 1& 1&Q&0 \\ 1&0&Q&Q \\ \hline \end{array}$ Which of the following expresses the next ... $(X\wedge \overline{Q })\vee (Y \wedge Q)$ $(X\wedge \overline{Q })\vee (\overline{Y } \wedge Q)$
asked Jan 13 in Digital Logic Satbir 336 views
3 votes
3 answers
14
ISRO2020-12
If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit? BCD code Gray code $8421$ code Excess-$3$ code
If $ABCD$ is a $4$-bit binary number, then what is the code generated by the following circuit? BCD code Gray code $8421$ code Excess-$3$ code
asked Jan 13 in Digital Logic Satbir 374 views
1 vote
2 answers
15
ISRO2020-11
Minimum number of NAND gates required to implement the following binary equation $Y = (\overline{A}+\overline{B})(C+D)$ $4$ $5$ $3$ $6$
Minimum number of NAND gates required to implement the following binary equation $Y = (\overline{A}+\overline{B})(C+D)$ $4$ $5$ $3$ $6$
asked Jan 13 in Digital Logic Satbir 472 views
1 vote
3 answers
16
ISRO2020-77
Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\overline{E}+\overline{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
Consider the following circuit The function by the network above is $\overline{AB}E+EF+\overline{CD}F$ $(\overline{E}+AB\overline{F})(C+D+\overline{F})$ $(\overline{AB}+E)(\overline{E}+\overline{F})(C+D+\overline{F})$ $(A+B)\overline{E} +\overline{EF}+CD\overline{F}$
asked Jan 13 in Digital Logic Satbir 343 views
1 vote
2 answers
17
ISRO2020-10
Following Multiplexer circuit is equivalent to Sum equation of full adder Carry equation of full adder Borrow equation for full subtractor Difference equation of a full subtractor
Following Multiplexer circuit is equivalent to Sum equation of full adder Carry equation of full adder Borrow equation for full subtractor Difference equation of a full subtractor
asked Jan 13 in Digital Logic Satbir 361 views
1 vote
2 answers
18
ISRO2020-9
In a $8$-bit ripple carry adder using identical full adders, each full adder takes $34$ ns for computing sum. If the time taken for $8$-bit addition is $90$ ns, find time taken by each full adder to find carry. $6$ ns $7$ ns $10$ ns $8$ ns
In a $8$-bit ripple carry adder using identical full adders, each full adder takes $34$ ns for computing sum. If the time taken for $8$-bit addition is $90$ ns, find time taken by each full adder to find carry. $6$ ns $7$ ns $10$ ns $8$ ns
asked Jan 13 in Digital Logic Satbir 458 views
3 votes
4 answers
19
ISI2017-DCG-10
The value of the Boolean expression (with usual definitions) $(A’BC’)’ +(AB’C)’$ is $0$ $1$ $A$ $BC$
The value of the Boolean expression (with usual definitions) $(A’BC’)’ +(AB’C)’$ is $0$ $1$ $A$ $BC$
asked Sep 18, 2019 in Digital Logic gatecse 300 views
3 votes
1 answer
20
Digital logic- nptel assignment
Suppose we are using 4-bit carry lookahead adder modules to build a 64- bit adder with two-level carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worst-case delay of the 64-bit adder will be ……….. nanoseconds.
Suppose we are using 4-bit carry lookahead adder modules to build a 64- bit adder with two-level carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worst-case delay of the 64-bit adder will be ……….. nanoseconds.
asked Aug 13, 2019 in Digital Logic ajaysoni1924 334 views
2 votes
2 answers
21
Logic Gates and switching circuits
The gates G1 & G2 in the figure have propagation delays of 10ns and 20ns respectively. If the input Vi makes an abrupt change from logic 0 to 1 at time t=t0 , then what's the output waveform V0 is ? Also please explain how to handle such kinds of questions of waveform? ​​​​
The gates G1 & G2 in the figure have propagation delays of 10ns and 20ns respectively. If the input Vi makes an abrupt change from logic 0 to 1 at time t=t0 , then what's the output waveform V0 is ? Also please explain how to handle such kinds of questions of waveform? ​​​​
asked Jun 14, 2019 in Digital Logic Gitika Babbar 620 views
0 votes
2 answers
23
Gray Code (Self Doubt)
Was solving the GO 2019 pdf when I encountered this question asked in TIFR 2017. Although I have understood this question, I have one doubt- It is mentioned in the question that for a 3-bit number, the ordering (000, 100, 101, 111, 110, 010, 011, 001) is one of the possible Gray codes. Then, how many such orders are there for an n-bit number?
Was solving the GO 2019 pdf when I encountered this question asked in TIFR 2017. Although I have understood this question, I have one doubt- It is mentioned in the question that for a 3-bit number, the ordering (000, 100, 101, 111, 110, 010, 011, 001) is one of the possible Gray codes. Then, how many such orders are there for an n-bit number?
asked Jun 13, 2019 in Digital Logic Debargha Bhattacharj 213 views
0 votes
0 answers
24
MADE EASY ELECTRONICS
The number of Essential Prime implicants are ______________.
The number of Essential Prime implicants are ______________.
asked May 25, 2019 in Digital Logic Hirak 209 views
0 votes
1 answer
25
carry look ahead adder vs ripple carry
$Exclusive-OR$ gate has a propagation delay of $10$ ns and that the $AND$ or $OR$ gates have a propagation delay of $5$ ns.What is the total propagation delay time in the four-bit adder.Assume $FAN-IN =2$ $1)$ ripple adder $2)$ carry look ahead adder
$Exclusive-OR$ gate has a propagation delay of $10$ ns and that the $AND$ or $OR$ gates have a propagation delay of $5$ ns.What is the total propagation delay time in the four-bit adder.Assume $FAN-IN =2$ $1)$ ripple adder $2)$ carry look ahead adder
asked May 16, 2019 in Digital Logic val_pro20 212 views
1 vote
1 answer
26
Made Easy Test Series:Flip-Flop
A Finite State Machine(FSM) is implemented using the D-FFs A and B with logic gates as shown below. The four possible states of FSM are $Q_{A}Q_{B}=00,01,10,11$. Assume that $X_{in}$ is held at constant logic level throughout the operation of FSM. ... states if $X_{in}=0$ How do we check $X_{in}$ here? Can we check it arbitrarily, or checked with prev states??
A Finite State Machine(FSM) is implemented using the D-FFs A and B with logic gates as shown below. The four possible states of FSM are $Q_{A}Q_{B}=00,01,10,11$. Assume that $X_{in}$ is held at constant logic level throughout the operation of FSM. Where the FSM is ... the four possible states if $X_{in}=0$ How do we check $X_{in}$ here? Can we check it arbitrarily, or checked with prev states??
asked May 16, 2019 in Digital Logic srestha 248 views
4 votes
3 answers
27
GateBook Test Series: Digital Logic - Boolean Algebra
What is the time complexity for checking whether an assignment of truth values to variables $x_1,\dots ,x_n$ satisfies a given formula $f(x_1\dots,x_n)$? $O(2^n)$ $O(g(n))$ where $g$ is a polynomial $O(log(n))$ None of the above
What is the time complexity for checking whether an assignment of truth values to variables $x_1,\dots ,x_n$ satisfies a given formula $f(x_1\dots,x_n)$? $O(2^n)$ $O(g(n))$ where $g$ is a polynomial $O(log(n))$ None of the above
asked May 15, 2019 in Digital Logic val_pro20 401 views
0 votes
1 answer
28
Made Easy Test Series: Digital Logic- Master Slave FF
$1)$ Master-Slave FF is designed to avoid race around condition $2)$ Master-Slave FF is used to store $2$ bit information Which of the following statement is correct? What is meaning of $2-bit $ information??
$1)$ Master-Slave FF is designed to avoid race around condition $2)$ Master-Slave FF is used to store $2$ bit information Which of the following statement is correct? What is meaning of $2-bit $ information??
asked May 15, 2019 in Digital Logic srestha 265 views
1 vote
2 answers
29
Made Easy Test Series: Digital Logic
A $3\times 8$ decoder with $2$ enable inputs is used to address $8$ block of memory. What will be the size of each memory block when addressed from a $16$ bit bus with $2$ MSB’s used to enable the decoder?
A $3\times 8$ decoder with $2$ enable inputs is used to address $8$ block of memory. What will be the size of each memory block when addressed from a $16$ bit bus with $2$ MSB’s used to enable the decoder?
asked May 15, 2019 in Digital Logic srestha 418 views
0 votes
1 answer
30
TEST BOOK QUESTION
CAN SOMEBODY EXPLAIN THIS ANSWER PLZ !!!
CAN SOMEBODY EXPLAIN THIS ANSWER PLZ !!!
asked May 14, 2019 in Digital Logic Shawn Frost 109 views
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