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Recent questions tagged digitallogic
Webpage for Digital Logic:
0
votes
0
answers
1
ME_Test_EPI
I think EPI will come to be 2.But answer given is 3. Please help me.
asked
3 days
ago
in
Digital Logic
by
Ayush Upadhyaya
Boss
(
11k
points)

31
views
digitallogic
+1
vote
1
answer
2
PI and EPI in case of Don't care
Consider the below function $f=\sum m(0,1,2,5,8,15)+d(6,7,10)$ In this Prime Implicant count comes7 and Essential Prime Implicant Count comes 2. Please verify.
asked
3 days
ago
in
Digital Logic
by
Ayush Upadhyaya
Boss
(
11k
points)

229
views
digitallogic
0
votes
1
answer
3
EPI Question
asked
6 days
ago
in
Digital Logic
by
smsubham
Loyal
(
6.8k
points)

89
views
digitallogic
0
votes
0
answers
4
Functionally complete
F(x, y, z) =x + y'z' It's functionally complete according to normal procedure to implement NOT & OR or AND from it. But from this short trick. https://www.google.co.in/amp/s/www.geeksforgeeks.org/gategatecs2015set1question49/amp It's preserving 1.so it can't be functionally complete. I must be wrong but I could not identify it.
asked
Aug 10
in
Digital Logic
by
MayankSharma
(
153
points)

24
views
functionalcompleteness
digitallogic
0
votes
0
answers
5
Self Doubt
Which if the following are correct? (Multiple Possible) A ExNOR (BC) = (A ExNOR B) (A ExNOR C) A ExOR (B + C) = (A ExOR B) + (A ExOR C) A ExNOR (B + C) = (A ExNOR B) + (A ExNOR C) None of These
asked
Aug 8
in
Digital Logic
by
smsubham
Loyal
(
6.8k
points)

29
views
digitallogic
booleanexpressions
booleanalgebra
booleanoperations
0
votes
0
answers
6
MADEEASY TESTSERIES DLD
Amazon announce a new flip flop named SetResetToggle due to shortage elements to the electronics and computer industries. The device symbol and function table for this flip flop are shown below: Which of the following is the characteristic equation? A. Q+=TQ′ + T′[Q(S ⊕ R) + SR′] B. Q+=(T ⊕Q) + S+R′Q C. Q+ = T′Q + T[Q′(S + R) + SR′] D. Q+ = TQ′ + T′[Q(S + R′) + SR′]
asked
Aug 7
in
Digital Logic
by
Avijit Shaw
(
11
points)

20
views
madeeasytestseries
digitallogic
gate
characteristic
equation
0
votes
2
answers
7
Output of 4 x 1 MUX
What will be the output "Y" of the mux?
asked
Aug 7
in
Digital Logic
by
Mk Utkarsh
Boss
(
14k
points)

32
views
digitallogic
multiplexer
0
votes
0
answers
8
Condition for overflow
Will addition of two negative numbers cause any overflow?
asked
Aug 6
in
Digital Logic
by
srestha
Veteran
(
91.8k
points)

34
views
digitallogic
overflow
0
votes
0
answers
9
number system
How to convert a floating point number from Number system X to Number system Y? Ex: Given a number .75, I need to convert to base 9, say. Please help.
asked
Aug 6
in
Digital Logic
by
pps121
Active
(
1.3k
points)

23
views
digitallogic
numberrepresentation
0
votes
0
answers
10
work book
Q 1. Fourbit parallel adder is given the number of half adder and OR gate required to implement 4bit parallel adder are 1.7 and 3 2.8 and 3 3. 7 and 4 4. 8 and 4 Q 2.The number of full adders and half adder required to add 16bit number is? (G) 8 HA, 8FH (A) 1 HA, 15 FA (T) 16 HA,0 FA (E) 4 HA, 12 FA
asked
Aug 5
in
Digital Logic
by
amit166
(
39
points)

30
views
digitallogic
0
votes
1
answer
11
GATE BOOK
Total number of prime implicants in the function F(A, B)=A EOR B
asked
Aug 2
in
Digital Logic
by
amit166
(
39
points)

45
views
digitallogic
0
votes
2
answers
12
#Number System
$(70\,\,\,34\,\,\, 3\,)_{81} = (?)_3$ Any trick to solve this type of questions?
asked
Jul 31
in
CO & Architecture
by
Anuj1995
(
251
points)

54
views
digitallogic
numberrepresentation
practice
0
votes
1
answer
13
DigitalME Workbook #4
What is the answer to this?
asked
Jul 31
in
Digital Logic
by
Ayush Upadhyaya
Boss
(
11k
points)

32
views
digitallogic
0
votes
2
answers
14
DigitalME Workbook #3
I am getting 8 gates as an answer to this. Can it be less than this?
asked
Jul 31
in
Digital Logic
by
Ayush Upadhyaya
Boss
(
11k
points)

34
views
digitallogic
0
votes
1
answer
15
DigitalME Worbook #2
To this I am getting answer as (d). Please confirm.
asked
Jul 31
in
Digital Logic
by
Ayush Upadhyaya
Boss
(
11k
points)

23
views
digitallogic
0
votes
1
answer
16
DigitalMade Easy Workbook
To this, I am getting answer as (A). Let me know if its correct.
asked
Jul 31
in
Digital Logic
by
Ayush Upadhyaya
Boss
(
11k
points)

37
views
digitallogic
0
votes
0
answers
17
Confusion in Synchronus Series Counter
I am not getting any difference between these two questions but answers are not matching, https://gateoverflow.in/86195/metest https://gateoverflow.in/26442/gate19915c
asked
Jul 29
in
Digital Logic
by
Shaik Masthan
Boss
(
15.5k
points)

78
views
sequentialcircuit
digitalcircuits
digitallogic
0
votes
0
answers
18
JK FLip Flop
If JK Flip Flop is used then owing to it's master slave nature,doesn't the complexity of the circuitry increased?
asked
Jul 29
in
Digital Logic
by
Devshree Dubey
Boss
(
13.2k
points)

18
views
digitallogic
flipflop
0
votes
0
answers
19
Johnson Counter Doubt
I have found this statement about Johnson Counter : A Johnson counter requires decoding gates whereas a ring counter doesn't. As with the binary counter, one logic gate (AND gate) is required to decode each state, but with the Johnson counter, each ... to implement it? The reference link is here: https://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol4/cwl3/report.html#johnson
asked
Jul 27
in
Digital Logic
by
dan31
(
19
points)

10
views
digitallogic
digitalcounter
0
votes
0
answers
20
Doubt regarding Flip Flop
How is it ascertained for a Flip Flop irrespective of it being SR,JK,T or D Flip Flop that it's NOR/NAND Gate implementation is talked of?
asked
Jul 27
in
Digital Logic
by
Devshree Dubey
Boss
(
13.2k
points)

25
views
digitallogic
flipflop
0
votes
0
answers
21
Minimization of POS
Please verify my approach for calculation the minimal POS form for a function f. STEPS: Find out the f' in sum of minterms. Minimize f' and find out minimal SOP form. Using DeMorgan's law, find out f. The calcuated f will be minimal and in ... approach. However, I need a confirmation whether this method is actually correct and is bound to give me correct results all the time..!
asked
Jul 26
in
Digital Logic
by
Harsh Kumar
Junior
(
587
points)

10
views
digitallogic
kmap
minsumofproductsform
0
votes
1
answer
22
Doubt regarding SR Flip Flop
Please can anyone explain Clocked SR FlipFlop with NAND gate Implementation via a Truth Table especially.
asked
Jul 26
in
Digital Logic
by
Devshree Dubey
Boss
(
13.2k
points)

32
views
digitallogic
0
votes
0
answers
23
Booth bitpair recoding of multipliers doubt
asked
Jul 22
in
Digital Logic
by
iarnav
Loyal
(
7.9k
points)

18
views
digitallogic
boothsbitpairrecoding
0
votes
1
answer
24
#Digital logic Floatinf point representation
asked
Jul 20
in
Digital Logic
by
iarnav
Loyal
(
7.9k
points)

79
views
floatingpointrepresentation
#digitallogic
digitallogic
coandarchitecture
+1
vote
1
answer
25
digital logic Floating point number
A 32bit floatingpoint number(follows IEEE STANDARD) is represented by a 8bit signed exponent, and a 23bit fractional mantissa. The base of the scale factor is 16, The range of the exponent is ___________, if the scale factor is represented in excess64 format.
asked
Jul 20
in
Digital Logic
by
iarnav
Loyal
(
7.9k
points)

55
views
floatingpointrepresentation
digitallogic
ieeerepresentation
+1
vote
1
answer
26
digital logic Floating point number
A 32bit floatingpoint number (follows IEEE Standard)is represented by a 8bit signed exponent, and a 23bit fractional mantissa. The base of the scale factor is 16, The range of the exponent is ___________ .
asked
Jul 20
in
Digital Logic
by
iarnav
Loyal
(
7.9k
points)

53
views
floatingpointrepresentation
digitallogic
ieeerepresentation
0
votes
1
answer
27
Minterm
I had a slight doubt as regards with Minterm. How the output is 1 in the truth table values of the minterms?Please explain in detail.
asked
Jul 18
in
Digital Logic
by
Devshree Dubey
Boss
(
13.2k
points)

53
views
digitallogic
0
votes
1
answer
28
Doubt
How NAND GATE is used for making of AND GATE?
asked
Jul 16
in
Digital Logic
by
Devshree Dubey
Boss
(
13.2k
points)

62
views
digitallogic
0
votes
0
answers
29
Minimum number of nand or nor gates for 2 bit adder.
asked
Jul 3
in
Digital Logic
by
adil.wadood
(
7
points)

78
views
digitallogic
adder
combinational
nand
nor
0
votes
1
answer
30
Online Lecture
Consider a GATE which outputs high voltage when all inputs are high and outputs low otherwise. How does this gate behave in positive logic gate and negative logic gate?
asked
Jun 24
in
Digital Logic
by
darkshadows
(
11
points)

37
views
postivelogicgate
digitallogic
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