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Recent questions tagged digitallogic
Webpage for Digital Logic:
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1
Digital
asked
2 hours
ago
in
Digital Logic
by
manisha11
Active
(
1.9k
points)

27
views
digitallogic
0
votes
0
answers
2
Digital
asked
2 hours
ago
in
Digital Logic
by
manisha11
Active
(
1.9k
points)

16
views
digitallogic
0
votes
0
answers
3
DLD cse
asked
3 hours
ago
in
Digital Logic
by
manisha11
Active
(
1.9k
points)

24
views
digitallogic
0
votes
1
answer
4
Digital logic  Morris Mano
How to multiply two numbers in the given base without converting them into decimals. $(1230)_4 \ and \ (23)_4$
asked
Feb 11
in
Digital Logic
by
Swapnil Naik
Active
(
3k
points)

48
views
digitallogic
morrismano
+3
votes
3
answers
5
GATE20194
In $16$bit $2$’s complement representation, the decimal number $28$ is: $1111 \: 1111 \: 0001 \: 1100$ $0000 \: 0000 \: 1110 \: 0100$ $1111 \: 1111 \: 1110 \: 0100$ $1000 \: 0000 \: 1110 \: 0100$
asked
Feb 7
in
Digital Logic
by
Arjun
Veteran
(
385k
points)

1.8k
views
gate2019
digitallogic
numberrepresentation
+2
votes
4
answers
6
GATE20196
Which one of the following is NOT a valid identity? $(x \oplus y) \oplus z = x \oplus (y \oplus z)$ $(x + y) \oplus z = x \oplus (y+z)$ $x \oplus y = x+y, \text{ if } xy=0$ $x \oplus y = (xy+x’y’)’$
asked
Feb 7
in
Digital Logic
by
Arjun
Veteran
(
385k
points)

1.7k
views
gate2019
digitallogic
booleanalgebra
0
votes
4
answers
7
GATE20198
Consider $Z=XY$ where $X, Y$ and Z are all in signmagnitude form. X and Y are each represented in $n$ bits. To avoid overflow, the representation of $Z$ would require a minimum of: $n$ bits $n1$ bits $n+1$ bits $n+2$ bits
asked
Feb 7
in
Digital Logic
by
Arjun
Veteran
(
385k
points)

1.9k
views
gate2019
digitallogic
numberrepresentation
+3
votes
4
answers
8
GATE201922
Two numbers are chosen independently and uniformly at random from the set {1,2,….,13}. The probability (rounded off to 3 decimal places) that their 4bit (unsigned) binary representations have the same most significant bit is _______________.
asked
Feb 7
in
Digital Logic
by
Arjun
Veteran
(
385k
points)

3.6k
views
gate2019
numericalanswers
digitallogic
numberrepresentation
probability
+1
vote
3
answers
9
GATE201930
Consider three $4$variable functions $f_1, f_2$, and $f_3$, which are expressed in sumofminterms as $f_1=\Sigma(0,2,5,8,14),$ $f_2=\Sigma(2,3,6,8,14,15),$ $f_3=\Sigma (2,7,11,14)$ For the following circuit with one AND gate and one XOR gate the output function $f$ can be expressed as: $\Sigma(7,8,11)$ $\Sigma (2,7,8,11,14)$ $\Sigma (2,14)$ $\Sigma (0,2,3,5,6,7,8,11,14,15)$
asked
Feb 7
in
Digital Logic
by
Arjun
Veteran
(
385k
points)

1.8k
views
gate2019
digitallogic
kmap
logicgates
+2
votes
9
answers
10
GATE201950
What is the minimum number of $2$input NOR gates required to implement a $4$ variable function expressed in sumofminterms form as $f=\Sigma(0,2,5,7, 8, 10, 13, 15)?$ Assume that all the inputs and their complements are available. Answer: _______
asked
Feb 7
in
Digital Logic
by
Arjun
Veteran
(
385k
points)

3.9k
views
gate2019
numericalanswers
digitallogic
canonicalnormalform
0
votes
1
answer
11
Gate 2019: Bits to avoid Overflow.
Let Z = X – Y, X, Y, Z are signed magnitude numbers and X, Y are represented in nbit numbers. To avoid overflow minimum number of bits would require for Z is _________ (a) nbit (b) n + 2 bits (c) n + 1 bits (d) (n – 1) bits
asked
Feb 4
in
Digital Logic
by
HeartBleed
(
485
points)

449
views
numberrepresentation
digitallogic
0
votes
0
answers
12
GO Mock test  4 by Bikram
In a synchronous series counter of Modulus 256, the propagation delay for each 2 input AND gate is 5 ns and for each flipflop is 25 ns. The maximum frequency of the Mod256 counter is _____MHz. https://gateoverflow.in/129738/gofullmock451 Given ... Doubt: Why we even need AND gates, we can make this counter with 8 flip flops, hence answer should be $1/25ns= 40MHZ$
asked
Jan 31
in
Digital Logic
by
chauhansunil20th
Active
(
4.8k
points)

26
views
digitallogic
0
votes
1
answer
13
#DigitalLogic
How many maximum boolean expressions such that f(x,y,z)=f($\overline{x},y,\overline{z}$)
asked
Jan 31
in
Digital Logic
by
Reshu $ingh
(
339
points)

38
views
digitallogic
0
votes
0
answers
14
#DigitalLogic
Why Gray codes are called reflected codes?
asked
Jan 28
in
Digital Logic
by
Reshu $ingh
(
339
points)

51
views
digitallogic
graycode
0
votes
0
answers
15
IEEE smallest difference
What is the minimum difference between two successive real numbers representable in this system?
asked
Jan 28
in
Digital Logic
by
Balaji Jegan
Active
(
4.8k
points)

83
views
ieeerepresentation
floatingpointrepresentation
digitallogic
coandarchitecture
0
votes
0
answers
16
Ace academy workbook
Till what value of mod counter you will call it? As per my understanding the maximum number it is counting is 5 so I call it as mod 6 counter but in in the workbook it is given as mod 5 counter and their explanation is that number of states are 5 that's why it is a mod 5 counter. What is correct and why? please help me.
asked
Jan 27
in
Digital Logic
by
Shashankesh Upadhyay
(
61
points)

47
views
digitallogic
digitallogic
digitalcounter
0
votes
0
answers
17
made easy test
Consider the circuit given below. Assume initially flipflops are in reset state. What will be the mod of above digital circuit?
asked
Jan 27
in
Digital Logic
by
snaily16
(
255
points)

45
views
madeeasytestseries
digitallogic
digitalcircuits
flipflop
0
votes
0
answers
18
#ACETestSeries
What is the concept of dummy bits? Please explain with examples.
asked
Jan 26
in
Digital Logic
by
Reshu $ingh
(
339
points)

18
views
digitallogic
digitalcircuits
0
votes
0
answers
19
made easy
asked
Jan 26
in
Digital Logic
by
screddy1313
(
401
points)

40
views
madeeasytestseries
digitallogic
0
votes
0
answers
20
What is the meaning of "A MINTERM GIVES VALUE '1' FOR EXACTLY ONE COMBINATIO OF VARIABLES"
asked
Jan 23
in
Digital Logic
by
sambana
(
43
points)

13
views
digitallogic
logicfunctions
0
votes
0
answers
21
flip flop msb lsb
What should be default order of msb lsb in flip flops if msb lsb flip flop not given for a counter
asked
Jan 21
in
Digital Logic
by
bts1jimin
(
245
points)

19
views
digitallogic
flipflop
0
votes
1
answer
22
flip flop : find mod of counter having presets as shown
asked
Jan 20
in
Digital Logic
by
bts1jimin
(
245
points)

37
views
digitallogic
flipflop
0
votes
0
answers
23
GATEBOOK2019 Mock Test147
A $1$ to $8$ multiplexer with data input $D_{in}$, address inputs $S_0, S_1, S_2$ (with $S_0$ as the LSB) and $\overline{Y}_0$ to $\overline{Y}_7$ as the eight multiplexed output, is to be designed using two $2 \text{to} 4$ decoders (with enable input $\overline{E}$ ... be $S_2, D_{in}, S_0, S_1$ $S_1, D_{in}, S_0, S_2$ $D_{in}, S_0, S_1. S_2$ $D_{in}, S_2, S_0, S_1$
asked
Jan 19
in
Others
by
GATEBOOK
Boss
(
15.3k
points)

167
views
gb2019mock1
digitallogic
demultiplexer
0
votes
0
answers
24
Made east test series
Please answer??
asked
Jan 17
in
Digital Logic
by
raahul
Active
(
1.2k
points)

38
views
madeeasytestseries
digitallogic
0
votes
1
answer
25
Full adder
Assume the operands are in 2’s Complement. To decrement A by 1, lines K,Cn and B should be : K = 1 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 1 K = 0 , Cin = 1 , B = 0 K = 1 , Cin = 0 , B = 0
asked
Jan 16
in
Digital Logic
by
Na462
Loyal
(
8.6k
points)

49
views
digitallogic
carrygenerator
fulladder
madeeasytestseries
0
votes
0
answers
26
self doubt
What is lockout state.
asked
Jan 15
in
Digital Logic
by
iamdeepakji
(
227
points)

30
views
digitallogic
+1
vote
0
answers
27
State Transition Diagram
Consider the below Digital Circuit : The State Transition diagram on circuit is :
asked
Jan 13
in
Digital Logic
by
Na462
Loyal
(
8.6k
points)

57
views
digitallogic
flipflop
madeeasytestseries
0
votes
0
answers
28
gateforum mock1
How to do these type questions step by step please help
asked
Jan 11
in
Digital Logic
by
Prince Sindhiya
Loyal
(
6.2k
points)

56
views
digitallogic
0
votes
0
answers
29
Madeeasy
asked
Jan 11
in
Digital Logic
by
jatin khachane 1
Loyal
(
6.4k
points)

97
views
madeeasytestseries
digitallogic
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