Recent questions tagged digital-logic

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Digital logic- nptel assignment
Suppose we are using 4-bit carry lookahead adder modules to build a 64- bit adder with two-level carry lookahead, with ripple carry between the modules. If the delay of a basic gate (AND, OR, NOT) is 2 nanoseconds, the worst-case delay of the 64-bit adder will be ……….. nanoseconds.

asked Aug 13 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 48 views

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1 answer

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Logic Gates and switching circuits
The gates G1 & G2 in the figure have propagation delays of 10ns and 20ns respectively. If the input Vi makes an abrupt change from logic 0 to 1 at time t=t0 , then what's the output waveform V0 is ? Also please explain how to handle such kinds of questions of waveform?

asked Jun 14 in Digital Logic by Gitika Babbar (147 points) | 101 views

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3 answers

3

Minimization doubt in DIGITAL LOGIC

asked Jun 14 in Digital Logic by Gitika Babbar (147 points) | 66 views

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1 answer

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Gray Code (Self Doubt)
Was solving the GO 2019 pdf when I encountered this question asked in TIFR 2017. Although I have understood this question, I have one doubt- It is mentioned in the question that for a 3-bit number, the ordering (000, 100, 101, 111, 110, 010, 011, 001) is one of the possible Gray codes. Then, how many such orders are there for an n-bit number?

asked Jun 13 in Digital Logic by Debargha Bhattacharj Junior (515 points) | 98 views

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MADE EASY ELECTRONICS
The number of Essential Prime implicants are ______________.

asked May 25 in Digital Logic by Hirak Active (3.4k points) | 68 views

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carry look ahead adder vs ripple carry
$Exclusive-OR$ gate has a propagation delay of $10$ ns and that the $AND$ or $OR$ gates have a propagation delay of $5$ ns.What is the total propagation delay time in the four-bit adder.Assume $FAN-IN =2$ $1)$ ripple adder $2)$ carry look ahead adder

asked May 16 in Digital Logic by val_pro20 Active (1.1k points) | 54 views

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Made Easy Test Series:Flip-Flop
A Finite State Machine(FSM) is implemented using the D-FFs A and B with logic gates as shown below. The four possible states of FSM are $Q_{A}Q_{B}=00,01,10,11$. Assume that $X_{in}$ is held at constant logic level throughout the operation of FSM. ... states if $X_{in}=0$ How do we check $X_{in}$ here? Can we check it arbitrarily, or checked with prev states??

asked May 16 in Digital Logic by srestha Veteran (113k points) | 69 views

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3 answers

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GateBook Test Series: Digital Logic - Boolean Algebra
What is the time complexity for checking whether an assignment of truth values to variables $x_1,\dots ,x_n$ satisfies a given formula $f(x_1\dots,x_n)$? $O(2^n)$ $O(g(n))$ where $g$ is a polynomial $O(log(n))$ None of the above

asked May 15 in Digital Logic by val_pro20 Active (1.1k points) | 135 views

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Made Easy Test Series: Digital Logic- Master Slave FF
$1)$ Master-Slave FF is designed to avoid race around condition $2)$ Master-Slave FF is used to store $2$ bit information Which of the following statement is correct? What is meaning of $2-bit $ information??

asked May 15 in Digital Logic by srestha Veteran (113k points) | 95 views

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1 answer

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Made Easy Test Series: Digital Logic
A $3\times 8$ decoder with $2$ enable inputs is used to address $8$ block of memory. What will be the size of each memory block when addressed from a $16$ bit bus with $2$ MSB’s used to enable the decoder?

asked May 15 in Digital Logic by srestha Veteran (113k points) | 64 views

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Boolean algebra-digital logic
$(a) A = 101010$ and $B = 011101$ are $1’s$ complement numbers. Perform the following operations and indicate whether overflow occurs. $(i) A + B$ $(ii) A − B$ $(b)$ Repeat part $(a)$ assuming the numbers are $2’s$ complement numbers.

asked May 11 in Digital Logic by val_pro20 Active (1.1k points) | 61 views

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BOOLEAN FUNCTION (Morris Mano)

asked May 6 in Digital Logic by altamash (429 points) | 43 views

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Boolean algebra expression Floyd Digital Logic
Simplify the following expression AB’C + A’BC + A’B’C Solution given is A’C + B’C can someone show me how?

asked May 2 in Digital Logic by vupadhayayx86 Active (1.3k points) | 137 views

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Test Book digital logic
I think option A is also correct ! if we take minterm and complement it to get POS then option A can also be the answer

asked Apr 9 in Digital Logic by Shawn Frost (31 points) | 68 views

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Morris Mano Edition 3 Exercise 9 Question 24 (Page No. 396)
The boolean functions for the input of SR latch are as follows. Obtain the circuit diagram using a minimum number of NAND gates. $S = x _1’x _2’x _3 + x _1x _2x _3$. $R = x _1x _2’ + x _2x _3’$

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 31 views

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Morris Mano Edition 3 Exercise 9 Question 23 (Page No. 396)
Draw the logic diagram of the product of sum expression $ Y = (x _1 + x _2’)(x _2 + x _3)$ Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero and $x _2$ goes from 0 to 1.Find a way to remove hazard by adding one more OR gate.

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 16 views

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Morris Mano Edition 3 Exercise 9 Question 22 (Page No. 396)
Find a circuit that has no static hazard and implements the boolean function: F(A,B,C,D) = $\sum(0,2,6,7,8,10,12)$

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 21 views

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Morris Mano Edition 3 Exercise 9 Question 18 (Page No. 395)
Merge each of the primitive flow table shown in the figure. Proceed as follows: Find all compatible pairs by means of implication table. Find the maximal compatibles by means of a merger diagram FInd the minimal set of compatibles that covers all the states and is closed.

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 30 views

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Morris Mano Edition 3 Exercise 9 Question 17 (Page No. 395)
Reduce the number of states in the state table listed below. Use an implication table.

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 15 views

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Morris Mano Edition 3 Exercise 9 Question 16 (Page No. 395)
Using the implication table method, show that the state table listed in the figure cannot be reduced any further.

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 20 views

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Morris Mano Edition 3 Exercise 9 Question 15 (Page No. 395)
Assign output values to the don’t care states in the flow tables in the figure below in such a way as to avoid transient output places

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 12 views

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Morris Mano Edition 3 Exercise 9 Question 14 (Page No. 394)
It is necessary to design an asynchronous sequential circuit with two inputs, $x _1 and x _2$, and one output $z$. Initially, both input and output are zero. when $x _1 and x _2$ becomes 1, z becomes 1. when the ... for the circuit and show that it can be reduced to the flow table shown in the figure complete the design of the circuit.

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 13 views

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Morris Mano Edition 3 Exercise 9 Question 13,25 (Page No. 394)
A traffic light is installed at the junction of the railroad and a road. The traffic light is controlled by two switches in the rails placed one mile apart on either side of the junction. A switch is turned on when a ... circuit. show that the flow table can be reduced to four rows Complete the circuit specified in the above problem.

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 23 views

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24

Morris Mano Edition 3 Exercise 9 Question 12 (Page No. 394)
Obtain a primitive flow table for a circuit with two inputs, $x _1 and x _2$ and two outputs $y _1 and y _2$, that satisfy the following four conditions. When $x _1x _2 = 00$, the output is $z _1z _2 = 00$. when $x _1 = 1$ and ... $x _1$ changes from 0 to 1, the output is $z _1z _2$ = 10. otherwise the output does not change.

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 7 views

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Morris Mano Edition 3 Exercise 9 Question 11 (Page No. 394)
Implement the circuit defined below with NAND SR latch. An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are as follows. $Y _1 = x _1x _2 + x _1y _2’ + x _2’y _1$ $Y _2 = x _2 + x _1y _1’y _2 + x _1’y _1$ $z = x _2 + y _1$

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 8 views

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26

Morris Mano Edition 3 Exercise 9 Question 10 (Page No. 394)
Implement the circuit with defined below with NOR SR latch. an asynchronous circuit is described by the following excitation and output functions: $Y = x _1x _2’ + (x _1 + x _2’)y$ $z = y$

asked Apr 8 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 9 views

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27

ISI2017-PCB-B-8(b)
Consider a simple code C for error detection and correction. Each codeword in C consists of 2 data bits $[d_1, d_0]$ followed by check bits $[c_2, c_1, c_0]$ ... '+' is a modulo-2 addition. Write down all the codewords for C Determine the minimum Hamming distance between any two distinct codewords of C

asked Apr 8 in Digital Logic by akash.dinkar12 Boss (41.3k points) | 27 views

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28

ISI2017-PCB-B-7(b)
Define a Boolean function $F(X_1, X_2, X_3, X_4, X_5, X_6)$ of six variables such that $\\ \begin{matrix} F & = & \text{1, when three or more input variables are at logic 1} \\ \: & = & \text{0, otherwise} \end{matrix} $ How many essential prime implicants does $F$ have? Justify they are essential.

asked Apr 8 in Digital Logic by akash.dinkar12 Boss (41.3k points) | 25 views

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Morris Mano Edition 3 Exercise 9 Question 9 (Page No. 394)
For the asynchronous sequential circuit shown in the figure: Derive the boolean functions for the outputs of two SR latches $Y _1 and Y _2$. Note that the S input of the second latch is $x _1’y _1’$. Derive the transition table and output map of the circuit.

asked Apr 7 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 28 views

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30

Morris Mano Edition 3 Exercise 9 Question 8 (Page No. 394)
Convert the circuit of the figure to the asynchronous sequential circuit by removing the clock-pulse(CP) and changes the flip-flops to the SR latches. Derive the transition table and output map of the modified circuit.

asked Apr 7 in Digital Logic by ajaysoni1924 Boss (10.2k points) | 22 views

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