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Recent questions tagged digital-logic

1 votes
2 answers
1292
Carry lookahead adder
can anyone tell me wat is the right equation for carry generator in carry lookahead adder ?? Confused .. $ C_{i} = G_{i}+P_{i}C_{i-1}$ $ C_{i+1}=G_{}i+P_{}iC_{}i$
can anyone tell me wat is the right equation for carry generator in carry lookahead adder ?? Confused ..$ C_{i} = G_{i}+P_{i}C_{i-1}$$ C_{i+1}=G_{}i+P_{}iC_{}i$
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0 votes
2 answers
1293
Latch
The number of D-latches present in edge-triggered D-flip flop is :- (A) 4 (B) 1 (C) 2 (D) 3
The number of D-latches present in edge-triggered D-flip flop is :-(A) 4(B) 1(C) 2(D) 3
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1 votes
1 answer
1294
ISRO-DEC2017-76
Which of the following set of components is sufficient to implement any arbitrary Boolean function? $XOR$ gates, $NOT$ gates $AND$ gates, $XOR$ gates and $1$ $2$ to $1$ multiplexer Three input gates that output $(A.B)+C$ for the inputs $A, B, C$
Which of the following set of components is sufficient to implement any arbitrary Boolean function?$XOR$ gates, $NOT$ gates$AND$ gates, $XOR$ gates and $1$$2$ to $1$ mult...
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0 votes
1 answer
1298
ROM Implementation
Could anyone explain the solution with a proper diagram?
Could anyone explain the solution with a proper diagram?
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0 votes
2 answers
1302
Nielit
How to solve these type questions ...what is procedure ...I know the answer I just want to know shortcuts
How to solve these type questions ...what is procedure ...I know the answer I just want to know shortcuts
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0 votes
0 answers
1303
What is the output of the combinational circuit?
Consider the combinational circuit given below: What is the output of this combinational circuit?
Consider the combinational circuit given below:What is the output of this combinational circuit?
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0 votes
0 answers
1304
how many number of clock pulses
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0 votes
1 answer
1306
K-Map
POS of (AB+C)
POS of (AB+C)
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0 votes
0 answers
1307
Ripple Carry Adder
Q.A one bit full adder takes 75 nsec to produce sum and 50 nsec to produce carry.A 4 bit parallel adder is designed using this type of full adder. The maximum rate of additions per second can be provided by 4 bit parallel adder......?
Q.A one bit full adder takes 75 nsec to produce sum and 50 nsec to produce carry.A 4 bit parallel adder is designed using this type of full adder. The maximum rate of add...
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0 votes
0 answers
1308
Digital logic Latch self doubt
I read that latch are level triggered and flip flop are egde triggered . Doubts 1. can a latch be synchronous? Is gated latch synchronous?? 2. Is flip flop always synchronous??
I read that latch are level triggered and flip flop are egde triggered .Doubts1. can a latch be synchronous? Is gated latch synchronous??2. Is flip flop always synchron...
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0 votes
0 answers
1310
No of 2 input NOR gates
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1 votes
0 answers
1311
Half adders
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1 votes
3 answers
1312
Digital Logic
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0 votes
1 answer
1313
made-easy
A 3 bit down counter is used to control the output of the multiplexer as shown in the figure. The counter is intially at (101)2 then output of multiplexer will follow the sequence i m getting I2,0,I1,0 is it correct?
A 3 bit down counter is used to control the output of the multiplexer as shown in the figure. The counter is intially at (101)2 then output of multiplexer will follow the...
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0 votes
3 answers
1314
MadeEasy Test Series: Digital Logic - Adder
A 1-bit full adder circuit takes 5 ns to generate the carry-out bit and 10 ns for the sum-bit. When 4, 1-bit full adders are cascaded, the maximum rate of additions per second will be _______ × 107.
A 1-bit full adder circuit takes 5 ns to generate the carry-out bit and 10 ns for the sum-bit. When 4, 1-bit full adders are cascaded, the maximum rate of additions per s...
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1 votes
1 answer
1315
made-easy
The initial content of serial IN parallel OUT, right shift, shift register shown below is 0011. After how many clock pulses, the content of register will return to its initial value. a) 7 b)8 c)11 d)13
The initial content of serial IN parallel OUT, right shift, shift register shown below is 0011. After how many clock pulses, the content of register will return to its in...
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0 votes
1 answer
1316
Counters
Is this statement true? Nonbinary counter means synchronous counter?
Is this statement true?Nonbinary counter means synchronous counter?
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0 votes
2 answers
1317
MadeEasy Test Series: Digital Logic - Digital Counter
What is the best architecture of the ‘Logic gate’? a 3-bit input AND gate a 2-input AND gate a NOT gate a wire connection (no logic gate needed)
What is the best architecture of the ‘Logic gate’?a 3-bit input AND gatea 2-input AND gatea NOT gatea wire connection (no logic gate needed)
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1 answer
1318
made-easy test series
A circuit is designed with 2 – J-K FF’s. If the output θA θB = 10 at starting, what will be the output (θA θB) after 13th clock pulse.
A circuit is designed with 2 – J-K FF’s. If the output θA θB = 10 at starting, what will be the output (θA θB) after 13th clock pulse.
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