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Recent questions tagged digital-logic
39
votes
5
answers
2071
GATE CSE 2000 | Question: 2.10
The simultaneous equations on the Boolean variables $x, y, z$ and $w$, $x + y + z = 1 $ $xy = 0$ $xz + w = 1$ $xy + \bar{z}\bar{w} = 0$ have the following solution for $x, y, z$ and $w,$ respectively: $0 \ 1 \ 0 \ 0$ $1 \ 1 \ 0 \ 1$ $1 \ 0 \ 1 \ 1$ $1 \ 0 \ 0 \ 0$
Kathleen
asked
in
Digital Logic
Sep 14, 2014
by
Kathleen
5.3k
views
gatecse-2000
digital-logic
boolean-algebra
easy
33
votes
4
answers
2072
GATE CSE 2000 | Question: 1.6
The number $43$ in $2's$ complement representation is $01010101$ $11010101$ $00101011$ $10101011$
Kathleen
asked
in
Digital Logic
Sep 14, 2014
by
Kathleen
9.5k
views
gatecse-2000
digital-logic
number-representation
easy
2
votes
0
answers
2073
GATE CSE 1992 | Question: 06,a,b
A microprocessor is capable of addressing 1 megabyte of memory with a 20-bit address bus. The system to be designed requires 256 K bytes of RAM, 256 K bytes of EPROM, 16 I/O devices (memory mapped I/O) and 1 K byte of ... to two clock cycles for memory read and write. Assuming control signals similar to 8085, design the extra logic required for interfacing EERAM.
Kathleen
asked
in
Digital Logic
Sep 13, 2014
by
Kathleen
640
views
gate1992
digital-logic
descriptive
memory-interfacing
out-of-gate-syllabus
8085-microprocessor
14
votes
3
answers
2074
GATE CSE 1992 | Question: 4-a
Consider addition in two's complement arithmetic. A carry from the most significant bit does not always correspond to an overflow. Explain what is the condition for overflow in two's complement arithmetic.
Kathleen
asked
in
Digital Logic
Sep 13, 2014
by
Kathleen
1.7k
views
gate1992
digital-logic
normal
number-representation
descriptive
20
votes
4
answers
2075
GATE CSE 1992 | Question: 02-ii
All digital circuits can be realized using only Ex-OR gates Multiplexers Half adders OR gates
Kathleen
asked
in
Digital Logic
Sep 13, 2014
by
Kathleen
5.6k
views
gate1992
normal
digital-logic
digital-circuits
multiple-selects
25
votes
4
answers
2076
GATE CSE 1992 | Question: 02-i
The operation which is commutative but not associative is: AND OR EX-OR NAND
Kathleen
asked
in
Digital Logic
Sep 13, 2014
by
Kathleen
4.0k
views
gate1992
easy
digital-logic
boolean-algebra
multiple-selects
20
votes
4
answers
2077
GATE CSE 1992 | Question: 01-i
The Boolean function in sum of products form where K-map is given below (figure) is _______
Kathleen
asked
in
Digital Logic
Sep 13, 2014
by
Kathleen
3.8k
views
gate1992
digital-logic
k-map
normal
fill-in-the-blanks
5
votes
1
answer
2078
GATE CSE 1991 | Question: 06,a
Using $\text{D}$ flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines: Clock $\text{CLK}$ Three parallel data inputs $A, B, C$ Serial input $S$ Control input $\text{load} / \overline{\text{SHIFT}}$.
Kathleen
asked
in
Digital Logic
Sep 13, 2014
by
Kathleen
827
views
gate1991
digital-logic
difficult
sequential-circuit
flip-flop
shift-registers
descriptive
22
votes
1
answer
2079
GATE CSE 1991 | Question: 5-a
Analyse the circuit in Fig below and complete the following table ${\begin{array}{|c|c|c|}\hline \textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline 0&0\\\ 0&1 \\ 1&0 \\ 1&1 \\ \hline \end{array}}$
Kathleen
asked
in
Digital Logic
Sep 13, 2014
by
Kathleen
3.0k
views
gate1991
digital-logic
normal
circuit-output
sequential-circuit
descriptive
27
votes
2
answers
2080
GATE CSE 1991 | Question: 03-ii
Advantage of synchronous sequential circuits over asynchronous ones is: faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above
Kathleen
asked
in
Digital Logic
Sep 12, 2014
by
Kathleen
6.5k
views
gate1991
digital-logic
normal
sequential-circuit
synchronous-asynchronous-circuits
multiple-selects
6
votes
3
answers
2081
GATE CSE 1991 | Question: 03,i
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: (i). The advantages of CMOS technology over a MOS is: (A). lower power dissipation (B). greater speed (C). smaller chip size (D). fewer masks for fabrication (E). none of the above
Kathleen
asked
in
Digital Logic
Sep 12, 2014
by
Kathleen
1.2k
views
gate1991
digital-logic
integrated-circuits
out-of-gate-syllabus
33
votes
1
answer
2082
GATE CSE 1991 | Question: 01-v
When two $4$-bit numbers $A = a_3a_2a_1a_0$ and $B=b_3b_2b_1b_0$ are multiplied, the bit $c_1$ of the product $C$ is given by ________
Kathleen
asked
in
Digital Logic
Sep 12, 2014
by
Kathleen
3.3k
views
gate1991
digital-logic
normal
number-representation
fill-in-the-blanks
21
votes
5
answers
2083
GATE CSE 1991 | Question: 01-iii
Consider the number given by the decimal expression: $16^3*9 + 16^2*7 + 16*5+3$ The number of $1’s$ in the unsigned binary representation of the number is ______
Kathleen
asked
in
Digital Logic
Sep 12, 2014
by
Kathleen
5.3k
views
gate1991
digital-logic
number-representation
normal
numerical-answers
28
votes
4
answers
2084
GATE CSE 2008 | Question: 26
If $P, Q, R$ are Boolean variables, then $(P + \bar{Q}) (P.\bar{Q} + P.R) (\bar{P}.\bar{R} + \bar{Q})$ simplifies to $P.\bar{Q}$ $P.\bar{R}$ $P.\bar{Q} + R$ $P.\bar{R} + Q$
Kathleen
asked
in
Digital Logic
Sep 12, 2014
by
Kathleen
8.2k
views
gatecse-2008
easy
digital-logic
boolean-algebra
33
votes
5
answers
2085
GATE CSE 2008 | Question: 8
Given $f_1$, $f_3$ and $f$ in canonical sum of products form (in decimal) for the circuit $f_1 = \Sigma m(4, 5, 6, 7, 8)$ $f_3 = \Sigma m(1, 6, 15)$ $f = \Sigma m(1, 6, 8, 15)$ then $f_2$ is $\Sigma m(4, 6)$ $\Sigma m(4, 8)$ $\Sigma m(6, 8)$ $\Sigma m(4, 6, 8)$
Kathleen
asked
in
Digital Logic
Sep 11, 2014
by
Kathleen
7.1k
views
gatecse-2008
digital-logic
canonical-normal-form
easy
28
votes
2
answers
2086
GATE CSE 2008 | Question: 6
Let $r$ denote number system radix. The only value(s) of $r$ that satisfy the equation $\sqrt{121_r}={11}_r$ is/are decimal $10$ decimal $11$ decimal $10$ and $11$ any value $> 2$
Kathleen
asked
in
Digital Logic
Sep 11, 2014
by
Kathleen
8.5k
views
gatecse-2008
digital-logic
number-representation
normal
25
votes
4
answers
2087
GATE CSE 2008 | Question: 5
In the Karnaugh map shown below, $X$ denotes a don’t care term. What is the minimal form of the function represented by the Karnaugh map? $\bar{b}.\bar{d} + \bar{a}.\bar{d}$ $\bar{a}.\bar{b} + \bar{b}.\bar{d} + \bar{a}.b.\bar{d}$ $\bar{b}.\bar{d} + \bar{a}.b.\bar{d}$ $\bar{a}.\bar{b} + \bar{b}.\bar{d} + \bar{a}.\bar{d}$
Kathleen
asked
in
Digital Logic
Sep 11, 2014
by
Kathleen
5.1k
views
gatecse-2008
digital-logic
k-map
easy
36
votes
2
answers
2088
GATE CSE 2008 | Question: 4
In the IEEE floating point representation the hexadecimal value $0\text{x}00000000$ corresponds to The normalized value $2^{-127}$ The normalized value $2^{-126}$ The normalized value $+0$ The special value $+0$
Kathleen
asked
in
Digital Logic
Sep 11, 2014
by
Kathleen
10.3k
views
gatecse-2008
digital-logic
floating-point-representation
ieee-representation
easy
3
votes
1
answer
2089
GATE CSE 1991 | Question: 01,i
Kathleen
asked
in
Others
Sep 11, 2014
by
Kathleen
856
views
gate1991
digital-logic
circuit-output
normal
out-of-gate-syllabus
55
votes
3
answers
2090
GATE CSE 2005 | Question: 62
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let $A_{i}$ represents the logic level on the line a in the i-th clock period. Let $A'$ represent the compliment of $A$. The correct output sequence on $Y$ over the clock periods $1$ ... $A_{1} A_{2} A_{2}' A_{3} A_{4}$ $A_{1} A_{2}' A_{3} A_{4} A_{5}'$
Isha Karn
asked
in
Digital Logic
Sep 3, 2014
by
Isha Karn
13.8k
views
gatecse-2005
digital-logic
circuit-output
normal
39
votes
3
answers
2091
GATE CSE 2012 | Question: 19
The amount of ROM needed to implement a $4\text{-bit}$ multiplier is $64$ bits $128$ bits $1$ Kbits $2$ Kbits
gatecse
asked
in
Digital Logic
Aug 5, 2014
by
gatecse
12.4k
views
gatecse-2012
digital-logic
normal
rom
32
votes
2
answers
2092
GATE CSE 2012 | Question: 7
The decimal value $0.5$ in IEEE single precision floating point representation has fraction bits of $000\dots 000$ and exponent value of $0$ fraction bits of $000\dots 000$ and exponent value of $−1$ fraction bits of $100\dots 000$ and exponent value of $0$ no exact representation
gatecse
asked
in
Digital Logic
Aug 5, 2014
by
gatecse
9.1k
views
gatecse-2012
digital-logic
normal
number-representation
ieee-representation
33
votes
3
answers
2093
GATE CSE 2012 | Question: 6
The truth table ${\begin{array}{|c|c|c|}\hline \textbf{X}& \textbf{Y}& \textbf{(X,Y)} \\\hline 0& 0& 0 \\ \hline 0& 1&0\\ \hline 1& 0& 1 \\\hline 1& 1& 1 \\\hline \end{array}}$ represents the Boolean function $X$ $X + Y$ $X \oplus Y$ $Y$
gatecse
asked
in
Digital Logic
Aug 5, 2014
by
gatecse
3.2k
views
gatecse-2012
digital-logic
easy
boolean-algebra
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