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Recent questions tagged direct-mapping
0
votes
3
answers
1
Made Easy Test Series 2024
Can anyone please confirm that below statement is correct or not : - Statement 3 is false for Only Full Associative cache mapping and for direct and set associative mapping Statement 3 is True Because of this concept(Answer) https://gateoverflow.in/409971/made-easy-test-series-2024
Can anyone please confirm that below statement is correct or not : -Statement 3 is false for Only Full Associative cache mapping and for direct and set associative map...
Ray Tomlinson
517
views
Ray Tomlinson
asked
Sep 5, 2023
CO and Architecture
direct-mapping
cache-memory
co-and-architecture
+
–
0
votes
3
answers
2
MADE EASY TEST SERIES 2024
SET ASSOCIATIVE MAP DIRECT MAP FULL ASSO MAP
SET ASSOCIATIVE MAPDIRECT MAP FULL ASSO MAP
Ray Tomlinson
362
views
Ray Tomlinson
asked
Sep 4, 2023
CO and Architecture
co-and-architecture
made-easy-test-series
direct-mapping
+
–
2
votes
1
answer
3
Unacademy Computer Organisation and Workbook
Assume a computer has a 32-bit address. Each block stores 64 bytes. A direct mapped cache has 512 blocks. In which block of cache would we look for each of the following addresses: 1A2BC012 FFFF00FF 12345678 C109D532
Assume a computer has a 32-bit address. Each block stores 64 bytes. A direct mapped cache has 512 blocks. In which block of cache would we look for each of the following ...
lovish_bhatia
303
views
lovish_bhatia
asked
Aug 27, 2023
CO and Architecture
co-and-architecture
direct-mapping
unacademy-test-series
+
–
1
votes
1
answer
4
Zeal Test
Question : Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 mapped??
Question :Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 map...
lalitver10
717
views
lalitver10
asked
Aug 19, 2022
CO and Architecture
co-and-architecture
zeal
cache-memory
direct-mapping
+
–
18
votes
2
answers
5
GATE CSE 2022 | Question: 44
Consider a system with $2 \;\text{KB}$ direct mapped data cache with a block size of $64 \; \text{bytes}.$ The system has a physical address space of $64 \; \text{KB}$ and a word length of $16 \; \text{bits.}$ During the execution of a program, four data ... only $\text{R}$ and $\text{S}$ reside in the cache. Every access to $\text{R}$ evicts $\text{Q}$ from the cache.
Consider a system with $2 \;\text{KB}$ direct mapped data cache with a block size of $64 \; \text{bytes}.$ The system has a physical address space of $64 \; \text{KB}$ an...
Arjun
9.1k
views
Arjun
asked
Feb 15, 2022
CO and Architecture
gatecse-2022
co-and-architecture
direct-mapping
multiple-selects
2-marks
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–
7
votes
5
answers
6
ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes?$2$ M...
Satbir
6.2k
views
Satbir
asked
Jan 13, 2020
CO and Architecture
isro-2020
co-and-architecture
cache-memory
direct-mapping
normal
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–
0
votes
2
answers
7
Direct Mapped Cache Multiplexer
Is there any multiplexer(s) present in the implementation of Direct Mapped Cache? If yes, then the Hit latency would be Multiplexer latency + Comparator Latency?
Is there any multiplexer(s) present in the implementation of Direct Mapped Cache?If yes, then the Hit latency would be Multiplexer latency + Comparator Latency?
Sumiran Agrawal
3.6k
views
Sumiran Agrawal
asked
May 16, 2019
CO and Architecture
co-and-architecture
icache-memory
direct-mapping
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–
0
votes
1
answer
8
Self doubt about LRU and Direct mapping cache
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned ...
S Ram
490
views
S Ram
asked
Jan 12, 2019
CO and Architecture
cache-memory
direct-mapping
co-and-architecture
+
–
0
votes
0
answers
9
Self Doubt
What does additional memory for tags refer to in Direct Mapping, Associative Mapping and Set- Associative Mapping?
What does additional memory for tags refer to in Direct Mapping, Associative Mapping and Set- Associative Mapping?
manisha11
215
views
manisha11
asked
Jan 5, 2019
CO and Architecture
co-and-architecture
cache-memory
direct-mapping
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–
0
votes
0
answers
10
Direct Mapping
what’s the answer here ...unable to understand their solution. and also shouldn’t be the reason like this For R to be true: “ A unique cache page is associated with every main memory page in direct mapped caches. “
what’s the answer here ...unable to understand their solution.and also shouldn’t be the reason like this For R to be true: “ A unique cache page is associated with ...
Ashwani Yadav
667
views
Ashwani Yadav
asked
Dec 20, 2018
CO and Architecture
cache-memory
direct-mapping
co-and-architecture
+
–
1
votes
0
answers
11
Direct Mapping and set associative Mapping
https://gateoverflow.in/1851/gate2006-74 https://gateoverflow.in/43565/gate2006-75 can someone check this questions ? i am not getting, how without help of MULTIPLEXER or DECODER, we are searching hit/miss i mean in direct mapping, how we select lines and their respective Tags without help of Multiplexer ?
https://gateoverflow.in/1851/gate2006-74https://gateoverflow.in/43565/gate2006-75can someone check this questions ?i am not getting, how without help of MULTIPLEXER or DE...
Shaik Masthan
2.4k
views
Shaik Masthan
asked
Dec 18, 2018
CO and Architecture
cache-memory
direct-mapping
comparators
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–
0
votes
1
answer
12
MadeEasy Test Series: CO & Architecture - Cache Memory
A : LRU replacement policy is not applicable to direct mapped caches B : A unique memory page is associated with every cache page in direct mapped caches Options: 1) Both True 2) Both False 3) A is True and B is false 4) B is True and A is false
A : LRU replacement policy is not applicable to direct mapped cachesB : A unique memory page is associated with every cache page in direct mapped cachesOptions:1) Both Tr...
jatin khachane 1
2.3k
views
jatin khachane 1
asked
Dec 6, 2018
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
direct-mapping
+
–
1
votes
1
answer
13
GA Test Series
answer is 1.. but I’m getting more than 1
answer is 1.. but I’m getting more than 1
aditi19
458
views
aditi19
asked
Dec 6, 2018
CO and Architecture
test-series
cache-memory
direct-mapping
+
–
4
votes
2
answers
14
Cache Mapping
Na462
840
views
Na462
asked
Oct 1, 2018
CO and Architecture
co-and-architecture
cache-memory
direct-mapping
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–
1
votes
0
answers
15
Cache-tag-directory
What is the size of tag in cache directory for direct and set-associative memory? For set-associative memory do we multiply by no of sets or no of blocks? According to me Size of Tag in cache directory = Number of tag bits(+ any extra bits like valid, ... = Number of tag bits(+ any extra bits like valid, modified etc) * number of sets Tag is associated with each block or set?
What is the size of tag in cache directory for direct and set-associative memory?For set-associative memory do we multiply by no of sets or no of blocks?According to meSi...
Apoorva Jain
1.4k
views
Apoorva Jain
asked
Sep 2, 2018
CO and Architecture
cache-memory
co-and-architecture
direct-mapping
set-associative-mapping
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–
0
votes
0
answers
16
Direct Map Cache
Ans. 1
Ans. 1
Na462
615
views
Na462
asked
Aug 4, 2018
CO and Architecture
co-and-architecture
cache-memory
direct-mapping
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–
0
votes
1
answer
17
No. of Misses
Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block of 16 bytes. In case of direct mapped cache, the number of cache misses are _______ (Assume that cache is empty initially). Ans. 1288
Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block ...
Na462
893
views
Na462
asked
Jul 29, 2018
CO and Architecture
co-and-architecture
misses
cache-memory
direct-mapping
+
–
3
votes
1
answer
18
MadeEasy Test Series: CO & Architecture - Cache Memory
The statement " Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value." is true or false ?
The statement " Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value." is true or false ?
ashish pal
1.9k
views
ashish pal
asked
Dec 31, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
direct-mapping
cache-memory
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–
0
votes
1
answer
19
why comparator is used in Direct mapping technique,why can't we use simple And gate here?
sourav chatterjee
1.5k
views
sourav chatterjee
asked
Dec 16, 2017
CO and Architecture
cache-memory
direct-mapping
+
–
1
votes
1
answer
20
CACHE direct mapping
Parshu gate
1.5k
views
Parshu gate
asked
Nov 6, 2017
CO and Architecture
cache-memory
direct-mapping
co-and-architecture
+
–
2
votes
0
answers
21
Doubt in direct cache mapping
The direct mapped cache uses M main memory blocks and N cache blocks, for a given Physical Address it resulted T tag bits and placed in P cache block. Which main memory words May respond to this Physical Address? Block size is P words.
The direct mapped cache uses M main memory blocks and N cache blocks, for a given Physical Address it resulted T tag bits and placed in P cache block. Which main memory w...
AnilGoudar
464
views
AnilGoudar
asked
Oct 18, 2017
CO and Architecture
cache-memory
direct-mapping
co-and-architecture
+
–
4
votes
1
answer
22
Conflict misses doubt.
I read that if block size increases, then we have fewer blocks so number of conflict misses increases. My doubt is how will the conflict misses increase ? If cache size is constant, then by increasing block size we have fewer blocks but SAME TAG ... blocks that would be mapped to each line of cache would be same and hence number of conflict misses should remain same right?
I read that if block size increases, then we have fewer blocks so number of conflict misses increases.My doubt is how will the conflict misses increase ? If cache size is...
Xylene
1.3k
views
Xylene
asked
Aug 6, 2017
CO and Architecture
misses
co-and-architecture
direct-mapping
+
–
0
votes
2
answers
23
Gateforum Test Series: CO & Architecture - cache memory
Assume a cache of $2K$ blocks ( 1 block size = 4 words= 16 bytes) and $32-bit$ address. Assume this machine is byte addressable. What is the bit length of each field in direct mapped? $(A).\space 19,11,2$ $(B).\space 20,11,2$ $(C).\space 21,9,2$ $(D). \text{none of these}$
Assume a cache of $2K$ blocks ( 1 block size = 4 words= 16 bytes) and $32-bit$ address. Assume this machine is byte addressable.What is the bit length of each field in di...
Satyajeet Singh
1.9k
views
Satyajeet Singh
asked
Jun 14, 2017
CO and Architecture
co-and-architecture
cache-memory
direct-mapping
gateforum
+
–
5
votes
1
answer
24
True or false
$S_1$: When the write-through protocol used in the simultaneous access memory organization then the hit ratio for write request is 100%. $S_2$: Conflict and Inference misses can be reduced by double the associativity of a cache design. $S_3$: In ... are required in the direct, associative and set associative cache designs to replace the cache blocks. Which of the following is false?
$S_1$: When the write-through protocol used in the simultaneous access memory organization then the hit ratio for write request is 100%.$S_2$: Conflict and Inference miss...
Supremo
2.3k
views
Supremo
asked
Jan 30, 2017
CO and Architecture
cache-memory
write-through
write-back
direct-mapping
+
–
16
votes
0
answers
25
Discussion regarding Cache Memory
What is the size of $MUX$ needed in direct mapped cache ? For ex :- | Tag = $17$ | line = $10$ | word = $5$ | Diagram Reference :- Direct mapped cache with multi word block In set associative cache, Do MUX and OR ... MUX and OR gate work parallely, then Hit latency includes both delays ? Diagram Reference :- - Also, any reason/explaination regarding below image ?
What is the size of $MUX$ needed in direct mapped cache ?For ex :- | Tag = $17$ | line = $10$ | word = $5$ |Diagram Reference :- Direct mapped cache with multi word bloc...
Kapil
2.4k
views
Kapil
asked
Jan 21, 2017
CO and Architecture
cache-memory
co-and-architecture
direct-mapping
+
–
0
votes
1
answer
26
tag directory size in direct mapping
how to calculate tag directory size in direct cache mapping... is it number of lines * tag bits??
how to calculate tag directory size in direct cache mapping...is it number of lines * tag bits??
vineet.ildm
2.5k
views
vineet.ildm
asked
Nov 27, 2016
CO and Architecture
cache-memory
direct-mapping
+
–
2
votes
2
answers
27
MadeEasy Test Series: CO & Architecture - Cache Memory
Consider the direct mapped cache organization which consists of m-lines with a line size of 2w words/ bytes. Main memory address can be viewed as consisting of three fields. The least significant w-bits identify a unique word within the block of main memory. ... answer would be 1,2,3, ... (m-1) but now i am confused what is asked in this ques.
Consider the direct mapped cache organization which consists of m-lines with a line size of 2w words/ bytes. Main memory address can be viewed as consisting of three fiel...
khushtak
1.1k
views
khushtak
asked
Jan 21, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
direct-mapping
+
–
1
votes
0
answers
28
MadeEasy Test Series: CO & Architecture - Cache Memory
[MADEEASY] Consider a cache as follows : - Direct Mapped - 16 words total cache size - 4 words cache block size A sequence of 9 memory reads is performed in order from following addresses 2, 13, 6, 16, 11, 3, 10, 2, 13. What is maximum number of ... (in block 0) 13 => 011 | 01 - Hit (in block 3) Its giving (D) But answer is given as (C).
[MADEEASY]Consider a cache as follows :- Direct Mapped - 16 words total cache size - 4 words cache block sizeA sequence of 9 memory reads is performed in order fr...
Tushar Shinde
592
views
Tushar Shinde
asked
Jan 14, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
direct-mapping
+
–
0
votes
2
answers
29
Direct Mapped Cache
If we are given direct mapped cache, we have to add Multiplexer delay to the comparator delay ?
If we are given direct mapped cache, we have to add Multiplexer delay to the comparator delay ?
Mojo-Jojo
1.3k
views
Mojo-Jojo
asked
Jan 11, 2016
CO and Architecture
co-and-architecture
cache-memory
direct-mapping
+
–
12
votes
3
answers
30
direct mapping and types of misses
Consider a cache as follows: Direct mapped 8 words total cache data size 2 words block size A sequence of eight memory read is performed in the order shown from the following addresses: 0 , 11 , 4 , 14 , 9 , 1 , 8 , 0 Calculate No. of misses No of compulsory misses No. of conflict misses No. of capacity misses
Consider a cache as follows:Direct mapped8 words total cache data size2 words block sizeA sequence of eight memory read is performed in the order shown from the following...
khushtak
6.4k
views
khushtak
asked
Dec 15, 2015
CO and Architecture
direct-mapping
misses
cache-memory
co-and-architecture
+
–
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