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Recent questions tagged direct-mapping

1 vote

1 answer

1

Zeal Test
Question : Consider a system with 20 bit physical address and direct mapped cache with 64 blocks and block size of 16 bytes To what block number does byte address 1200 mapped??

lalitver10 asked in CO and Architecture Aug 19, 2022

370 views

11 votes

2 answers

2

GATE CSE 2022 | Question: 44
Consider a system with $2 \;\text{KB}$ direct mapped data cache with a block size of $64 \; \text{bytes}.$ The system has a physical address space of $64 \; \text{KB}$ and a word length of $16 \; \text{bits.}$ During the execution of a program, four data ... only $\text{R}$ and $\text{S}$ reside in the cache. Every access to $\text{R}$ evicts $\text{Q}$ from the cache.

Arjun asked in CO and Architecture Feb 15, 2022

by Arjun

4.3k views

6 votes

5 answers

3

ISRO2020-47
How many total bits are required for a direct-mapped cache with $128$ KB of data and $1$ word block size, assuming a $32$-bit address and $1$ word size of $4$ bytes? $2$ Mbits $1.7$ Mbits $2.5$ Mbits $1.5$ Mbits

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

4.4k views

0 votes

2 answers

4

Direct Mapped Cache Multiplexer
Is there any multiplexer(s) present in the implementation of Direct Mapped Cache? If yes, then the Hit latency would be Multiplexer latency + Comparator Latency?

Sumiran Agrawal asked in CO and Architecture May 16, 2019

by Sumiran Agrawal

2.9k views

0 votes

1 answer

5

Self doubt about LRU and Direct mapping cache
Can we apply LRU policy to direct mapped cache. according to me it doesn't make any sense as eventually it will be like FIFO only as unique memory addresses are assigned to each cache line. But my doubt / confusion is can we implement LRU on direct mapped caches?

S Ram asked in CO and Architecture Jan 12, 2019

by S Ram

404 views

0 votes

0 answers

6

Self Doubt
What does additional memory for tags refer to in Direct Mapping, Associative Mapping and Set- Associative Mapping?

manisha11 asked in CO and Architecture Jan 5, 2019

134 views

0 votes

0 answers

7

Direct Mapping
what’s the answer here ...unable to understand their solution. and also shouldn’t be the reason like this For R to be true: “ A unique cache page is associated with every main memory page in direct mapped caches. “

Ashwani Yadav asked in CO and Architecture Dec 20, 2018

by Ashwani Yadav

420 views

1 vote

0 answers

8

Direct Mapping and set associative Mapping
https://gateoverflow.in/1851/gate2006-74 https://gateoverflow.in/43565/gate2006-75 can someone check this questions ? i am not getting, how without help of MULTIPLEXER or DECODER, we are searching hit/miss i mean in direct mapping, how we select lines and their respective Tags without help of Multiplexer ?

Shaik Masthan asked in CO and Architecture Dec 18, 2018

by Shaik Masthan

1.7k views

0 votes

1 answer

9

MadeEasy Test Series: CO & Architecture - Cache Memory
A : LRU replacement policy is not applicable to direct mapped caches B : A unique memory page is associated with every cache page in direct mapped caches Options: 1) Both True 2) Both False 3) A is True and B is false 4) B is True and A is false

jatin khachane 1 asked in CO and Architecture Dec 6, 2018

by jatin khachane 1

1.8k views

1 vote

1 answer

10

GA Test Series
answer is 1.. but I’m getting more than 1

aditi19 asked in CO and Architecture Dec 6, 2018

311 views

4 votes

2 answers

11

Na462 asked in CO and Architecture Oct 1, 2018

by Na462

556 views

1 vote

0 answers

12

Cache-tag-directory
What is the size of tag in cache directory for direct and set-associative memory? For set-associative memory do we multiply by no of sets or no of blocks? According to me Size of Tag in cache directory = Number of tag bits(+ any extra bits like valid, ... = Number of tag bits(+ any extra bits like valid, modified etc) * number of sets Tag is associated with each block or set?

Apoorva Jain asked in CO and Architecture Sep 2, 2018

by Apoorva Jain

1.2k views

0 votes

0 answers

13

Direct Map Cache
Ans. 1

Na462 asked in CO and Architecture Aug 4, 2018

by Na462

399 views

0 votes

1 answer

14

No. of Misses
Assume that we have a two dimensional array of 60 × 60. Each element is of 4 bytes and array is stored in row major order. RAM is 2 MB and cache is 8 KB with each block of 16 bytes. In case of direct mapped cache, the number of cache misses are _______ (Assume that cache is empty initially). Ans. 1288

Na462 asked in CO and Architecture Jul 29, 2018

by Na462

669 views

3 votes

1 answer

15

MadeEasy Test Series: CO & Architecture - Cache Memory
The statement " Direct mapped cache, may produce more misses if programs refers to memory words that occupy a same tag value." is true or false ?

ashish pal asked in CO and Architecture Dec 31, 2017

1.5k views

0 votes

1 answer

16

why comparator is used in Direct mapping technique,why can't we use simple And gate here?

sourav chatterjee asked in CO and Architecture Dec 16, 2017

by sourav chatterjee

1.2k views

1 vote

1 answer

17

CACHE direct mapping

Parshu gate asked in CO and Architecture Nov 6, 2017

1.3k views

2 votes

0 answers

18

Doubt in direct cache mapping
The direct mapped cache uses M main memory blocks and N cache blocks, for a given Physical Address it resulted T tag bits and placed in P cache block. Which main memory words May respond to this Physical Address? Block size is P words.

AnilGoudar asked in CO and Architecture Oct 19, 2017

357 views

4 votes

1 answer

19

Conflict misses doubt.
I read that if block size increases, then we have fewer blocks so number of conflict misses increases. My doubt is how will the conflict misses increase ? If cache size is constant, then by increasing block size we have fewer blocks but SAME TAG ... blocks that would be mapped to each line of cache would be same and hence number of conflict misses should remain same right?

Xylene asked in CO and Architecture Aug 6, 2017

by Xylene

929 views

0 votes

2 answers

20

Gateforum Test Series: CO & Architecture - cache memory
Assume a cache of $2K$ blocks ( 1 block size = 4 words= 16 bytes) and $32-bit$ address. Assume this machine is byte addressable. What is the bit length of each field in direct mapped? $(A).\space 19,11,2$ $(B).\space 20,11,2$ $(C).\space 21,9,2$ $(D). \text{none of these}$

Satyajeet Singh asked in CO and Architecture Jun 14, 2017

by Satyajeet Singh

1.4k views

5 votes

1 answer

21

True or false
$S_1$: When the write-through protocol used in the simultaneous access memory organization then the hit ratio for write request is 100%. $S_2$: Conflict and Inference misses can be reduced by double the associativity of a cache design. $S_3$: In ... are required in the direct, associative and set associative cache designs to replace the cache blocks. Which of the following is false?

Supremo asked in CO and Architecture Jan 30, 2017

1.8k views

16 votes

0 answers

22

Discussion regarding Cache Memory
What is the size of $MUX$ needed in direct mapped cache ? For ex :- | Tag = $17$ | line = $10$ | word = $5$ | Diagram Reference :- Direct mapped cache with multi word block In set associative cache, Do MUX and OR ... MUX and OR gate work parallely, then Hit latency includes both delays ? Diagram Reference :- - Also, any reason/explaination regarding below image ?

Kapil asked in CO and Architecture Jan 21, 2017

by Kapil

2.0k views

0 votes

1 answer

23

tag directory size in direct mapping
how to calculate tag directory size in direct cache mapping... is it number of lines * tag bits??

vineet.ildm asked in CO and Architecture Nov 27, 2016

2.1k views

1 vote

2 answers

24

MadeEasy Test Series: CO & Architecture - Cache Memory
Consider the direct mapped cache organization which consists of m-lines with a line size of 2w words/ bytes. Main memory address can be viewed as consisting of three fields. The least significant w-bits identify a unique word within the block of main memory. ... answer would be 1,2,3, ... (m-1) but now i am confused what is asked in this ques.

khushtak asked in CO and Architecture Jan 21, 2016

812 views

1 vote

0 answers

25

MadeEasy Test Series: CO & Architecture - Cache Memory
[MADEEASY] Consider a cache as follows : - Direct Mapped - 16 words total cache size - 4 words cache block size A sequence of 9 memory reads is performed in order from following addresses 2, 13, 6, 16, 11, 3, 10, 2, 13. What is maximum number of ... (in block 0) 13 => 011 | 01 - Hit (in block 3) Its giving (D) But answer is given as (C).

Tushar Shinde asked in CO and Architecture Jan 14, 2016

by Tushar Shinde

425 views

0 votes

2 answers

26

Direct Mapped Cache
If we are given direct mapped cache, we have to add Multiplexer delay to the comparator delay ?

Mojo-Jojo asked in CO and Architecture Jan 11, 2016

1.1k views

12 votes

3 answers

27

direct mapping and types of misses
Consider a cache as follows: Direct mapped 8 words total cache data size 2 words block size A sequence of eight memory read is performed in the order shown from the following addresses: 0 , 11 , 4 , 14 , 9 , 1 , 8 , 0 Calculate No. of misses No of compulsory misses No. of conflict misses No. of capacity misses

khushtak asked in CO and Architecture Dec 15, 2015

5.1k views

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Recent questions tagged direct-mapping