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Recent questions tagged dma

3 votes
1 answer
1
Consider a computer system with $\text{DMA}$ support. The $\text{DMA}$ module is transferring one $8$-bit character in one $\text{CPU}$ cycle from a device to memory through cycle stealing at regular intervals. Consider a $\text{2 MHz}$ processor. If $0.5 \%$ processor cycles are used for $\text{DMA}$, the data transfer rate of the device is __________ bits per second.
asked Feb 18 in CO and Architecture Arjun 1.1k views
0 votes
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One mode that some DMA controllers use is to have the device controller send the word to the DMA controller, which then issues a second bus request to write to memory. How can this mode be used to perform memory to memory copy? Discuss any advantage or disadvantage of using this method instead of using the CPU to perform memory to memory copy.
asked Oct 28, 2019 in Operating System Lakshman Patel RJIT 149 views
2 votes
1 answer
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Suppose that a system uses DMA for data transfer from disk controller to main memory. Further assume that it takes $t_{1}\: nsec$ on average to acquire the bus and $t_{2}\:nsec$ to transfer one word over the bus $(t_{1} >> t_{2}).$ ... that commanding the disk controller requires acquiring the bus to send one word and acknowledging a transfer also requires acquiring the bus to send one word.
asked Oct 28, 2019 in Operating System Lakshman Patel RJIT 255 views
2 votes
1 answer
4
A DMA controller has five channels. The controller is capable of requesting a $32$-bit word every $40\: nsec.$ A response takes equally long. How fast does the bus have to be to avoid being a bottleneck?
asked Oct 28, 2019 in Operating System Lakshman Patel RJIT 466 views
1 vote
2 answers
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2 votes
3 answers
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1 vote
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7
I was going through this problem: Consider a disk drive with the following specifications: 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in cycle stealing mode whereby whenever one 4 byte word is ... intermediate buffer wherein we empty the disk buffer. And only after 4B are there in intermediate buffer, we send it over system bus.
asked Jan 7, 2019 in CO and Architecture Raj Singh 1 255 views
1 vote
2 answers
8
True/false 1. To access bus the DMA does not issue an interrupt it is done through DMA-request and DMA-acknowledge wires. Interrupt is issued by DMA to CPU only after complete data is transferred to the specific memory address by DMA. 2. DMA interrupts the CPU whenever it needs to initiate I/O and also when it has finished I/O transfers.
asked Jan 4, 2019 in CO and Architecture Gurdeep Saini 466 views
1 vote
2 answers
9
If the disk is rotating at 3600rpm, determine the effective data transfer rate at which is defined as the number of bytes transfered per second between disk and memory. (Given size of track = 512 bytes)?
asked Dec 31, 2018 in CO and Architecture nitesh_scorpio 1.3k views
3 votes
1 answer
10
A hard disk with a transfer rate of 1 KBps is constantly transferring data to memory using DMA cycle stealing mode. The size of the data transfer is 16 bytes. The processor runs at 400 kHz clock frequency. The DMA controller requires 10 cycles for initialization ... and preparation time as 0.9375 sec and percentage time CPU gets blocked = transfer time/preparation time (IN case of cycle stealing)
asked Dec 28, 2018 in CO and Architecture Shivam Kasat 822 views
0 votes
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11
a system employing interrupt-driven I/O for a particular device that transfers data at an average of 8 KB/s on a continuous basis. a. Assume that interrupt processing takes about 100 s (i.e., the time to jump to the interrupt service routine (ISR), execute it, and ... i'm getting 216/500 and 188/500 respectively. please check it. (i've taken K=1000 instead of 1024 for simplicity of calculation).
asked Dec 9, 2018 in CO and Architecture aambazinga 444 views
1 vote
0 answers
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can someone explain what is preparation time in DMA exactly? and why is it multiplied by CPU cycle time in most of the questions here? does preparation time means that a word is brought into disk controller buffer from hard disk and it utilizes CPU? PS-DMA is giving me headaches!!!
asked Dec 8, 2018 in CO and Architecture aditi19 268 views
0 votes
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13
Which of the following mode of data transfer uses Interrupt mechanism ? (More then may be correct) Programmed I/O Interrupt Driven data transfer DMA Mode Asynchronous I/O Synchronous I/O None of the above
asked Dec 8, 2018 in CO and Architecture Na462 335 views
1 vote
1 answer
14
Consider a device of 1MBPS is operating in a cycle stealing mode of DMA .Whenever 16 B word is available it is transferred into memory in 4 microseconds. What is the % of time the processor is blocked due to DMA? a) 10% b) 20% c) 80% d) 90%
asked Nov 20, 2018 in CO and Architecture Avir Singh 661 views
0 votes
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15
Consider x = CPU time or data preparation time = 1 microsecond and y = data transfer time from DISK to DMA = 21 microseconds. % of memory cycles stolen = 1/(21) * 100 = 4.76% Doubt - For each 21 memory cycle, 1 memory cycle will be taken to transfer data. CPU can do its own work for 20 memory cycles and 1 memory cycle it will remain idle. What does this CPU cycle stealing means ?
asked Oct 5, 2018 in CO and Architecture iarnav 1.1k views
2 votes
1 answer
16
Consider ​y μs is cycle time / transfer time (for memory) x μs is data transfer time / preparation time (for disk) then % of time CPU idle in CYCLE STEALING MODE is = y/x and % of time CPU idle in Burst MODE is = (y)/(x+y) May someone please explain how is this Cpu idle time is calculated in both cycle stealing time and burst mode
asked Oct 5, 2018 in CO and Architecture iarnav 738 views
1 vote
0 answers
17
Consider sending a large file of $360,000$ bits from Host $A$ to Host $B,$ connected through a router, as shown in the below figure $2.$ Assume that there is no queuing and propagation delay, and the router has sufficient buffer space. Host $A$ ... assume that transferring one byte involves $4$ operations: in-status, check-status, branch and read/write in memory, each requiring one machine cycle.
asked Sep 18, 2018 in Computer Networks jothee 164 views
0 votes
2 answers
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19
Locality of Reference is use Cache Memory but not DMA. Why? I mean atleast temporal locality should use DMA. as definition of temporal locaity is "Temporal locality refers to the reuse of specific data, and/or resources, within a relatively small time duration" So, it can use direct memory . right?
asked Jul 25, 2018 in Operating System srestha 202 views
0 votes
0 answers
20
Consider 8-bit DMA device operating in cycle stealing mode (Single Transfer Mode). Each DMA cycle takes 6 clock and each clock is of 2 MHz. An intermediate CPU machine cycle take 2 μsec. What is the data transfer rate of DMA? Ans. 200 KB/sec
asked Jul 23, 2018 in CO and Architecture Na462 572 views
0 votes
1 answer
21
In DMA, there are two modes of transferring data: burst and cycle stealing. Also, there are two states of CPU when operating DMA: either it's blocked or consumed. I want to know whether CPU is blocked or consumed when operating in burst mode, and same for cycle stealing mode.
asked Jul 5, 2018 in CO and Architecture habedo007 247 views
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22
DMA is mainly used to control faster processor activity. Then how processor time slows down by a DMA activity?
asked Jul 3, 2018 in CO and Architecture srestha 195 views
1 vote
1 answer
23
State whether the following statement is TRUE or FALSE and why ? In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive simultaneously, the microprocessor attends first to the bus request.
asked May 4, 2018 in CO and Architecture ankitgupta.1729 577 views
0 votes
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Please help me with this question.. The CPU of a system having an execution rate of 1 million instructions per second needs 4 machine cycles on an average for executing an instruction. On an average, 50% of the cycles use memory bus. For execution of the ... that transferring one byte involves 4 operations: in-status, check-status, branch and read/write in memory, each requiring one machine cycle.
asked May 4, 2018 in CO and Architecture Vikram Saurabh 235 views
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