Recent questions tagged dma / GATE Overflow for GATE CSE

1 votes

2 answers

61

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 1
A DMA module is transferring bytes to memory using cycle stealing mode from a device transmitting at $16$ KB/s. The processor is fetching instructions at the rate of $1$ MB/s. The percentage by which the processor will be slowed down due to the DMA activity is ______

A DMA module is transferring bytes to memory using cycle stealing mode from a device transmitting at $16$ KB/s. The processor is fetching instructions at the rate of $1$ ...

Bikram

831 views

Bikram asked May 27, 2017

0 votes

1 answer

62

[CO] DMA
When the DMA transfer is taking place then what is processor doing at that time?

When the DMA transfer is taking place then what is processor doing at that time?

rahul sharma 5

466 views

rahul sharma 5 asked May 22, 2017

1 votes

1 answer

63

Test by Bikram | Mock GATE | Test 4 | Question: 52
A DMA module transfers characters to memory (using cycle stealing mode) from a device transmitting at 8800 bps. The processor fetches instructions at the rate of $1$ million instructions per second (1 MIPS). The processor will be slowed down due to the DMA activity by _______ % ( up to 2 decimal places ).

A DMA module transfers characters to memory (using cycle stealing mode) from a device transmitting at 8800 bps. The processor fetches instructions at the rate of $1$ mill...

Bikram

495 views

Bikram asked May 14, 2017

20 votes

2 answers

64

COA DMA doubt
What is formula for % of time CPU gets blocked?? Is it X(X+Y) or X/Y only??? What is formula for % of time CPU is consumed in Interuppt driven IO??? Formula for % of CPU slow down in interrupt driven IO???

What is formula for % of time CPU gets blocked??Is it X(X+Y) or X/Y only???What is formula for % of time CPU is consumed in Interuppt driven IO??? Formula for % of CPU s...

Rahul Jain25

10.6k views

Rahul Jain25 asked Feb 6, 2017

1 votes

2 answers

65

MadeEasy Test Series

AmitPatil

626 views

AmitPatil asked Feb 2, 2017

12 votes

4 answers

66

MadeEasy Subject Test: CO & Architecture - Dma
Consider $1 \text{ MBPS}$ hard disk is interfaced to the processor in a cycle stealing mode of $\text{DMA}$ whenever $64$ bytes of the data is available in the buffer then it is transferred to the main memory. Processor word length is $64$ bits ... $\text{CPU}$ time is consumed for the $\text{DMA}$ operation is ________ (in $\%$).

Consider $1 \text{ MBPS}$ hard disk is interfaced to the processor in a cycle stealing mode of $\text{DMA}$ whenever $64$ bytes of the data is available in the buffer the...

vaishali jhalani

4.1k views

vaishali jhalani asked Jan 30, 2017

1 votes

2 answers

67

MadeEasy Subject Test: CO & Architecture - Dma
I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. before and after that it can do its own work. Where am I wrong?

I have gone through these types of questions but I'm unable to understand. how to appraoch these questions? And during the dma transfer, cpu is considered to be idle. bef...

sidsunny

867 views

sidsunny asked Jan 26, 2017

0 votes

0 answers

68

MadeEasy Subject Test: CO & Architecture - Dma

vaishali jhalani

325 views

vaishali jhalani asked Jan 25, 2017

0 votes

1 answer

69

MadeEasy Subject Test: CO & Architecture - Dma

debanjan sarkar

342 views

debanjan sarkar asked Jan 24, 2017

3 votes

2 answers

70

Test by Bikram | Mock GATE | Test 2 | Question: 41
A $DMA$ module is transferring bytes to memory using cycle stealing mode from a device transmitting at $16 KB/s$. The processor is fetching instructions at the rate of $1 MB/s$. The percentage by which the processor will be slowed down due to the $DMA$ activity is ______.

A $DMA$ module is transferring bytes to memory using cycle stealing mode from a device transmitting at $16 KB/s$. The processor is fetching instructions at the rate of $1...

Bikram

902 views

Bikram asked Jan 24, 2017

1 votes

2 answers

71

MadeEasy CBT 2017: CO & Architecture - Dma

Dulqar

655 views

Dulqar asked Jan 22, 2017

1 votes

1 answer

72

dma2 madeeasy TB
An i/o device transfers data at the rate of 10 MBPS over a 100 MBPS bus. The data is transferred in 4 KB blocks.if the processor operates at 500 megahertz and it takes a total of 5000 cycles to handle is DMA request find the fraction of CPU time handling the transfer with and without DMA.

An i/o device transfers data at the rate of 10 MBPS over a 100 MBPS bus. The data is transferred in 4 KB blocks.if the processor operates at 500 megahertz and it takes a ...

khushtak

444 views

khushtak asked Jan 19, 2017

2 votes

1 answer

73

dma1 madeEasy TB
a hard drive with a maximum transfer rate of 1 Mbytes per second is connected to a 32bit ,10MIps CPU operating at a clock frequency of 100megahertz .Assume that the IO interface is DMA based and it takes 500 clock cycles for the CPU to set up ... data transfer is done using 2KB blocks, calculate the percentage of CPU TIME consumed in Handling the hard drive. Plz explain the answer.

a hard drive with a maximum transfer rate of 1 Mbytes per second is connected to a 32bit ,10MIps CPU operating at a clock frequency of 100megahertz .Assume that the IO in...

khushtak

990 views

khushtak asked Jan 19, 2017

1 votes

0 answers

74

significance of dma
what is signified by the term direct memory access DMA? A) an efficient IO mechanism when interrupts for single by transfer operation b) a class of multiprocessor computer C) a mechanism used by I/o system to bypass the memory management function to an Operating System D) a more efficient and mechanism then program to follow by transfer operation.

what is signified by the term direct memory access DMA?A) an efficient IO mechanism when interrupts for single by transfer operationb) a class of multiprocessor computer ...

khushtak

1.1k views

khushtak asked Jan 19, 2017

1 votes

1 answer

75

MadeEasy Subject Test: CO & Architecture - Dma

harkirat31

304 views

harkirat31 asked Jan 18, 2017

0 votes

0 answers

76

Direct memory acess
Consider a system in which bus cycle takes 500 ns. Transfer of bus control in either direction, from processor to device or vice-versa, takes 250 ns.One of the IO device has data transfer rate of 75 KB/sec and employs DMA. Data are transfer red one ... block of 256 bytes? b) calculate the same for cycle stealing mode Please explain in which mode we use bus cycle time and why?

Consider a system in which bus cycle takes 500 ns. Transfer of bus control in either direction, from processor to device or vice-versa, takes 250 ns.One of the IO device ...

Geet

534 views

Geet asked Jan 6, 2017

1 votes

1 answer

77

DMA Cycle stealing
Explain in detail?

Explain in detail?

Prajwal Bhat

1.5k views

Prajwal Bhat asked Dec 21, 2016

0 votes

0 answers

78

MadeEasy Subject Test: CO & Architecture - Dma
Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing mode where by whenever 1 B word is ready it is sent ... for each memory cycle is 50 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is __________ .

Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing...

Kai

244 views

Kai asked Dec 19, 2016

0 votes

1 answer

79

Register data transfer
Registers R1 and R2 contain memory address and data to be written in that memory adress respectively. To execute the instruction that transfers content of R2 to memory adress pointed by R1 we would first need to transfer content of R1 to MAR and R2 to MDR. MAR <- R1 MDR <- R2 Can both of these operations be performed in same clock cycle?

Registers R1 and R2 contain memory address and data to be written in that memory adress respectively. To execute the instruction that transfers content of R2 to memory ad...

Rakesh K

751 views

Rakesh K asked Dec 9, 2016

0 votes

2 answers

80

CPU blocked time in DMA
Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing mode where by whenever 1 B word is ready it is sent to memory, ... . The time for each memory cycle is 50 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is ______

Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing...

Sanket_

640 views

Sanket_ asked Dec 6, 2016

0 votes

0 answers

81

DMA-VG
Consider a hard disk which when requested to read a sector of 2048 bytes, first reads into its own local memory, and then uses DMA to transfer it to the main memory over a bus. The latency of access of both memories is 80ns each. The bus is ... and both memories are 16 bytes wide each. How long does it take to complete the transfer? All possible pipelining between stages is implemented.

Consider a hard disk which when requested to read a sector of 2048 bytes, first reads into its own local memory, and then uses DMA to transfer it to the main memory over ...

srestha

320 views

srestha asked Dec 1, 2016

0 votes

2 answers

82

DMA madeeasy
Here device transfer rate is 416.7 us and cpu executing an instruction in .5 us. So how to decide the clock cycle time, to calculate the fraction of cpu slows down?

Here device transfer rate is 416.7 us and cpu executing an instruction in .5 us.So how to decide the clock cycle time, to calculate the fraction of cpu slows down?

vaishali jhalani

1.2k views

vaishali jhalani asked Nov 28, 2016

3 votes

2 answers

83

Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 23
A hard disk is connected to a $2$ GHz processor through a DMA controller which works in burst mode. The initial set up of a DMA transfer takes $1000$ ... is $16$ KB. Then, the fraction of CPU time free if the disk is transferring data is _______%.

A hard disk is connected to a $2$ GHz processor through a DMA controller which works in burst mode. The initial set up of a DMA transfer takes $1000$ clock cycles for the...

Bikram

1.1k views

Bikram asked Nov 25, 2016

0 votes

2 answers

84

Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 17
The fastest mode of data transfer is: Programmable I/O Interrupt I/O DMA Both A and B

The fastest mode of data transfer is:Programmable I/OInterrupt I/ODMABoth A and B

Bikram

479 views

Bikram asked Nov 25, 2016

2 votes

1 answer

85

IIT m november 2016
A DMA needs 5 clock cycle to transfer 8 byte data.how many clock needed to transfer 1024 byte of data ,if burst transfer is not used

A DMA needs 5 clock cycle to transfer 8 byte data.how many clock needed to transfer 1024 byte of data ,if burst transfer is not used

Aboveallplayer

852 views

Aboveallplayer asked Nov 23, 2016

27 votes

2 answers

86

Hamacher-DMA
The average seek time and rotational delay in a disk system are 6ms and 3ms, respectively. The rate of data transfer to or from the disk is 30 Mbytes/sec and all disk accesses are for 8 Kbytes of data. Disk DMA controller, the processor and the main ... stolen by a disk unit, on average over a long period of time during which a sequence of independent 8K-byte transfers takes place?

The average seek time and rotational delay in a disk system are 6ms and 3ms, respectively. The rate of data transfer to or from the disk is 30 Mbytes/sec and all disk ac...

srestha

5.4k views

srestha asked Nov 20, 2016

2 votes

2 answers

87

DMA anc CPU idle time
Which of the following statements is / are true? A. In DMA approach CPU never gets idle for data transfer. B. In DMA approach, CPU becomes idle whenever DMA controller steals cycle. C. In DMA approach,DMA controller accepts a data transfer ... completing last data transfer request D. In DMA approach, CPU can proceed in parallel, only if next instructions do not need bus

Which of the following statements is / are true?A. In DMA approach CPU never gets idle for data transfer.B. In DMA approach, CPU becomes idle whenever DMA controller stea...

sh!va

2.8k views

sh!va asked Nov 4, 2016

–4 votes

0 answers

88

COA Interface
What is this RS – 232 interface . Somebody please explain in easy words please

What is this RS – 232 interface . Somebody please explain in easy words please

LavTheRawkstar

853 views

LavTheRawkstar asked Nov 3, 2016

1 votes

1 answer

89

DMA transfer time
Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address register Decrement the count If count !=0 go to LOOP This is a code to transfer 500 B from ... to transfer one byte of data from the device to the memory. Calculate the DMA transfer time . % time processor is busy

Initialize the address register Initialize the count to 500 LOOP: Load a byte from device Store in memory at address given by address register Increment the address regis...

PEKKA

2.1k views

PEKKA asked Nov 3, 2016

15 votes

3 answers

90

DMA -cycle stealing
Consider a system in which bus cycle takes 100 ns. Transfer of bus control from processor to device or device to processor, takes 250 ns. One of the IO device has data transfer rate of 75 KB/sec and employs DMA. Data are transferred one byte at a time. How ... with the bus when transferring a block of 256 bytes assuming DMA uses cycle stealing mode? 0.153 ms 0.546 ms 1.2ms 3.4ms

Consider a system in which bus cycle takes 100 ns. Transfer of bus control from processor to device or device to processor, takes 250 ns. One of the IO device has data tr...

Akriti sood

7.3k views

Akriti sood asked Nov 2, 2016

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