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Recent questions tagged effective-memory-access
0
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31
Madeeasy Test Series [Effective memory access time]
My approach: Given EMAT = 4 4 = (1-p)(m) + p(page fault service + m) ……………. p = page fault rate Page fault service = (0.6) * 10 + (0.4)* (3) ==> 7.2 4 = (1-p)(1) + p(7.2 + 1) They have taken 4 = (1-p)(1) + p(7.2) In page fault also we should consider Memory access time right ..??
My approach: Given EMAT = 44 = (1-p)(m) + p(page fault service + m) ……………. p = page fault ratePage fault service = (0.6) * 10 + (0.4)* (3) == 7.24 = (1-p)(1) +...
jatin khachane 1
772
views
jatin khachane 1
asked
Dec 15, 2018
Operating System
effective-memory-access
operating-system
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0
votes
0
answers
32
Self Doubt [Effective memory access time]
Page fault rate = p Main memory access time = m Page fault service time = PS EMAT = (1-p) (m) + (p) (PS + m) OR EMAT = (1-p) (m) + (p) (PS) which one is right ...if page fault occurs should we consider [ Page fault service time + MM ] OR [ Page fault service time only ]
Page fault rate = pMain memory access time = mPage fault service time = PSEMAT = (1-p) (m) + (p) (PS + m)OREMAT = (1-p) (m) + (p) (PS)which one is right ...if page fault...
jatin khachane 1
592
views
jatin khachane 1
asked
Dec 15, 2018
Operating System
effective-memory-access
page-fault
operating-system
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–
0
votes
0
answers
33
General doubt.
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz explain?
I am unable to understand the memory access time for hierarchical and simultaneous access using write back policy even after reading from go sources. Can someone plz expl...
sushmita
254
views
sushmita
asked
Dec 12, 2018
CO and Architecture
computer
co-and-architecture
cache-memory
effective-memory-access
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0
votes
0
answers
34
conceptual doubt
in case of hierarchical memory organization when there is a miss in cache , we need to bring the entire block from main memory to cache so in the formula- AMAT= H1*T1+(1-H1(T1+T2)) T1- cache access time/word T2= memory access time/word T2 ... in some cases we just take word access time of main memory. also please tell me what should be T2 in case of simultaneous organization?
in case of hierarchical memory organization when there is a miss in cache , we need to bring the entire block from main memory to cache so in the formula-AMAT= H1*T1+(1-H...
sushmita
516
views
sushmita
asked
Dec 12, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
multilevel-cache
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0
votes
0
answers
35
GATE analysis
An Intel processor uses a cache block size of 128 bytes and a memory transfer to cache is about 10 times the access time of cache memory. with cache hit ratio of 0.97 what percent will be the effective memory access to that of access time of memory A. 20 percent B. 30 percent C. 40 percent D. 50 percent
An Intel processor uses a cache block size of 128 bytes and a memory transfer to cache is about 10 times the access time of cache memory. with cache hit ratio of 0.97 wha...
Abhijit Borah
451
views
Abhijit Borah
asked
Dec 10, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
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0
votes
0
answers
36
OS EMAT vs AMAT
In Page Fault and Demand Paging concept what is the difference between Effective Memory access time and average memory access time? The formulae are known but i am confused with the concept.
In Page Fault and Demand Paging concept what is the difference between Effective Memory access time and average memory access time?The formulae are known but i am confuse...
Shamim Ahmed
871
views
Shamim Ahmed
asked
Dec 9, 2018
Operating System
operating-system
effective-memory-access
page-fault
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0
votes
0
answers
37
Hamacher
aditi19
306
views
aditi19
asked
Dec 8, 2018
CO and Architecture
co-and-architecture
carl-hamacher
cache-memory
memory-interfacing
effective-memory-access
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0
votes
2
answers
38
Memory Access-self doubt
what is the number of memory accessed required in register indirect mode index register mode base register mode pls explain in details with examples
what is the number of memory accessed required inregister indirect modeindex register modebase register modepls explain in details with examples
aditi19
515
views
aditi19
asked
Nov 30, 2018
CO and Architecture
co-and-architecture
addressing-modes
effective-memory-access
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1
votes
1
answer
39
miss penalty
Effective address time for a cache comprising of L1 and L2 cache =9ns hit ratio of L1 cache = 0.8 hit ratio of L2 cache = 0.9 memory access time =100ns Miss penalty of L1 cache = 25ns Access times for L1 and L2 caches are x and y ns; let z=x+y; what’s z?? I am getting 20.33 but the given answer is different!
Effective address time for a cache comprising of L1 and L2 cache =9nshit ratio of L1 cache = 0.8 hit ratio of L2 cache = 0.9memory access time =100nsMiss penalty of L1 ca...
Gate Fever
923
views
Gate Fever
asked
Nov 28, 2018
CO and Architecture
co-and-architecture
multilevel-cache
effective-memory-access
numerical-answers
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0
votes
1
answer
40
Local Coaching
A cache is having 60% hit ratio. Cache access time is 30 ns and main memory access time is 100 ns. What is the average access time for reading? My doubt is whether to assume cache and main memory to be hierarchically connected or directly connected to the processor when nothing is given? If assumed ... , ans = 0.6(30) + 0.4(30+100). If assumed to be direct, ans = 0.6(30) + 0.4(100).
A cache is having 60% hit ratio. Cache access time is 30 ns and main memory access time is 100 ns. What is the average access time for reading?My doubt is whether to assu...
subho16
498
views
subho16
asked
Nov 26, 2018
CO and Architecture
co-and-architecture
cache-memory
doubt
numerical-answers
effective-memory-access
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–
1
votes
2
answers
41
COA: Cache Accesss Time
Little confusion with these questions. What will be o/p for these two questions one with Write back and the other is Write through. 1.)A 128 word cache and main memory are divided into 8 word blocks. The access time of a cache ... average access time? What will be the default technique ( write-allocate and no write-allocate)followed for Hierarchal and Simultaneous access ?
Little confusion with these questions.What will be o/p for these two questions one with Write back and the other is Write through.1.)A 128 word cache and main memory are ...
Hemanth_13
771
views
Hemanth_13
asked
Nov 7, 2018
CO and Architecture
co-and-architecture
cache-memory
write-through
write-back
effective-memory-access
numerical-answers
+
–
0
votes
1
answer
42
Galvin #page fault service time #memory management #disk access
gourav94240
1.5k
views
gourav94240
asked
Oct 19, 2018
Operating System
page-fault
operating-system
effective-memory-access
page-replacement
page
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–
1
votes
0
answers
43
MadeEasy Test Series: Operating System - Effective Memory Access
here when we calculate time if the write operation has to be performed then according to me we have to calculate it in following way- EMAT =0.8*(0.9*(100)+0.1*(100+1000)) + 0.2(100 +1000) =380 ns i have ... is the question and they have not included cache time, is there anything wrong in my approach if it is the please correct me
here when we calculate time if the write operation has to be performed thenaccording to me we have to calculate it in following way-EMAT =0.8*(0.9*(100)+0.1*(100+1000)) +...
garimanand
347
views
garimanand
asked
Oct 8, 2018
Operating System
operating-system
effective-memory-access
made-easy-test-series
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–
0
votes
1
answer
44
When to use word access time and when to use block access time in access time calculation.
Hello, I came across this question when practicing from a gate app. My question is here simultaneous access is used and hence we are transferring from cache to cpu if hit or main memory to ... is needed. Added the image of question. Thanks https://gateoverflow.in/?qa=blob&qa_blobid=13957411914537045045
Hello, I came across this question when practicing from a gate app. My question is here simultaneous access is used and hence we are transferring from cache to cpu if hit...
Chaitrasj
192
views
Chaitrasj
asked
Oct 4, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
write-through
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–
0
votes
0
answers
45
Hierarchy or simultaneous
Deepalitrapti
482
views
Deepalitrapti
asked
Sep 26, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
write-through
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–
0
votes
0
answers
46
Hit miss
Deepalitrapti
396
views
Deepalitrapti
asked
Sep 17, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
write-back
gate-2017
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–
0
votes
1
answer
47
Page Fault Doubt
https://gateoverflow.in/2122/gate2011-20-ugcnet-june2013-ii-48 in the solution why memory access is not considered along with page fault service time when a page fault occurs? Because after page fault the page has to be brought into the memory which needs memory access
https://gateoverflow.in/2122/gate2011-20-ugcnet-june2013-ii-48in the solution why memory access is not considered along with page fault service time when a page fault occ...
aditi19
340
views
aditi19
asked
Sep 13, 2018
Operating System
page-fault
effective-memory-access
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–
0
votes
1
answer
48
EMAT in case of page fault
I have read that EMAT when the page fault occurs is =p(PS+MA)+(1-p)(MA) p is the probability of page fault i-p is the probability that page is present in Main Memory PS is the Page fault service time MA is the memory access time but according to me first it ... which is going to take one Memory access So,EMAT should be equals=p(MA+PS+MA)+(1-p)(MA+MA). why it is not so??
I have read that EMAT when the page fault occurs is =p(PS+MA)+(1-p)(MA)p is the probability of page faulti-p is the probability that page is present in Main MemoryPS is t...
CHIRAG CHAWLA
1.5k
views
CHIRAG CHAWLA
asked
Aug 11, 2018
Operating System
page-fault
operating-system
effective-memory-access
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–
0
votes
0
answers
49
Access Time Doubt
#OS After going through some previous year questions on.. I found that in gate we have to use simultaneous access of memory instead of hierarchical access But i have a small doubt regarding 2 questions In Simultaneous EMAT = TLB hit(tlb access) + Tlb miss(n* ... that in first question exact abswer should be 64ns as option is not matching so we have taken as 65ns Is it correct??
#OSAfter going through some previous year questions on.. I found that in gate we have to use simultaneous access of memory instead of hierarchical access But i have a sma...
tusharforever
283
views
tusharforever
asked
Jul 31, 2018
Operating System
effective-memory-access
operating-system
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–
2
votes
2
answers
50
Cache Memory
Consider the following statements: S1 : Doubling the line size halves the number of tags in the cache. S2 : Doubling the associativity doubles the number of tags in the cache. S3 : Doubling the line size usually reduce compulsory misses. Which of the above statements is always true?
Consider the following statements:S1 : Doubling the line size halves the number of tags in the cache.S2 : Doubling the associativity doubles the number of tags in the cac...
Na462
2.1k
views
Na462
asked
Jul 23, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
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–
2
votes
0
answers
51
Effective Access Time
Consider a two level memory hierarchy L1 (cache) has an accessing time of 10 nsec and main memory has accessing time 100 nsec. Assume the hit ratio read operation is 0.75 and 40% references are for write operation. The average access time for system (in nsec) if it uses write through technique ________. (Upto 1 decimal places) Ans. 67.6
Consider a two level memory hierarchy L1 (cache) has an accessing time of 10 nsec and main memory has accessing time 100 nsec. Assume the hit ratio read operation is 0.75...
Na462
3.0k
views
Na462
asked
Jul 23, 2018
CO and Architecture
effective-memory-access
co-and-architecture
+
–
0
votes
1
answer
52
Cache Memory
Suppose after analyzing a new cache design, you discover that the cache has too many conflict misses and this needs to be resolved. You know that you must increase associativity in order to decrease the number of cache misses. What are the implications of increasing associativity? A. Slower cache access time B. Increase index bits C. Increase block size D. All of these
Suppose after analyzing a new cache design, you discover that the cache has too many conflict misses and this needs to be resolved. You know that you must increase associ...
Na462
1.2k
views
Na462
asked
Jul 23, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
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–
1
votes
1
answer
53
Effective Access Time
Na462
1.1k
views
Na462
asked
Jul 12, 2018
Operating System
effective-memory-access
operating-system
+
–
0
votes
0
answers
54
Cache Memory
Hi sir, i want to ask that how we'll come to know whether this is an independent memory organization or it is a hierarchical organization ? In case of hierarchical it's answer would've been 1.23T1 In case of independent it's answer is 1.11T1
Hi sir, i want to ask that how we'll come to know whether this is an independent memory organization or it is a hierarchical organization ? In case of hierarchical it's a...
Priyansh Singh
277
views
Priyansh Singh
asked
Jul 2, 2018
CO and Architecture
cache-memory
multilevel-cache
co-and-architecture
effective-memory-access
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–
0
votes
0
answers
55
Compile Design Question From run time environment
Ronish Jariwala 1
737
views
Ronish Jariwala 1
asked
Apr 15, 2018
Compiler Design
compiler-design
effective-memory-access
stack
symbol-table
runtime-environment
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–
2
votes
1
answer
56
My doubt on TLB and page fault
First read this whole thing what I am writing below: Case 1: If we have to access unit address in memory using TLB and we assume that no page fault occurs then, EMAT=p( T+M )+( 1-p ) (T+M+M) T=TLB access time, M= ... if there page fault occurs then how does the last calculated EMAT here affects the first Estimated memory access time which we have calculated using TLB?
First read this whole thing what I am writing below:Case 1: If we have to access unit address in memory using TLB and we assume that no page fault occurs then,EMAT=p( T+M...
Akash Kumar Roy
2.6k
views
Akash Kumar Roy
asked
Apr 5, 2018
Operating System
operating-system
translation-lookaside-buffer
hit-ratio
page-fault
effective-memory-access
+
–
0
votes
1
answer
57
Cache Organization
Ques. In a two-level memory hierarchy, let $t_1 = 10^{-7s}$ and $t_2 = 10^{-2s}$. If ta denotes the average access time of the memory hierarchy, and if we define the access efficiency to be equal to $t_1=t_a$, then what must the hit ratio $H$ ... Why they have considered only Hit Time instead of Hit Ratio and Hit time.... and plz explain which one to use and when...
Ques. In a two-level memory hierarchy, let $t_1 = 10^{-7s}$ and $t_2 = 10^{-2s}$. If ta denotes the average accesstime of the memory hierarchy, and if we define the acces...
Na462
456
views
Na462
asked
Mar 9, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
+
–
1
votes
1
answer
58
Cache Organization
My Doubt is simple How to know which cache organization to use hierarchical or direct cache while calculating the average access time. Like in this Question:- https://gateoverflow.in/2308/gate1993-11 Here hierarchal access is used and why? Plz help me
My Doubt is simple How to know which cache organization to use hierarchical or direct cache while calculating the averageaccess time.Like in this Question:- https://gateo...
Na462
350
views
Na462
asked
Mar 8, 2018
CO and Architecture
co-and-architecture
cache-memory
effective-memory-access
+
–
0
votes
0
answers
59
TLB-Memory-access-live-test-2
A system uses $2$ level paging scheme. A regular memory access takes $100$ ns and servicing a page fault takes $10$ millisecond. An avg instruction takes $100$ ns of CPU time and $2$ memory access. The TLB hit ratio is $95\%$. and page fault is $1$ in every $10,000$ memory access. Avg instruction execution time.$?$ Options given are $1300$ns $1150$ns $2320$ns $1275$ns
A system uses $2$ level paging scheme.A regular memory access takes $100$ ns and servicing a page fault takes $10$ millisecond.An avg instruction takes $100$ ns of CPU ti...
Inspiron
479
views
Inspiron
asked
Jan 29, 2018
CO and Architecture
effective-memory-access
co-and-architecture
+
–
1
votes
1
answer
60
Memory Organization
Q.1 What is diffrence between EMAT(effective) and AMAT(average mem access time)? Q.2 Suppose we have L1 cache ,L2cache and MM , and H1,M1, T1: hit/miss ratio, access time of L1 cache. And H2 , M2, T2 hit/miss ration of L2. amd MM access time is t3. Then how to calculate EMAT and AMAT?
Q.1 What is diffrence between EMAT(effective) and AMAT(average mem access time)?Q.2 Suppose we have L1 cache ,L2cache and MM , and H1,M1, T1: hit/miss ratio, access time ...
Prateek K
358
views
Prateek K
asked
Jan 29, 2018
CO and Architecture
cache-memory
effective-memory-access
+
–
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