# Recent questions tagged flip-flop

1
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
2
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
3
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ Flip-flop with inputs $X = S$ and $Y=R$ $\text{J-K}$ Flip-flop with inputs $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
4
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
5
If the input $\text{J}$ is connected through $\text{K}$ input of $\text{J-K}$, then flip-flop will behave as a D type flip-flop T type flip-flop S-R flip-flop Toggle switch
6
To build a mod-$19$ counter the number of flip-flop required is $3$ $5$ $7$ $8$
7
Which of the following conditions must be met to avoid race around problem? $\Delta t< t_{p}< T$ $T>\Delta t> t_{p}$ $2t_{p}< \Delta t< T$ none of these
8
How many flip-flop are needed to divide the input frequency by $64$? $4$ $5$ $6$ $8$
9
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip-flops Clock input of one flip-flop
10
The number of columns in a stateable for a sequential circuit with $’m’$ flip flops and $’n’$ input is $m+n$ $m+2n$ $2m+n$ $2m+2n$
11
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip flops Clock input of one flip-flop
1 vote
12
In a ripple counter using edge triggered $JK$ flip-flops, the pulse input is applied to the clock input of all flip-flops clock input of one flip-flop $J$ and $K$ inputs of all flip-flops $J$ and $K$ inputs of one flip flop
1 vote
13
What will be the final output of D flip-Flop if the input string is $0010011100$? $1$ $0$ Don’t Care None of the above
14
A binary $3$-bit down counter uses $J$-$K$ flip-flops, $FF_{i}$ with inputs $J_{i}$, $K_{i}$ and outputs $Q_{i}$, $i$ = $0, 1, 2$ respectively. The minimized expression for the input from following is : $J_{0} = K_{0} = 0$ $J_{0} = K_{0} = 1$ $J_{1} = K_{1} = Q_{0}$ ... $J_{2} = K_{2} =\overline{Q}_{1} \overline{Q}_{0}$ I, III, V I, IV, VI II, III, V II, IV, VI
1 vote
15
A new flipflop with inputs $X$ and $Y$, has the following property $\begin{array}{|c|c|c|}\hline \bf{X}& \bf{Y}& \bf{Current\ state}&\bf{ Next\ state} \\\hline 0&0&Q&1 \\ 0&1&Q&\overline{Q}\\ 1& 1&Q&0 \\ 1&0&Q&Q \\ \hline \end{array}$ Which of the following expresses the next ... $(X\wedge \overline{Q })\vee (Y \wedge Q)$ $(X\wedge \overline{Q })\vee (\overline{Y } \wedge Q)$
1 vote
16
A Finite State Machine(FSM) is implemented using the D-FFs A and B with logic gates as shown below. The four possible states of FSM are $Q_{A}Q_{B}=00,01,10,11$. Assume that $X_{in}$ is held at constant logic level throughout the operation of FSM. Where the FSM is ... the four possible states if $X_{in}=0$ How do we check $X_{in}$ here? Can we check it arbitrarily, or checked with prev states??
17
$1)$ Master-Slave FF is designed to avoid race around condition $2)$ Master-Slave FF is used to store $2$ bit information Which of the following statement is correct? What is meaning of $2-bit$ information??
18
For the asynchronous sequential circuit shown in the figure: Derive the boolean functions for the outputs of two SR latches $Y _1 and Y _2$. Note that the S input of the second latch is $x _1’y _1’$. Derive the transition table and output map of the circuit.
19
Convert the circuit of the figure to the asynchronous sequential circuit by removing the clock-pulse(CP) and changes the flip-flops to the SR latches. Derive the transition table and output map of the modified circuit.
20
Analyze the T flip-flop shown in the figure. Obtain the transition table and show that the circuit is unstable when both T and CP are equal to 1.
1 vote
21
A sequential circuit has three flip-flops, A, B, C; one input, x; one output, y; The state diagram is shown in the figure. The circuit is to be designed by treating the unused state as don’t care conditions. The final circuit should be analyzed to ensure that it is self-correcting. Use D flip-flop in the design. USe JK flip-flops in the design .
22
Design a sequential circuit with two JK flip-flops, A and B and two inputs, E and x. If E = 0 the circuit remains in the same state regardless of the value of x. When E = 1and x = 1, the circuit goes through the transactions from 00 to 01 to10 to 11 back to 00, and repeats. When E = 1 and x = 0 the circuit goes through the transactions from 00 to 11 to 10 to 01 back to 00, and repeats.
23
Design a sequential circuit with two D flip-flops A and B and one input, x. When x = 0 the state of the circuit remains the same. When x =1 circuit goes through the state transition from 00 to 01 to 1 to 10 back to 00 and, repeats.
24
Convert a D flip-flop to JK flip-flop by including input gates to the D flip-flop. The gates need for the input of the D flip-flop can be determined by means of the sequential circuit design procedure. The sequential circuit to be considered will have one D flip-flop and two inputs, J and K.
A sequential circuit has two JK flip-flop, A and B, two inputs, x and y; and one output, z; The flip-flop input functions and the circuit output function are as follows: $JA= bx + b’y’$ $KA= B’xy’$ $JB = A’x$ $KB=A + xy’$ $z = Axy + Bx’y’$ draw the logic diagram of the circuit. tabulate the state table. Derive the next-state equations for A and B.