The Gateway to Computer Science Excellence
For all GATE CSE Questions
Toggle navigation
Facebook Login
or
Email or Username
Password
Remember
Login
Register

I forgot my password
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
Prev
Blogs
New Blog
Exams
First time here? Checkout the
FAQ
!
x
×
Close
Use the google search bar on side panel. It searches through all previous GATE/other questions. For hardcopy of previous year questions please see
here
Recent questions tagged flipflop
+1
vote
0
answers
1
Made Easy Test Series:FlipFlop
A Finite State Machine(FSM) is implemented using the DFFs A and B with logic gates as shown below. The four possible states of FSM are $Q_{A}Q_{B}=00,01,10,11$. Assume that $X_{in}$ is held at constant logic level throughout the operation of FSM. ... states if $X_{in}=0$ How do we check $X_{in}$ here? Can we check it arbitrarily, or checked with prev states??
asked
May 16
in
Digital Logic
by
srestha
Veteran
(
111k
points)

36
views
digitallogic
flipflop
madeeasytestseries
0
votes
1
answer
2
Made Easy Test Series: Digital Logic Master Slave FF
$1)$ MasterSlave FF is designed to avoid race around condition $2)$ MasterSlave FF is used to store $2$ bit information Which of the following statement is correct? What is meaning of $2bit $ information??
asked
May 15
in
Digital Logic
by
srestha
Veteran
(
111k
points)

71
views
digitallogic
madeeasytestseries
flipflop
0
votes
0
answers
3
Morris Mano Edition 3 Exercise 9 Question 9 (Page No. 394)
For the asynchronous sequential circuit shown in the figure: Derive the boolean functions for the outputs of two SR latches $Y _1 and Y _2$. Note that the S input of the second latch is $x _1’y _1’$. Derive the transition table and output map of the circuit.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

25
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
latch
flipflop
0
votes
0
answers
4
Morris Mano Edition 3 Exercise 9 Question 8 (Page No. 394)
Convert the circuit of the figure to the asynchronous sequential circuit by removing the clockpulse(CP) and changes the flipflops to the SR latches. Derive the transition table and output map of the modified circuit.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

18
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
flipflop
0
votes
0
answers
5
Morris Mano Edition 3 Exercise 9 Question 7 (Page No. 394)
Analyze the T flipflop shown in the figure. Obtain the transition table and show that the circuit is unstable when both T and CP are equal to 1.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

9
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
flipflop
0
votes
0
answers
6
Morris Mano Edition 3 Exercise 6 Question 22 (Page No. 255)
A sequential circuit has three flipflops, A, B, C; one input, x; one output, y; The state diagram is shown in the figure. The circuit is to be designed by treating the unused state as don't care conditions. The final circuit ... analyzed to ensure that it is selfcorrecting. Use D flipflop in the design. USe JK flipflops in the design .
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

13
views
digitallogic
sequentialcircuit
flipflop
synchronousasynchronouscircuits
0
votes
0
answers
7
Morris Mano Edition 3 Exercise 6 Question 21 (Page No. 255)
Design a sequential circuit with two JK flipflops, A and B and two inputs, E and x. If E = 0 the circuit remains in the same state regardless of the value of x. When E = 1and x = 1, the circuit goes through the transactions from ... = 1 and x = 0 the circuit goes through the transactions from 00 to 11 to 10 to 01 back to 00, and repeats.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

19
views
digitallogic
sequentialcircuit
flipflop
synchronousasynchronouscircuits
0
votes
0
answers
8
Morris Mano Edition 3 Exercise 6 Question 20 (Page No. 255)
Design a sequential circuit with two D flipflops A and B and one input, x. When x = 0 the state of the circuit remains the same. When x =1 circuit goes through the state transition from 00 to 01 to 1 to 10 back to 00 and, repeats.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

6
views
digitallogic
sequentialcircuit
flipflop
synchronousasynchronouscircuits
0
votes
0
answers
9
Morris Mano Edition 3 Exercise 6 Question 19 (Page No. 254)
Convert a D flipflop to JK flipflop by including input gates to the D flipflop. The gates need for the input of the D flipflop can be determined by means of the sequential circuit design procedure. The sequential circuit to be considered will have one D flipflop and two inputs, J and K.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

19
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
flipflop
0
votes
0
answers
10
Morris Mano Edition 3 Exercise 6 Question 18 (Page No. 254)
Analyze the circuit in the following figure and show that it is equivalent to T flipflop.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

16
views
digitallogic
sequentialcircuit
flipflop
synchronousasynchronouscircuits
0
votes
0
answers
11
Morris Mano Edition 3 Exercise 6 Question 12 (Page No. 254)
A sequential circuit has two JK flipflop, A and B, two inputs, x and y; and one output, z; The flipflop input functions and the circuit output function are as follows: $JA= bx + b'y'$ $KA= B'xy'$ ... draw the logic diagram of the circuit. tabulate the state table. Derive the nextstate equations for A and B.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

56
views
digitallogic
flipflop
sequentialcircuit
0
votes
0
answers
12
Morris Mano Edition 3 Exercise 6 Question 11 (Page No. 253)
A sequential circuit has two JK flipflops one input, x, and one output y. The logic diagram of the circuit is shown in the figure. Derive the state table and state diagram. .
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

11
views
digitallogic
sequentialcircuit
flipflop
0
votes
0
answers
13
Morris Mano Edition 3 Exercise 6 Question 10 (Page No. 253)
A JN flipflop has two inputs J and N, input J behaves like J input of the JK flipflop and input N behaves like the complement of K input of JK flipflop.(that is N = k') Tabulate the characteristic table of the ... flop. Tabulate the Excitation table of the flipflop. Show that by connecting two inputs together, one obtains a D flipflop.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

7
views
digitallogic
sequentialcircuit
flipflop
0
votes
0
answers
14
Morris Mano Edition 3 Exercise 6 Question 9 (Page No. 253)
Derive the state diagram and state table of the sequential circuit shown in the figure. Explain the function that the circuit performs.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

12
views
digitallogic
sequentialcircuit
flipflop
0
votes
0
answers
15
Morris Mano Edition 3 Exercise 6 Question 8 (Page No. 252)
A sequential circuit has one flipflop, Q; two inputs x and y; and one output, S. It consists of a full adder circuit connected to a D flipflop as shown in the figure. Derive the state table and state diagram of the circuit.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

33
views
digitallogic
flipflop
sequentialcircuit
0
votes
0
answers
16
Morris Mano Edition 3 Exercise 6 Question 7 (Page No. 252)
A sequential circuit has three D flipflop, A, B, C and one input x. It is described by the following flipflop input functions $DA = (B’C + BC’)x + (BC + B’C’)x’$ $DB = A$ $DC = B$ derive a state table for the circuit. Draw two state diagram: one for x = 0 and other for x = 1.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

35
views
digitallogic
sequentialcircuit
flipflop
0
votes
0
answers
17
Morris Mano Edition 3 Exercise 6 Question 6 (Page No. 252)
A sequential circuit with two D flipflops, A and B; two input x and y; one output z; it is specified by the following nextstate and output equations: $A(t+1) = x’y + xA$ $B(t+1) = x’B + xA$ $Z = B$ Draw the logic diagram of the circuit. Dervie the state table. Drive the state diagram.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

8
views
digitallogic
sequentialcircuit
flipflop
0
votes
0
answers
18
Morris Mano Edition 3 Exercise 6 Question 5 (Page No. 252)
The Dtype positive edge triggered flipflop of the figure is modified by including an asynchronous clear input in the circuit. The Asynchronous clear input is connected to the third input in gate 2 and also to the third input in ... that when asynchronous clear input is at logic 1, it has no effect on the normal operation of the circuit.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

7
views
digitallogic
flipflop
sequentialcircuit
0
votes
0
answers
19
Morris Mano Edition 3 Exercise 6 Question 4 (Page No. 252)
Draw the logic diagram of a masterslave D flipflop. Use NAND gates
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

10
views
digitallogic
sequentialcircuit
flipflop
0
votes
0
answers
20
Morris Mano Edition 3 Exercise 6 Question 3 (Page No. 252)
The D FLipflop can be constructed with the four NAND gates only. This can be done by removing gate number 5 from the circuit and, instead, connecting the output of gate number 3 the input of gate number 4. Draw the Modified circuit and show that it operates in the same way as the original circuit operates .
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

2
views
digitallogic
flipflop
sequentialcircuit
0
votes
0
answers
21
Morris Mano Edition 3 Exercise 6 Question 2 (Page No. 251)
Construct the D flipflop that has the same characteristics as the one shown in the figure, but instead of using NAND gates use NOR gates only.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

9
views
digitallogic
sequentialcircuit
flipflop
0
votes
0
answers
22
Morris Mano Edition 3 Exercise 6 Question 1 (Page No. 251)
Construct a D flipflop that have the same charactorstics as the one shown in the figure, but instead of using NAND gates use NOR and AND gates only. (Remember that one input NOR gate is equivalent to an inverter.
asked
Apr 4
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.4k
points)

5
views
digitallogic
sequentialcircuit
flipflop
0
votes
0
answers
23
Self Doubt
What is control input and control output ? Is in SR output changes with control input and control output?
asked
Apr 1
in
Digital Logic
by
srestha
Veteran
(
111k
points)

11
views
digitallogic
flipflop
0
votes
0
answers
24
flip flop msb lsb
What should be default order of msb lsb in flip flops if msb lsb flip flop not given for a counter
asked
Jan 21
in
Digital Logic
by
bts1jimin
(
193
points)

33
views
digitallogic
flipflop
0
votes
1
answer
25
flip flop : find mod of counter having presets as shown
asked
Jan 20
in
Digital Logic
by
bts1jimin
(
193
points)

45
views
digitallogic
flipflop
0
votes
0
answers
26
GATEBOOK2019 Mock Test148
The figure shows a digital circuit constructed using negative edge triggered JK flip flops. Assume a starting state Q2Q1Q0 = 000. This state Q2Q1Q0 = 000 will repeat after _______ number of cycles of the clock CLK? $4$ $5$ $6$ $7$
asked
Jan 19
in
Digital Logic
by
GATEBOOK
Boss
(
11.4k
points)

156
views
gb2019mock1
flipflop
0
votes
0
answers
27
MadeEasy Test Series: Digital Logic  Digital Counter
asked
Jan 11
in
Digital Logic
by
jatin khachane 1
Loyal
(
6.7k
points)

132
views
madeeasytestseries
digitallogic
flipflop
digitalcounter
0
votes
1
answer
28
MadeEasy Full Length Test 2019: Digital Logic  Flip Flop
The answer I got is 3 but it’s given as 5 and in the solution they are mentioning that the no. of flip flops here are defined by the sequence not the no. of states??
asked
Jan 6
in
Digital Logic
by
Sambhrant Maurya
Active
(
1.4k
points)

91
views
digitallogic
counters
sequentialcircuit
flipflop
madeeasytestseries2019
madeeasytestseries
0
votes
0
answers
29
Digital Logic made easy
Consider the circuit given below: MSB and LSB of mod 10 ripple counter act as clock to ripple down and up counter respectively. Initially all the counters were cleared and output of comparator was A=B. The clock pulse is applied. Find the minimum no of clock pulses required to make A=B again.
asked
Jan 5
in
Digital Logic
by
Sambhrant Maurya
Active
(
1.4k
points)

163
views
digitallogic
ripplecounteroperation
sequentialcircuit
flipflop
0
votes
1
answer
30
GATE 2001 ECE
The digital block in the figure is realized using two positive edge triggered flip flops. Assume that for t<t0, Q1=Q2=0. The correct realization is given by which of the following figures?
asked
Jan 5
in
Digital Logic
by
Sambhrant Maurya
Active
(
1.4k
points)

65
views
digitallogic
sequentialcircuit
flipflop
Page:
1
2
3
4
5
6
next »
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
The day that made me an IIScian :)
Unanswered Previous year GATE/TIFR questions
From being a Failure to getting into IISc  (Rank 888, Score 692)
My interview experience at IITs/IISc
IIT Delhi CSE Mtech interview 14 may
Follow @csegate
Recent questions tagged flipflop
Recent Blog Comments
@Debargh, Yes. 👍
Thanks. Regarding the probability question, was...
Thanks
What were the Eigen values of A apart from 0? I...
49,540
questions
54,099
answers
187,269
comments
71,006
users