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Recent questions tagged flipflop
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ISRO202080
A new flipflop with inputs $X$ and $Y$ ... $(X\wedge \overline{Q })\vee (Y \wedge Q)$ $(X\wedge \overline{Q })\vee (\overline{Y } \wedge Q)$
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Made Easy Test Series:FlipFlop
A Finite State Machine(FSM) is implemented using the DFFs A and B with logic gates as shown below. The four possible states of FSM are $Q_{A}Q_{B}=00,01,10,11$. Assume that $X_{in}$ is held at constant logic level throughout the operation of FSM. ... states if $X_{in}=0$ How do we check $X_{in}$ here? Can we check it arbitrarily, or checked with prev states??
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May 16, 2019
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Digital Logic
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srestha
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Made Easy Test Series: Digital Logic Master Slave FF
$1)$ MasterSlave FF is designed to avoid race around condition $2)$ MasterSlave FF is used to store $2$ bit information Which of the following statement is correct? What is meaning of $2bit $ information??
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May 15, 2019
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Digital Logic
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srestha
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Morris Mano Edition 3 Exercise 9 Question 9 (Page No. 394)
For the asynchronous sequential circuit shown in the figure: Derive the boolean functions for the outputs of two SR latches $Y _1 and Y _2$. Note that the S input of the second latch is $x _1’y _1’$. Derive the transition table and output map of the circuit.
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Apr 7, 2019
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Digital Logic
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ajaysoni1924
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5
Morris Mano Edition 3 Exercise 9 Question 8 (Page No. 394)
Convert the circuit of the figure to the asynchronous sequential circuit by removing the clockpulse(CP) and changes the flipflops to the SR latches. Derive the transition table and output map of the modified circuit.
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Apr 7, 2019
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Digital Logic
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Morris Mano Edition 3 Exercise 9 Question 7 (Page No. 394)
Analyze the T flipflop shown in the figure. Obtain the transition table and show that the circuit is unstable when both T and CP are equal to 1.
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Apr 7, 2019
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Digital Logic
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Morris Mano Edition 3 Exercise 6 Question 22 (Page No. 255)
A sequential circuit has three flipflops, A, B, C; one input, x; one output, y; The state diagram is shown in the figure. The circuit is to be designed by treating the unused state as don't care conditions. The final circuit ... analyzed to ensure that it is selfcorrecting. Use D flipflop in the design. USe JK flipflops in the design .
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Apr 4, 2019
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Digital Logic
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Morris Mano Edition 3 Exercise 6 Question 21 (Page No. 255)
Design a sequential circuit with two JK flipflops, A and B and two inputs, E and x. If E = 0 the circuit remains in the same state regardless of the value of x. When E = 1and x = 1, the circuit goes through the transactions from ... = 1 and x = 0 the circuit goes through the transactions from 00 to 11 to 10 to 01 back to 00, and repeats.
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Apr 4, 2019
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Digital Logic
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Morris Mano Edition 3 Exercise 6 Question 20 (Page No. 255)
Design a sequential circuit with two D flipflops A and B and one input, x. When x = 0 the state of the circuit remains the same. When x =1 circuit goes through the state transition from 00 to 01 to 1 to 10 back to 00 and, repeats.
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Apr 4, 2019
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Digital Logic
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Morris Mano Edition 3 Exercise 6 Question 19 (Page No. 254)
Convert a D flipflop to JK flipflop by including input gates to the D flipflop. The gates need for the input of the D flipflop can be determined by means of the sequential circuit design procedure. The sequential circuit to be considered will have one D flipflop and two inputs, J and K.
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Apr 4, 2019
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Digital Logic
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Morris Mano Edition 3 Exercise 6 Question 18 (Page No. 254)
Analyze the circuit in the following figure and show that it is equivalent to T flipflop.
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Apr 4, 2019
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Digital Logic
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Morris Mano Edition 3 Exercise 6 Question 12 (Page No. 254)
A sequential circuit has two JK flipflop, A and B, two inputs, x and y; and one output, z; The flipflop input functions and the circuit output function are as follows: $JA= bx + b'y'$ $KA= B'xy'$ ... draw the logic diagram of the circuit. tabulate the state table. Derive the nextstate equations for A and B.
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Apr 4, 2019
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Digital Logic
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Morris Mano Edition 3 Exercise 6 Question 11 (Page No. 253)
A sequential circuit has two JK flipflops one input, x, and one output y. The logic diagram of the circuit is shown in the figure. Derive the state table and state diagram. .
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Apr 4, 2019
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Digital Logic
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Morris Mano Edition 3 Exercise 6 Question 10 (Page No. 253)
A JN flipflop has two inputs J and N, input J behaves like J input of the JK flipflop and input N behaves like the complement of K input of JK flipflop.(that is N = k') Tabulate the characteristic table of the ... flop. Tabulate the Excitation table of the flipflop. Show that by connecting two inputs together, one obtains a D flipflop.
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Apr 4, 2019
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Digital Logic
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15
Morris Mano Edition 3 Exercise 6 Question 9 (Page No. 253)
Derive the state diagram and state table of the sequential circuit shown in the figure. Explain the function that the circuit performs.
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Apr 4, 2019
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Digital Logic
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16
Morris Mano Edition 3 Exercise 6 Question 8 (Page No. 252)
A sequential circuit has one flipflop, Q; two inputs x and y; and one output, S. It consists of a full adder circuit connected to a D flipflop as shown in the figure. Derive the state table and state diagram of the circuit.
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Digital Logic
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17
Morris Mano Edition 3 Exercise 6 Question 7 (Page No. 252)
A sequential circuit has three D flipflop, A, B, C and one input x. It is described by the following flipflop input functions $DA = (B’C + BC’)x + (BC + B’C’)x’$ $DB = A$ $DC = B$ derive a state table for the circuit. Draw two state diagram: one for x = 0 and other for x = 1.
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Digital Logic
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18
Morris Mano Edition 3 Exercise 6 Question 6 (Page No. 252)
A sequential circuit with two D flipflops, A and B; two input x and y; one output z; it is specified by the following nextstate and output equations: $A(t+1) = x’y + xA$ $B(t+1) = x’B + xA$ $Z = B$ Draw the logic diagram of the circuit. Dervie the state table. Drive the state diagram.
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Digital Logic
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Morris Mano Edition 3 Exercise 6 Question 5 (Page No. 252)
The Dtype positive edge triggered flipflop of the figure is modified by including an asynchronous clear input in the circuit. The Asynchronous clear input is connected to the third input in gate 2 and also to the third input in ... that when asynchronous clear input is at logic 1, it has no effect on the normal operation of the circuit.
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20
Morris Mano Edition 3 Exercise 6 Question 4 (Page No. 252)
Draw the logic diagram of a masterslave D flipflop. Use NAND gates
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Morris Mano Edition 3 Exercise 6 Question 3 (Page No. 252)
The D FLipflop can be constructed with the four NAND gates only. This can be done by removing gate number 5 from the circuit and, instead, connecting the output of gate number 3 the input of gate number 4. Draw the Modified circuit and show that it operates in the same way as the original circuit operates .
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Morris Mano Edition 3 Exercise 6 Question 2 (Page No. 251)
Construct the D flipflop that has the same characteristics as the one shown in the figure, but instead of using NAND gates use NOR gates only.
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Morris Mano Edition 3 Exercise 6 Question 1 (Page No. 251)
Construct a D flipflop that have the same charactorstics as the one shown in the figure, but instead of using NAND gates use NOR and AND gates only. (Remember that one input NOR gate is equivalent to an inverter.
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Self Doubt
What is control input and control output ? Is in SR output changes with control input and control output?
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Apr 1, 2019
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Digital Logic
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flip flop msb lsb
What should be default order of msb lsb in flip flops if msb lsb flip flop not given for a counter
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Jan 21, 2019
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Digital Logic
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26
flip flop : find mod of counter having presets as shown
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Jan 20, 2019
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Digital Logic
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27
MadeEasy Test Series: Digital Logic  Digital Counter
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Jan 11, 2019
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28
MadeEasy Full Length Test 2019: Digital Logic  Flip Flop
The answer I got is 3 but it’s given as 5 and in the solution they are mentioning that the no. of flip flops here are defined by the sequence not the no. of states??
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Jan 6, 2019
in
Digital Logic
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Sambhrant Maurya
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madeeasytestseries
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29
Digital Logic made easy
Consider the circuit given below: MSB and LSB of mod 10 ripple counter act as clock to ripple down and up counter respectively. Initially all the counters were cleared and output of comparator was A=B. The clock pulse is applied. Find the minimum no of clock pulses required to make A=B again.
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Jan 5, 2019
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Digital Logic
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Sambhrant Maurya
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30
GATE 2001 ECE
The digital block in the figure is realized using two positive edge triggered flip flops. Assume that for t<t0, Q1=Q2=0. The correct realization is given by which of the following figures?
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Jan 5, 2019
in
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