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Recent questions tagged flip-flop
0
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0
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121
Given J-K flip-flop in 0 state, what is the sequence of inputs necessary to cause the following sequence of states
Garrett McClure
asked
in
Digital Logic
Oct 31, 2017
by
Garrett McClure
273
views
flip-flop
digital-logic
digital-circuits
0
votes
0
answers
122
Given S-R flip-flop in 0 state, what is the sequence of inputs necessary to cause the following sequence of states
Garrett McClure
asked
in
Digital Logic
Oct 31, 2017
by
Garrett McClure
235
views
flip-flop
digital-logic
digital-circuits
0
votes
3
answers
123
Digital Circuits - Given that the present state of a flip-flop is q and the next state is Q, answer the following.
Garrett McClure
asked
in
Digital Logic
Oct 30, 2017
by
Garrett McClure
722
views
flip-flop
digital-circuits
digital-logic
2
votes
1
answer
124
MadeEasy Subject Test: Digital Logic - Flip Flop
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of MOD 256 counter ?(in MHz) a)18.18 b)19.18 c)20. ... makes Frequency = 1/(30 nsec) = 33.33 Mhz? please correct me where I am going wrong. Thanks for your help :)
Kamal Pratap
asked
in
Digital Logic
Oct 10, 2017
by
Kamal Pratap
373
views
made-easy-test-series
digital-logic
synchronous-asynchronous-circuits
clock-frequency-flop
flip-flop
1
vote
0
answers
125
GATE 1991 SELF DOUBT
https://gateoverflow.in/26442/gate1991_5-c i think the answer given by arjun sir is wrong because the time period of the clock should be selected in such a way that the present output is generated by the flipflop and it goes to the combinational ... output of the last flipflop doesnt effect any inpputs to any other flipflops and hence the delay of that flipflop can be neglected
Venkat Sai
asked
in
Digital Logic
Oct 7, 2017
by
Venkat Sai
306
views
digital-logic
flip-flop
0
votes
0
answers
126
self dbt
https://gateoverflow.in/659/gate2000-2-12 is this a master slave fipflop ?? the clock to the second is not inverted .. the question should be like within same clock both operate but one is in positive edge and the other is in negative edge ??
Venkat Sai
asked
in
Digital Logic
Oct 4, 2017
by
Venkat Sai
94
views
flip-flop
0
votes
0
answers
127
self dbt
https://gateoverflow.in/659/gate2000-2-12 is this a master slave fipflop ?? the clock to the second is not inverted .. the question should be like within same clock both operate but one is in positive edge and the other is in negative edge ??
Venkat Sai
asked
in
Digital Logic
Oct 4, 2017
by
Venkat Sai
110
views
flip-flop
0
votes
1
answer
128
Virtula gate test
Can somebody explain the question, please?
AnilGoudar
asked
in
Digital Logic
Oct 4, 2017
by
AnilGoudar
190
views
digital-logic
flip-flop
1
vote
0
answers
129
latch vs flip flop
what is the difference between latch and flip flop in terms of enable and clock ?someone pls explain with circuit diagram .
set2018
asked
in
Digital Logic
Sep 29, 2017
by
set2018
301
views
digital-logic
flip-flop
digital-circuits
0
votes
1
answer
130
UGC NET CSE | December 2008 | Part 2 | Question: 14
The characteristics equation of $D$ flip-flop is : $Q$=$1$ $Q$=$0$ $Q$=$\bar{D}$ $Q$=$D$
rishu_darkshadow
asked
in
Digital Logic
Sep 25, 2017
by
rishu_darkshadow
503
views
ugcnetcse-dec2008-paper2
digital-logic
flip-flop
8
votes
0
answers
131
General
I heard JK Master Slave flipflop is not in syllabus. But there is this question of 2001, https://gateoverflow.in/752/gate2001-11 which is based on JK Master Slave Flipflop. I just want to know is JK Master Slave Flipflop still in Gate 2018 Syllabus?
Utkarsh Anand
asked
in
Digital Logic
Sep 19, 2017
by
Utkarsh Anand
437
views
digital-logic
flip-flop
gatecse-2018
0
votes
0
answers
132
FLIP FLOP
what is the use of clock in flip flop ...explain please .......
air1ankit
asked
in
Digital Logic
Aug 26, 2017
by
air1ankit
180
views
flip-flop
digital-circuits
digital-logic
0
votes
0
answers
133
Digital-Logic Flip-flop Counters
Qn) Ripple counter with preset works as? QN- 2) Construction of Decoder 4:16? QN- 3) 4 JK Flip-flops with high input. The frequency at output?
POOJAN SHAH
asked
in
Digital Logic
Aug 25, 2017
by
POOJAN SHAH
502
views
digital-circuits
flip-flop
digital-counter
sequential
1
vote
0
answers
134
From a practice problem set of Made Easy
This is a question in Made Easy sheet and is related to Master Slave JK Flip Flop. I understand the solution but while trying to get the answer using the timing diagram The answer I get is different from that in the option(00,01,11,10,00). Please verify my timing diagram shown in image and correct me where I am wrong
Aastha Mishra
asked
in
Digital Logic
Aug 1, 2017
by
Aastha Mishra
444
views
flip-flop
digital-logic
sequential
digital-circuits
3
votes
3
answers
135
Number of Flip-Flops
Let the counting Sequence be 0 - 1 - 0 - 2 - 0 - 3 - 1, Then How many flip flops are required to implement the counter?
AnilGoudar
asked
in
Digital Logic
Jun 15, 2017
by
AnilGoudar
2.7k
views
digital-logic
flip-flop
0
votes
1
answer
136
Counters
Draw the Wave time diagram for the following counter and what is the mod value of the counter? Assume all J, k are attached to logic 1.
Shubhanshu
asked
in
Digital Logic
Apr 29, 2017
by
Shubhanshu
560
views
digital-logic
digital-counter
flip-flop
1
vote
1
answer
137
ISRO 2006-ECE Flipflops
Which of the following statements are correct ? 1. A flip-flop is used to store $1$ bit of information. 2. Race-around condition occurs in a $J$-$K$ flip-flop when both the inputs are $1$. 3. Master-slave configuration is used in flip-flops to store $2$ bits of information. 4. A transparent ... -type flip-flop. $1$,$2$ and $3$ $1$,$3$ and $4$ $1$,$2$ and $4$ $2$,$3$ and $4$
sh!va
asked
in
Digital Logic
Mar 3, 2017
by
sh!va
2.1k
views
isro-ece
digital-logic
flip-flop
1
vote
1
answer
138
ISRO 2007-ECE JK flipflop as Divide by 2 circuit
For one of the following conditions, clocked $J$-$K$ flip-flop can be used as divided by $2$ circuit where the pulse train to be divided is applied at clock input : $J$ = $1$, $K$ = $1$ and the flip-flop should have active $HIGH$ inputs ... have active $HIGH$ inputs. $J$ = $1$, $K$ = $1$ and the flip-flop should be a negative edge triggered one.
sh!va
asked
in
Digital Logic
Mar 2, 2017
by
sh!va
1.6k
views
isro-ece
digital-logic
flip-flop
1
vote
0
answers
139
ISRO 2008- ECE Flip flop counter
A counter is designed with six stages of flip flops. Determine the output frequency at the last (sixth) stage, when input frequency is $1$ $MHz$. $1$ $MHz$ $166$ $KHz$ $15.625$ $KHz$ $0$
sh!va
asked
in
Digital Logic
Mar 1, 2017
by
sh!va
737
views
digital-logic
isro-ece
flip-flop
0
votes
1
answer
140
ISRO 2008- ECE SR flipflop to D flip flop
A $S$-$R$ flip flop with a clock input can be converted to a $’D’$ flip flop using : Two inverters the flip flop outputs ($Q$&$\bar{Q}$) connected to its inputs ($S$&$R$) One inverter Not possible
sh!va
asked
in
Digital Logic
Mar 1, 2017
by
sh!va
438
views
isro-ece
digital-logic
flip-flop
1
vote
2
answers
141
ISRO 2008- ECE Johnson Counter
The mod number of a Johnson counter will be always equal to the number of flip flops used : same twice $2N$ where $N$ is the number of flip flops. None of the these
sh!va
asked
in
Digital Logic
Mar 1, 2017
by
sh!va
898
views
isro-ece
digital-logic
flip-flop
29
votes
7
answers
142
GATE CSE 2017 Set 1 | Question: 33
Consider a combination of $\text{T}$ and $\text{D}$ flip-flops connected as shown below. The output of the $\text{D}$ flip-flop is connected to the input of the $\text{T}$ flip-flop and the output of the $\text{T}$ flip-flop is connected to the input of ... $3^{\text{rd}}$ cycle are $01$ and after the $4^{\text{th}}$ cycle are $01$ respectively.
Arjun
asked
in
Digital Logic
Feb 14, 2017
by
Arjun
10.5k
views
gatecse-2017-set1
digital-logic
flip-flop
normal
0
votes
1
answer
143
Test by Bikram | Mock GATE | Test 3 | Question: 43
The characteristic expression for a new $AB$-flip-flop is given below: $Q_{n+1}$\left ( A, B, Q_{n} \right )$ = $\sim A \sim Q_{n}$ $+$ $B$Q_{n}$ , where $\sim A$ means Not $A$ or $A$ $Bar$. Identify the CORRECT statement among ... $A = 0, B = 1$ then flip flop resets. If $A = 0, B = 0$ then toggles.
Bikram
asked
in
GATE
Feb 9, 2017
by
Bikram
84
views
tbb-mockgate-3
digital-logic
flip-flop
0
votes
1
answer
144
Virtual Gate Test Series: Digital Logic - Flip Flops
The following sequential circuit has initial state $QAQB = 00$ with one input $X$ and one output $Z.$ What is the minimum input sequence which takes the machine to state $11?$ $(A) 00$ $(B) 10$ $(C) 11$ $(D)$ State $11$ is not reachable
Samujjal Das
asked
in
Digital Logic
Feb 7, 2017
by
Samujjal Das
989
views
digital-logic
sequential-circuit
flip-flop
virtual-gate-test-series
4
votes
2
answers
145
MadeEasy Subject Test: Digital Logic - Flip Flop
In the given counter circuit, the flip flops are having the propagation delay of 2ns and AND gate is having propagation delay of 1ns. What is the minimum clock rate possible to apply so that clock will work satisfactorily? A) 143 MHZ B) 200 MHZ C) 333MHZ D) NONE OF THE ABOVE Please explain the steps too
Randomeshwar
asked
in
Digital Logic
Feb 3, 2017
by
Randomeshwar
2.2k
views
digital-logic
made-easy-test-series
flip-flop
2
votes
0
answers
146
Identify MOD of the Counter
Clock Q0 Q1 Q2 State 0 0 0 0 1 1 0 0 1 2 0 1 0 2 3 1 1 0 3 4 0 0 1 4 5 1 0 1 5 At clock t5 or lets say after 5 clock pulses Q0 and Q2 becomes 1 and through NAND gate they will become 0 and since preset ... connecting clock to the gate play any significance role? Doubt is similar to the one of the gate questions asked prviously : https://gateoverflow.in/1234/gate2007-36
yg92
asked
in
Digital Logic
Jan 22, 2017
by
yg92
3.4k
views
digital-logic
digital-counter
flip-flop
sequential
combinational-circuit
1
vote
1
answer
147
Virtual Gate Test Series: Digital Logic - Flip Flop Delay
Sheshang
asked
in
Digital Logic
Jan 18, 2017
by
Sheshang
345
views
digital-logic
clock-frequency
flip-flop
virtual-gate-test-series
1
vote
1
answer
148
Switching Theory and Logic Design AnandKumar - Chapter 6 Example6-10
What is the minimum number of Synchronuous T Flip Flops Required to count the sequence 0-3-5-6-0
Anjana Babu
asked
in
Digital Logic
Jan 16, 2017
by
Anjana Babu
525
views
digital-logic
flip-flop
0
votes
1
answer
149
Minimum Number of JK Flip Flops required
What is the minimum number of JK Flip Flops required to construct counter with count sequence 0−0−0−1−1−2−2−3−3
Anjana Babu
asked
in
Digital Logic
Jan 16, 2017
by
Anjana Babu
1.3k
views
digital-logic
flip-flop
2
votes
2
answers
150
Virtual Gate Test Series: Digital Logic - Counter
smartmeet
asked
in
Digital Logic
Jan 10, 2017
by
smartmeet
382
views
digital-logic
flip-flop
digital-counter
virtual-gate-test-series
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