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Recent questions tagged flip-flop
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121
Sequential Circuits - No of flip flops required
If there are total 16 different states in a system and there is one external input, then how many flip flops are required? Is it 3 or 4 ? Thank you.
If there are total 16 different states in a system and there is one external input, then how many flip flops are required? Is it 3 or 4 ?Thank you.
Harsh Kumar
770
views
Harsh Kumar
asked
Sep 16, 2018
Digital Logic
digital-logic
flip-flop
sequential-circuit
digital-circuits
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0
votes
0
answers
122
Testbook Test Series: Digital Logic - Flip Flop
Assume the initial state of the clock and the flip flop is LOW (=0). If the frequency of the clock signal is f with 50% duty cycle and the flip-flop delay (< Tclk/2) the output frequency is ?
Assume the initial state of the clock and the flip flop is LOW (=0). If the frequency of the clock signal is f with 50% duty cycle and the flip-flop delay (< Tclk/2) the...
Prakhar Yadav 1
426
views
Prakhar Yadav 1
asked
Sep 13, 2018
Digital Logic
digital-logic
flip-flop
testbook-test-series
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0
votes
0
answers
123
JK FLip Flop
If JK Flip Flop is used then owing to it's master slave nature,doesn't the complexity of the circuitry increased?
If JK Flip Flop is used then owing to it's master slave nature,doesn't the complexity of the circuitry increased?
Devshree Dubey
456
views
Devshree Dubey
asked
Jul 28, 2018
Digital Logic
digital-logic
flip-flop
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0
votes
0
answers
124
Doubt regarding Flip Flop
How is it ascertained for a Flip Flop irrespective of it being SR,JK,T or D Flip Flop that it's NOR/NAND Gate implementation is talked of?
How is it ascertained for a Flip Flop irrespective of it being SR,JK,T or D Flip Flop that it's NOR/NAND Gate implementation is talked of?
Devshree Dubey
455
views
Devshree Dubey
asked
Jul 27, 2018
Digital Logic
digital-logic
flip-flop
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0
votes
3
answers
125
UGC NET CSE | July 2018 | Part 2 | Question: 92
In $\text{RS}$ flip-flop, the output of the flip-flop at time $(t+1)$ same as the output at time $t$, after the occurrence of a clock pulse if : $S=R=1$ $S=0, R=1$ $S=2, R=0$ $S=R=0$
In $\text{RS}$ flip-flop, the output of the flip-flop at time $(t+1)$ same as the output at time $t$, after the occurrence of a clock pulse if :$S=R=1$$S=0, R=1$$S=2, R=0...
Pooja Khatri
2.1k
views
Pooja Khatri
asked
Jul 13, 2018
Digital Logic
ugcnetcse-july2018-paper2
digital-logic
flip-flop
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0
votes
0
answers
126
T flip flops
I have seen some of the questions like ISRO 2017-ECE T- Flip flops saying that T flip flops are connected in cascade. But, I am not able to understand what is the circuit diagram... ? I mean how are they connected ? Is the output of one being fed into the input of other, or the output of one is fed into the clock input of other ? Please provide me with a circuit diagram. Thank you.
I have seen some of the questions like ISRO 2017-ECE T- Flip flops saying that T flip flops are connected in cascade. But, I am not able to understand what is the circuit...
Harsh Kumar
488
views
Harsh Kumar
asked
Jun 17, 2018
Digital Logic
digital-logic
flip-flop
digital-circuits
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–
0
votes
1
answer
127
JK Flip Flop - Frequency
Balaji Jegan
348
views
Balaji Jegan
asked
Jun 14, 2018
Digital Logic
digital-logic
flip-flop
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0
votes
2
answers
128
JK Flip Flop - Unused States
Balaji Jegan
1.3k
views
Balaji Jegan
asked
Jun 14, 2018
Digital Logic
digital-logic
flip-flop
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0
votes
1
answer
129
Counter
Answer given is 4 but mine is 2
Answer given is 4 but mine is 2
ajaysoni1924
424
views
ajaysoni1924
asked
May 22, 2018
Digital Logic
digital-logic
digital-counter
flip-flop
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0
votes
1
answer
130
Flipflop
Answer is TQ'+T'[Q(s+r')+sr']
Answer is TQ'+T'[Q(s+r')+sr']
ajaysoni1924
1.5k
views
ajaysoni1924
asked
May 22, 2018
Digital Logic
digital-logic
flip-flop
+
–
41
votes
9
answers
131
GATE CSE 2018 | Question: 22
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $\text{D}$ flip-flops. The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ____
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $\text{D}$ flip-flops.The number of states in the state trans...
gatecse
23.2k
views
gatecse
asked
Feb 14, 2018
Digital Logic
gatecse-2018
digital-logic
flip-flop
numerical-answers
normal
1-mark
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2
votes
0
answers
132
MadeEasy Test Series 2018: Digital Logic - Flip Flop
State-Diagram of a flip-flop is shown below: The next state equation of the above flip flop will be (X represent input) My doubt:- In truth table in input 00 the next state will be 1. Now this 1 is because of the state number 1 or because ... written on the edge as 0/1 ? The circled part is the state number or the output(1) from the edge 0/1 ?
State-Diagram of a flip-flop is shown below:The next state equation of the above flip flop will be (X represent input)My doubt:-In truth table in input 00 the next state...
rahul sharma 5
381
views
rahul sharma 5
asked
Jan 21, 2018
Digital Logic
made-easy-test-series
digital-logic
flip-flop
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2
votes
0
answers
133
Doubtsssss
Please tell me How to solve this question step by step
Please tell me How to solve this question step by step
nikkey123
238
views
nikkey123
asked
Jan 11, 2018
Digital Logic
digital-logic
flip-flop
+
–
2
votes
1
answer
134
Self doubt
Please tell me step by step How to solve these type of questions
Please tell me step by step How to solve these type of questions
nikkey123
309
views
nikkey123
asked
Jan 11, 2018
Digital Logic
digital-logic
flip-flop
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–
1
votes
0
answers
135
Find Mod value
Shubhanshu
164
views
Shubhanshu
asked
Jan 8, 2018
Digital Logic
digital-logic
flip-flop
+
–
2
votes
0
answers
136
Digital Logic: Counters
Consider the following question: My explanation: A clock cycle time should be large enough that all flip-flops can come in a stable state before the next clock cycle starts. Suppose cycle 1 is just completed and cycle 2 is just about to start: 1. to ... on the following link, it is $\frac{1}{20ns}$. Can someone explain, please? https://gateoverflow.in/26442/gate1991_5-c
Consider the following question:My explanation: A clock cycle time should be large enough that all flip-flops can come in a stable state before the next clock cycle start...
Manu Thakur
466
views
Manu Thakur
asked
Dec 17, 2017
Digital Logic
digital-counter
digital-circuits
flip-flop
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–
0
votes
2
answers
137
Latch
The number of D-latches present in edge-triggered D-flip flop is :- (A) 4 (B) 1 (C) 2 (D) 3
The number of D-latches present in edge-triggered D-flip flop is :-(A) 4(B) 1(C) 2(D) 3
ankitgupta.1729
876
views
ankitgupta.1729
asked
Dec 17, 2017
Digital Logic
digital-logic
flip-flop
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–
0
votes
0
answers
138
# of Ff
Number of Flipflop required to represent following states 000 -> 010 -> 011 -> 100 I think 2 is an anwer .Rt ?
Number of Flipflop required to represent following states000 - 010 - 011 - 100I think 2 is an anwer .Rt ?
hem chandra joshi
330
views
hem chandra joshi
asked
Dec 17, 2017
Digital Logic
flip-flop
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–
0
votes
1
answer
139
MadeEasy Workbook: Digital Logic - Flip Flop
Explain this question Plz
Explain this question Plz
nikkey123
1.1k
views
nikkey123
asked
Dec 16, 2017
Digital Logic
made-easy-test-series
digital-logic
flip-flop
made-easy-booklet
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–
1
votes
0
answers
140
MadeEasy Workbook: Digital Logic - Flip Flop
Please explain question 17
Please explain question 17
nikkey123
657
views
nikkey123
asked
Dec 16, 2017
Digital Logic
made-easy-test-series
digital-logic
flip-flop
+
–
0
votes
0
answers
141
MadeEasy Test Series: Digital Logic - Flip Flop
pranab ray
265
views
pranab ray
asked
Dec 14, 2017
Digital Logic
made-easy-test-series
digital-logic
flip-flop
+
–
4
votes
2
answers
142
Virtual Gate Test Series: Digital Logic - Flip Flops
Manoja Rajalakshmi A
1.2k
views
Manoja Rajalakshmi A
asked
Nov 13, 2017
Digital Logic
digital-logic
sequential-circuit
flip-flop
circuit-output
virtual-gate-test-series
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–
1
votes
0
answers
143
counters
If a full modulus counter having 10 flipflops is initially at 0. After how many pulses it will count 0000001100 ? (A) 2060 (B) 1036 (C) 3048 (D) ALL
If a full modulus counter having 10 flipflops is initially at 0. After how many pulses it will count 0000001100 ?(A) 2060(B) 1036(C) 3048(D) ALL
Parshu gate
731
views
Parshu gate
asked
Nov 11, 2017
Digital Logic
digital-counter
flip-flop
+
–
1
votes
1
answer
144
counters
mod 1 mod 3 mod 4 mod 2
mod 1 mod 3 mod 4 mod 2
Parshu gate
715
views
Parshu gate
asked
Nov 10, 2017
Digital Logic
digital-counter
flip-flop
digital-circuits
+
–
1
votes
1
answer
145
Flip flops
Consider the complemented circuit shown below: If the initial value of the output Q1 Q0 is 00, then the next three values of Q1 Q0 are:- 10,01,01,00 10,01,11,00 10,01,00,01 10,01,10,00 Doubt:- I am getting a sequence which is not matching with any of the option
Consider the complemented circuit shown below:If the initial value of the output Q1 Q0 is 00, then the next three values of Q1 Q0 are:- 10,01,01,00 10,01,11,00 10,01,0...
akb1115
1.3k
views
akb1115
asked
Nov 8, 2017
Digital Logic
digital-logic
flip-flop
digital-circuits
digital-counter
sequential
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–
0
votes
0
answers
146
Digital Logic - Output waveforms for a negative edge triggered J-K flip-flop.
Garrett McClure
1.1k
views
Garrett McClure
asked
Nov 6, 2017
Digital Logic
digital-logic
digital-circuits
flip-flop
+
–
0
votes
1
answer
147
COUNTER USING JK FLIPFLOP
Parshu gate
613
views
Parshu gate
asked
Nov 6, 2017
Digital Logic
flip-flop
digital-logic
+
–
1
votes
0
answers
148
Given a programmable logic device (PLD) with 20 inputs, 20 product terms, and 20 outputs. Answer the following.
Garrett McClure
327
views
Garrett McClure
asked
Nov 5, 2017
Digital Logic
digital-logic
digital-circuits
flip-flop
+
–
2
votes
1
answer
149
Given T flip-flop in 0 state, what is the sequence of inputs necessary to cause the following sequence of states
Given a T flip-flop in the 0 state, what is the sequence of inputs necessary to cause the following sequence of states:0, 1, 1, 1, 0, 0, 1, 0, 1, 0.
Garrett McClure
1.4k
views
Garrett McClure
asked
Nov 2, 2017
Digital Logic
flip-flop
digital-logic
digital-circuits
+
–
0
votes
0
answers
150
Given J-K flip-flop in 0 state, what is the sequence of inputs necessary to cause the following sequence of states
Given a J-K flip-flop in the 0 state what is the sequence of states for the following sequence of inputs:00, 01, 10, 11, 11, 00, 00, 11, 01, 10.
Garrett McClure
402
views
Garrett McClure
asked
Oct 31, 2017
Digital Logic
flip-flop
digital-logic
digital-circuits
+
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