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Recent questions tagged flip-flop
1
vote
1
answer
151
Virtual Gate Test Series: Digital Logic - Flip Flop Delay
Sheshang
asked
in
Digital Logic
Jan 18, 2017
by
Sheshang
345
views
digital-logic
clock-frequency
flip-flop
virtual-gate-test-series
1
vote
1
answer
152
Switching Theory and Logic Design AnandKumar - Chapter 6 Example6-10
What is the minimum number of Synchronuous T Flip Flops Required to count the sequence 0-3-5-6-0
Anjana Babu
asked
in
Digital Logic
Jan 16, 2017
by
Anjana Babu
525
views
digital-logic
flip-flop
0
votes
1
answer
153
Minimum Number of JK Flip Flops required
What is the minimum number of JK Flip Flops required to construct counter with count sequence 0−0−0−1−1−2−2−3−3
Anjana Babu
asked
in
Digital Logic
Jan 16, 2017
by
Anjana Babu
1.3k
views
digital-logic
flip-flop
2
votes
2
answers
154
Virtual Gate Test Series: Digital Logic - Counter
smartmeet
asked
in
Digital Logic
Jan 10, 2017
by
smartmeet
382
views
digital-logic
flip-flop
digital-counter
virtual-gate-test-series
0
votes
2
answers
155
MadeEasy Subject Test: Digital Logic - Flip Flop
Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be Q1 Q0 = 00 For an input sequence X = 1010, the respective output sequence will be _______.
Pankaj Joshi
asked
in
Digital Logic
Dec 26, 2016
by
Pankaj Joshi
497
views
made-easy-test-series
digital-logic
flip-flop
2
votes
0
answers
156
Digital Logic Mater Slave flip flop
In Master Slave concept it states that Master works when clock goes from o to 1(assume +ve adge triggered),and slave works when clock goes from 1 to 0 ,so it means effective work is done only in half of the clock time and for the ... thing apply to all +ve edge trigered circuits that they works only for half of the clock duration? I hope question makes sense?
rahul sharma 5
asked
in
Digital Logic
Dec 22, 2016
by
rahul sharma 5
211
views
digital-logic
flip-flop
digital-circuits
0
votes
1
answer
157
MadeEasy Test Series: Digital Logic - Flip Flop
#plz check its 256 or 512... according to me its 512
Hradesh patel
asked
in
Digital Logic
Dec 1, 2016
by
Hradesh patel
237
views
made-easy-test-series
digital-logic
flip-flop
15
votes
4
answers
158
ME test
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of the MOD256 counter ? (in MHz)
Lokesh .
asked
in
Digital Logic
Nov 25, 2016
by
Lokesh .
2.8k
views
digital-logic
digital-counter
flip-flop
20
votes
4
answers
159
GATE CSE 1990 | Question: 5-c
For the synchronous counter shown in Fig$.3,$ write the truth table of $Q_{0}, Q_{1}$, and $Q_{2}$ after each pulse, starting from $Q_{0}=Q_{1}=Q_{2}=0$ and determine the counting sequence and also the modulus of the counter.
makhdoom ghaya
asked
in
Digital Logic
Nov 24, 2016
by
makhdoom ghaya
4.2k
views
gate1990
descriptive
digital-logic
sequential-circuit
flip-flop
digital-counter
7
votes
1
answer
160
Self Doubt | Modulus Counter
Q1. How many flip-flops are required to construct mod 4 counter? Ans - 2 right ? Alway it should be 2 or it may not be 2. Q2 . If We want to design a synchronous counter that counts the sequence 0−1−0−2−0−3 and then repeats. A) What ... design-modulo-272-counter https://gateoverflow.in/82111/is-bcd-or-mod-10-counter-are-same https://gateoverflow.in/39670/gate-2016-1-8
vijaycs
asked
in
Digital Logic
Nov 22, 2016
by
vijaycs
1.1k
views
digital-logic
digital-counter
flip-flop
4
votes
1
answer
161
GATE CSE 1987 | Question: 1-III
The above circuit produces the output sequence: $1111\quad 1111\quad0000\quad0000$ $1111 \quad 0000\quad1111\quad0000$ $1111 \quad 0001\quad0011\quad0101$ $1010\quad1010\quad1010\quad1010$
makhdoom ghaya
asked
in
Digital Logic
Nov 7, 2016
by
makhdoom ghaya
3.5k
views
gate1987
digital-logic
sequential-circuit
flip-flop
digital-counter
0
votes
0
answers
162
flip flop
Which one of the given state transitions is not possible for the given flip-flop? 0 → 1 1→ 0 0 → 0 1 → 1
Shashank Chandekar
asked
in
Digital Logic
Nov 7, 2016
by
Shashank Chandekar
307
views
digital-logic
flip-flop
1
vote
1
answer
163
flip flop
Given the sequence 010202010 is generated from a sequential circuit of n flip-flops. And these flip-flops generate the sequence respectively. What is the minimum value of n? 3 4 5 6
Shashank Chandekar
asked
in
Digital Logic
Nov 7, 2016
by
Shashank Chandekar
495
views
flip-flop
digital-logic
3
votes
1
answer
164
Digital Counters
Q..A 4 bit Counter having flip-flops with identical propagation delay time of 50ns will have maximum frequency limit of ____ MHZ??? My question is how to know wheather the question is talking about Synchronous counter or Asynchronous counter??? For Sync. it will be 1/50ns for Async. it will be 1/(4*50)ns which obe to take?????
bad_engineer
asked
in
Digital Logic
Oct 26, 2016
by
bad_engineer
585
views
digital-logic
digital-counter
flip-flop
testbook-test-series
1
vote
1
answer
165
Counter
4-bit 16 module ripple counter uses JK-flip flop.propagation delay of each flip flop is 50ns find max clock frequncy.
papesh
asked
in
Digital Logic
Oct 4, 2016
by
papesh
981
views
digital-counter
flip-flop
1
vote
1
answer
166
MadeEasy Workbook: Digital Logic - Flip Flop
to complete the circuit what is the value of X?? A) Q2' B) Q1 + Q2 C) (Q1 ex-or Q2)' D) (Q1 ex-or Q2)
Hradesh patel
asked
in
Digital Logic
Oct 1, 2016
by
Hradesh patel
191
views
made-easy-booklet
digital-logic
flip-flop
2
votes
0
answers
167
MadeEasy Workbook: Digital Logic - Flip Flop
Hradesh patel
asked
in
Digital Logic
Oct 1, 2016
by
Hradesh patel
140
views
made-easy-booklet
digital-logic
flip-flop
0
votes
1
answer
168
How can I construct a function table and excitation table from the given realisation?
How can I construct a function table and excitation table from the given realisation, Please explain
Alex Louis
asked
in
Digital Logic
Sep 26, 2016
by
Alex Louis
471
views
digital-logic
flip-flop
0
votes
0
answers
169
GATE Overflow | Digital Logic | Test 1 | Question: 16
The output of a gated S-R flip-flop changes only if the: flip-flop is set control input data has changed flip-flop is reset input data has no change
Bikram
asked
in
Digital Logic
Sep 20, 2016
by
Bikram
245
views
digital-logic
go-digital-logic-1
flip-flop
1
vote
3
answers
170
GATE Overflow | Digital Logic | Test 1 | Question: 6
The minimum number of Flip-Flops required to construct a binary Modulo $n$ counter is ________ $n$ $n-1$ $2^n – 1$ $\lceil \log_2 n \rceil$
Bikram
asked
in
Digital Logic
Sep 20, 2016
by
Bikram
280
views
digital-logic
go-digital-logic-1
flip-flop
digital-counter
0
votes
2
answers
171
UGC NET CSE | December 2010 | Part 2 | Question: 8
An Astable multivibrator has : One stable state Two stable states No stable states None of these
makhdoom ghaya
asked
in
Digital Logic
Sep 5, 2016
by
makhdoom ghaya
1.1k
views
ugcnetcse-dec2010-paper2
digital-logic
flip-flop
0
votes
1
answer
172
UGC NET CSE | Junet 2015 | Part 3 | Question: 6
The number of flip-flops required to design a modulo -272 counter is 8 9 27 11
go_editor
asked
in
Digital Logic
Jul 31, 2016
by
go_editor
2.6k
views
ugcnetcse-june2015-paper3
digital-logic
sequential-circuit
flip-flop
0
votes
1
answer
173
UGC NET CSE | September 2013 | Part 3 | Question: 35
An Astable multi vibrator using the $555$ timer to generate a square wave of $5$ KHz with $70\%$ duty cycle will have : $R_A =40.4 K \Omega, R_B = 17.25 K \Omega, C=2000 pF$ $R_A =17.25 K \Omega, R_B = 40.4 K \Omega, C=2000 pF$ $R_A =40.4 K \Omega, R_B = 17.25 K \Omega, C=5000 pF$ $R_A =17.25 K \Omega, R_B = 40.4 K \Omega, C=5000 pF$
go_editor
asked
in
Digital Logic
Jul 24, 2016
by
go_editor
1.2k
views
ugcnetcse-sep2013-paper3
digital-logic
flip-flop
0
votes
1
answer
174
UGC NET CSE | September 2013 | Part 3 | Question: 34
The power dissipation of a flip-flop is $3$ mW. The power dissipation of a digital system with $4$ flip-flops is given by : $3^4$ mW $4^3$ mW $4/3$ mW $12$ mW
go_editor
asked
in
Digital Logic
Jul 24, 2016
by
go_editor
1.2k
views
ugcnetcse-sep2013-paper3
digital-logic
flip-flop
6
votes
1
answer
175
UGC NET CSE | June 2016 | Part 2 | Question: 10
In a positive edge triggered $J$-$K$ flip flop , if $J$ and $K$ both are high then the output will be ______on the rising edge of the clock : No change Set Reset Toggle
Sanjay Sharma
asked
in
Digital Logic
Jul 11, 2016
by
Sanjay Sharma
3.6k
views
ugcnetcse-june2016-paper2
digital-logic
flip-flop
1
vote
2
answers
176
UGC NET CSE | June 2014 | Part 3 | Question: 44
Which of the following flip-flops is free from race condition ? $T$ flip-flop $SR$ flip-flop Master-slave $JK$ flip-flop None of the above
makhdoom ghaya
asked
in
Digital Logic
Jul 10, 2016
by
makhdoom ghaya
1.7k
views
ugcnetjune2014iii
digital-logic
sequential-circuit
flip-flop
4
votes
3
answers
177
ISRO2016-18
The functional difference between $SR$ flip-flop and $J$-$K$ flip-flop is that : $J$-$K$ flip-flop is faster than $SR$ flip-flop $J$-$K$ flip-flop has a feedback path $J$-$K$ flip-flop accepts both inputs $1$ None of them
sourav.
asked
in
Digital Logic
Jul 3, 2016
by
sourav.
5.3k
views
digital-logic
flip-flop
isro2016
6
votes
2
answers
178
ISRO2011-74
In an $RS$ flip-flop, if the $S$ line (Set line) is set high ($1$) and the $R$ line (Reset line) is set low ($0$), then the state of the flip-flop is : Set to $1$ Set to $0$ No change in state Forbidden
go_editor
asked
in
Digital Logic
Jun 23, 2016
by
go_editor
2.8k
views
isro2011
digital-logic
flip-flop
5
votes
3
answers
179
ISRO2007-05
The characteristic equation of an $SR$ flip-flop is given by : $Q_{n+1}=S+RQ_n$ $Q_{n+1}=R\bar{Q}_n + \bar{S}Q_n$ $Q_{n+1}=\bar{S}+RQ_n$ $Q_{n+1}=S+\bar{R}Q_n$
go_editor
asked
in
Digital Logic
Jun 10, 2016
by
go_editor
10.0k
views
isro2007
digital-logic
flip-flop
2
votes
2
answers
180
why nodes with 2 children have degree 3 in a binary tree?
sh!va
asked
in
Unknown Category
Jun 4, 2016
by
sh!va
1.0k
views
binary-tree
algorithms
flip-flop
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