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Recent questions tagged flip-flop
9
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2
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181
Design a counter for the following binary sequence: 0,4,5,3,1,6,2,7 and repeat.Use JK flip-flops | IIIT-Hyderbad
pC
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in
Digital Logic
Apr 7, 2016
by
pC
23.3k
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digital-logic
flip-flop
103
votes
19
answers
182
GATE CSE 2016 Set 1 | Question: 8
We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.
Sandeep Singh
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Digital Logic
Feb 12, 2016
by
Sandeep Singh
43.3k
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gatecse-2016-set1
digital-logic
digital-counter
flip-flop
normal
numerical-answers
0
votes
1
answer
183
T flipflop counters
What will be the value of G1 and G2 how to calculate them?
Pradip Nichite
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in
Digital Logic
Jan 18, 2016
by
Pradip Nichite
225
views
flip-flop
digital-counter
0
votes
2
answers
184
flip flip output
I think given answer is wrong. can anybody help?
Pradip Nichite
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in
Digital Logic
Jan 14, 2016
by
Pradip Nichite
243
views
digital-logic
flip-flop
1
vote
1
answer
185
What is the o/p according to given timing diagram?
a) A = 0, 1, 0, 0, B = 1, 0, 1, 1 b) A = 1, 0, 1, 1, B = 0, 1, 0, 0 c) A = 1, 1, 0, 0, B = 1, 1, 0, 0 d) A = 0, 1, 0, 0, B = 0, 1, 0, 0 I thought it would be (c) as previous states should persist for 1st clock. But answer given is (a). Can somebody please explain??
Tushar Shinde
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in
Digital Logic
Dec 30, 2015
by
Tushar Shinde
576
views
digital-logic
flip-flop
clock-frequency
0
votes
2
answers
186
A switch tail ring counter is made by using a single D FF.
A switch-tail ring counter is made by using a single D FF. The resulting circuit is (a) SR flip-flop (b) JK flip-flop (c) D flip-flop (d) T flip-flop
Payal Rastogi
asked
in
Digital Logic
Dec 26, 2015
by
Payal Rastogi
12.0k
views
sequential
digital-logic
flip-flop
1
vote
1
answer
187
When a JK flip flop is constructed from an SR flip flop
When a J-K flip-flop is constructed from an SR flip-flop a) S = JQ, R = K+JQ b) J = S, K = R c) J = SR'Q, K = S'(R+Q) d) S = JQ', R = KQ
Payal Rastogi
asked
in
Digital Logic
Dec 26, 2015
by
Payal Rastogi
1.2k
views
flip-flop
digital-logic
53
votes
4
answers
188
GATE CSE 1991 | Question: 5-c
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10\;\text{ns}$. Also, assume that the setup time for the $JK$ inputs of the flip flops is negligible.
ibia
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in
Digital Logic
Nov 14, 2015
by
ibia
17.9k
views
gate1991
digital-logic
sequential-circuit
flip-flop
digital-counter
0
votes
2
answers
189
What happens when the input of a flip flop changes exactly at the time of the clock pulse transition?
Akshay Jindal
asked
in
Digital Logic
Sep 27, 2015
by
Akshay Jindal
446
views
flip-flop
digital-logic
23
votes
4
answers
190
GATE1992-04-c
Design a $3$-bit counter using D-flip flops such that not more than one flip-flop changes state between any two consecutive states.
Arjun
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in
Digital Logic
Sep 22, 2015
by
Arjun
2.4k
views
gate1992
digital-logic
sequential-circuit
flip-flop
digital-counter
normal
descriptive
31
votes
9
answers
191
GATE CSE 1993 | Question: 6-3
For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is: Shift Register $\text{Mod- 3}$ Counter $\text{Mod- 6}$ Counter $\text{Mod- 2}$ Counter None of the above
go_editor
asked
in
Digital Logic
Sep 20, 2015
by
go_editor
9.3k
views
gate1993
digital-logic
sequential-circuit
flip-flop
digital-counter
circuit-output
multiple-selects
41
votes
7
answers
192
GATE CSE 2015 Set 1 | Question: 37
A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the $J$ and $K$ inputs of the $JK$ ... $JK$ flip-flops. Both the flip-flops have non-zero propagation delays. $0110110\ldots$ $0100100\ldots$ $011101110\ldots$ $011001100\ldots$
makhdoom ghaya
asked
in
Digital Logic
Feb 13, 2015
by
makhdoom ghaya
9.9k
views
gatecse-2015-set1
digital-logic
flip-flop
normal
43
votes
5
answers
193
GATE IT 2007 | Question: 7
Which of the following input sequences for a cross-coupled $R-S$ flip-flop realized with two $NAND$ gates may lead to an oscillation? $11, 00$ $01, 10$ $10, 01$ $00, 11$
Ishrat Jahan
asked
in
Digital Logic
Oct 30, 2014
by
Ishrat Jahan
18.2k
views
gateit-2007
digital-logic
normal
flip-flop
17
votes
1
answer
194
GATE CSE 1994 | Question: 2-1
The number of flip-flops required to construct a binary modulo $N$ counter is __________
Kathleen
asked
in
Digital Logic
Oct 4, 2014
by
Kathleen
5.1k
views
gate1994
digital-logic
sequential-circuit
flip-flop
digital-counter
fill-in-the-blanks
18
votes
1
answer
195
GATE CSE 1993 | Question: 19
A control algorithm is implemented by the NAND – gate circuitry given in figure below, where $A$ and $B$ are state variable implemented by $D$ flip-flops, and $P$ is control input. Develop the state transition table for this controller.
Kathleen
asked
in
Digital Logic
Sep 30, 2014
by
Kathleen
2.4k
views
gate1993
digital-logic
sequential-circuit
flip-flop
circuit-output
normal
descriptive
24
votes
4
answers
196
GATE CSE 2011 | Question: 50
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. If at some instance prior to the occurrence of the clock edge, $P, Q$ and $R$ have a value $0$, $1$ and $0$ respectively, what shall be the value of $PQR$ after the clock edge? $000$ $001$ $010$ $011$
go_editor
asked
in
Digital Logic
Sep 29, 2014
by
go_editor
9.0k
views
gatecse-2011
digital-logic
circuit-output
flip-flop
normal
46
votes
8
answers
197
GATE CSE 2004 | Question: 18, ISRO2007-31
In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in $Q = 0, Q' = 1$ $Q = 1, Q' = 0$ $Q = 1, Q' = 1$ Indeterminate states
Kathleen
asked
in
Digital Logic
Sep 19, 2014
by
Kathleen
17.7k
views
gatecse-2004
digital-logic
easy
isro2007
flip-flop
23
votes
2
answers
198
GATE CSE 2001 | Question: 11
A sequential circuit takes an input stream of $0's$ and $1's$ and produces an output stream of $0's$ and $1's.$ Initially it replicates the input on its output until two consecutive $0's$ are encountered on the input. From then onward, it ... diagram Give the minimized sum-of-product expression for $\text{J}$ and $\text{K}$ inputs of one of its state flip-flops
Kathleen
asked
in
Digital Logic
Sep 15, 2014
by
Kathleen
3.6k
views
gatecse-2001
digital-logic
normal
descriptive
flip-flop
35
votes
5
answers
199
GATE CSE 2000 | Question: 2.12
The following arrangement of master-slave flip flops has the initial state of $P, Q$ as $0, 1$ (respectively). After three clock cycles the output state $P, Q$ is (respectively), $1, 0$ $1, 1$ $0, 0$ $0, 1$
Kathleen
asked
in
Digital Logic
Sep 14, 2014
by
Kathleen
8.7k
views
gatecse-2000
digital-logic
circuit-output
normal
flip-flop
5
votes
1
answer
200
GATE CSE 1991 | Question: 06,a
Using $\text{D}$ flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines: Clock $\text{CLK}$ Three parallel data inputs $A, B, C$ Serial input $S$ Control input $\text{load} / \overline{\text{SHIFT}}$.
Kathleen
asked
in
Digital Logic
Sep 13, 2014
by
Kathleen
832
views
gate1991
digital-logic
difficult
sequential-circuit
flip-flop
shift-registers
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