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Recent questions tagged flip-flop

1 votes
1 answer
181
Switching Theory and Logic Design AnandKumar - Chapter 6 Example6-10
What is the minimum number of Synchronuous T Flip Flops Required to count the sequence 0-3-5-6-0
What is the minimum number of Synchronuous T Flip Flops Required to count the sequence 0-3-5-6-0
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0 votes
1 answer
182
Minimum Number of JK Flip Flops required
What is the minimum number of JK Flip Flops required to construct counter with count sequence 0−0−0−1−1−2−2−3−3
What is the minimum number of JK Flip Flops required to construct counter with count sequence 0−0−0−1−1−2−2−3−3
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0 votes
2 answers
184
MadeEasy Subject Test: Digital Logic - Flip Flop
Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be Q1 Q0 = 00 For an input sequence X = 1010, the respective output sequence will be _______.
Consider a clocked sequential circuit as shown in the figure below. Assuming initial state to be Q1 Q0 = 00For an input sequence X = 1010, the respective output sequence ...
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15 votes
4 answers
187
ME test
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of the MOD256 counter ? (in MHz)
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the...
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6 votes
1 answer
190
GATE CSE 1987 | Question: 1-III
The above circuit produces the output sequence: $1111\quad 1111\quad0000\quad0000$ $1111 \quad 0000\quad1111\quad0000$ $1111 \quad 0001\quad0011\quad0101$ $1010\quad1010\quad1010\quad1010$
The above circuit produces the output sequence:$1111\quad 1111\quad0000\quad0000$$1111 \quad 0000\quad1111\quad0000$$1111 \quad 0001\quad0011\quad0101$$1010\quad1010\quad...
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0 votes
0 answers
191
flip flop
Which one of the given state transitions is not possible for the given flip-flop? 0 → 1 ​​​​​​​ 1→ 0 ​​​​​​​ 0 → 0 ​​​​​​​ 1 → 1
Which one of the given state transitions is not possible for the given flip-flop? 0 → 1 ​​​​​​​ 1→ 0 ​​​​​​​ 0 → 0 ​​​​​​�...
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1 votes
1 answer
192
flip flop
Given the sequence 010202010 is generated from a sequential circuit of n flip-flops. And these flip-flops generate the sequence respectively. What is the minimum value of n? 3 4 5 ​​​​​​​ 6
Given the sequence 010202010 is generated from a sequential circuit of n flip-flops. And these flip-flops generate the sequence respectively. What is the minimum value of...
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1 votes
1 answer
194
Counter
4-bit 16 module ripple counter uses JK-flip flop.propagation delay of each flip flop is 50ns find max clock frequncy.
4-bit 16 module ripple counter uses JK-flip flop.propagation delay of each flip flop is 50ns find max clock frequncy.
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1 votes
1 answer
195
MadeEasy Workbook: Digital Logic - Flip Flop
to complete the circuit what is the value of X?? A) Q2' B) Q1 + Q2 C) (Q1 ex-or Q2)' D) (Q1 ex-or Q2)
to complete the circuit what is the value of X?? A) Q2' B) Q1 + Q2 C) (Q1 ex-or Q2)' D) (Q1 ex-or Q2)
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0 votes
1 answer
197
How can I construct a function table and excitation table from the given realisation?
How can I construct a function table and excitation table from the given realisation, Please explain
How can I construct a function table and excitation table from the given realisation, Please explain
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1 votes
1 answer
198
GATE Overflow | Digital Logic | Test 1 | Question: 16
The output of a gated S-R flip-flop changes only if the: flip-flop is set control input data has changed flip-flop is reset input data has no change
The output of a gated S-R flip-flop changes only if the:flip-flop is setcontrol input data has changedflip-flop is resetinput data has no change
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1 votes
3 answers
199
GATE Overflow | Digital Logic | Test 1 | Question: 6
The minimum number of Flip-Flops required to construct a binary Modulo $n$ counter is ________ $n$ $n-1$ $2^n – 1$ $\lceil \log_2 n \rceil$
The minimum number of Flip-Flops required to construct a binary Modulo $n$ counter is ________$n$$n-1$$2^n – 1$$\lceil \log_2 n \rceil$
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0 votes
2 answers
200
UGC NET CSE | December 2010 | Part 2 | Question: 8
An Astable multivibrator has : One stable state Two stable states No stable states None of these
An Astable multivibrator has :One stable stateTwo stable statesNo stable statesNone of these
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0 votes
1 answer
203
UGC NET CSE | September 2013 | Part 3 | Question: 34
The power dissipation of a flip-flop is $3$ mW. The power dissipation of a digital system with $4$ flip-flops is given by : $3^4$ mW $4^3$ mW $4/3$ mW $12$ mW
The power dissipation of a flip-flop is $3$ mW. The power dissipation of a digital system with $4$ flip-flops is given by :$3^4$ mW$4^3$ mW$4/3$ mW$12$ mW
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6 votes
1 answer
204
UGC NET CSE | June 2016 | Part 2 | Question: 10
In a positive edge triggered $J$-$K$ flip flop , if $J$ and $K$ both are high then the output will be ______on the rising edge of the clock : No change Set Reset Toggle
In a positive edge triggered $J$-$K$ flip flop , if $J$ and $K$ both are high then the output will be ______on the rising edge of the clock :No changeSetResetToggle
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1 votes
2 answers
205
UGC NET CSE | June 2014 | Part 3 | Question: 44
Which of the following flip-flops is free from race condition ? $T$ flip-flop $SR$ flip-flop Master-slave $JK$ flip-flop None of the above
Which of the following flip-flops is free from race condition ?$T$ flip-flop$SR$ flip-flop Master-slave $JK$ flip-flop None of the above
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4 votes
3 answers
206
ISRO2016-18
The functional difference between $SR$ flip-flop and $J$-$K$ flip-flop is that : $J$-$K$ flip-flop is faster than $SR$ flip-flop $J$-$K$ flip-flop has a feedback path $J$-$K$ flip-flop accepts both inputs $1$ None of them
The functional difference between $SR$ flip-flop and $J$-$K$ flip-flop is that :$J$-$K$ flip-flop is faster than $SR$ flip-flop$J$-$K$ flip-flop has a feedback path$J$-$K...
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6 votes
3 answers
207
ISRO2011-74
In an $RS$ flip-flop, if the $S$ line (Set line) is set high ($1$) and the $R$ line (Reset line) is set low ($0$), then the state of the flip-flop is : Set to $1$ Set to $0$ No change in state Forbidden
In an $RS$ flip-flop, if the $S$ line (Set line) is set high ($1$) and the $R$ line (Reset line) is set low ($0$), then the state of the flip-flop is :Set to $1$Set to $0...
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5 votes
3 answers
208
ISRO2007-05
The characteristic equation of an $SR$ flip-flop is given by : $Q_{n+1}=S+RQ_n$ $Q_{n+1}=R\bar{Q}_n + \bar{S}Q_n$ $Q_{n+1}=\bar{S}+RQ_n$ $Q_{n+1}=S+\bar{R}Q_n$
The characteristic equation of an $SR$ flip-flop is given by :$Q_{n+1}=S+RQ_n$$Q_{n+1}=R\bar{Q}_n + \bar{S}Q_n$$Q_{n+1}=\bar{S}+RQ_n$$Q_{n+1}=S+\bar{R}Q_n$
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2 votes
2 answers
210
flip flops
Which of the following flip-flops is free from race condition ? (A) T flip-flop (B) SR flip-flop (C) Master-slave JK flip-flop (D) None of the above
Which of the following flip-flops is free from race condition ?(A) T flip-flop(B) SR flip-flop(C) Master-slave JK flip-flop(D) None of the above
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