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Recent questions tagged flip-flop
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31
NIELIT 2017 OCT Scientific Assistant A (IT) - Section D: 10
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
Lakshman Patel RJIT
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Digital Logic
Aug 28, 2020
by
Lakshman Patel RJIT
599
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nielit2017oct-assistanta-it
digital-logic
sequential-circuit
flip-flop
digital-counter
0
votes
3
answers
32
NIELIT 2017 OCT Scientific Assistant A (CS) - Section D: 9
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ ... $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
Lakshman Patel RJIT
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in
Digital Logic
Aug 28, 2020
by
Lakshman Patel RJIT
1.3k
views
nielit2017oct-assistanta-cs
digital-logic
sequential-circuit
flip-flop
1
vote
2
answers
33
NIELIT 2017 OCT Scientific Assistant A (CS) - Section D: 10
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
Lakshman Patel RJIT
asked
in
Digital Logic
Aug 28, 2020
by
Lakshman Patel RJIT
504
views
nielit2017oct-assistanta-cs
digital-logic
sequential-circuit
flip-flop
digital-counter
0
votes
2
answers
34
NIELIT 2016 MAR Scientist C - Section C: 40
If the input $\text{J}$ is connected through $\text{K}$ input of $\text{J-K}$, then flip-flop will behave as a D type flip-flop T type flip-flop S-R flip-flop Toggle switch
Lakshman Patel RJIT
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in
Digital Logic
Apr 2, 2020
by
Lakshman Patel RJIT
326
views
nielit2016mar-scientistc
digital-logic
flip-flop
0
votes
1
answer
35
NIELIT 2016 MAR Scientist C - Section C: 41
To build a mod-$19$ counter the number of flip-flop required is $3$ $5$ $7$ $8$
Lakshman Patel RJIT
asked
in
Digital Logic
Apr 2, 2020
by
Lakshman Patel RJIT
565
views
nielit2016mar-scientistc
digital-logic
flip-flop
0
votes
1
answer
36
NIELIT 2016 MAR Scientist C - Section C: 44
Which of the following conditions must be met to avoid race around problem? $\Delta t< t_{p}< T$ $T>\Delta t> t_{p}$ $2t_{p}< \Delta t< T$ none of these
Lakshman Patel RJIT
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in
Digital Logic
Apr 2, 2020
by
Lakshman Patel RJIT
520
views
nielit2016mar-scientistc
digital-logic
flip-flop
0
votes
2
answers
37
NIELIT 2016 MAR Scientist C - Section C: 64
How many flip-flop are needed to divide the input frequency by $64$? $4$ $5$ $6$ $8$
Lakshman Patel RJIT
asked
in
Digital Logic
Apr 2, 2020
by
Lakshman Patel RJIT
719
views
nielit2016mar-scientistc
digital-logic
flip-flop
0
votes
0
answers
38
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 19
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip-flops Clock input of one flip-flop
Lakshman Patel RJIT
asked
in
Digital Logic
Apr 1, 2020
by
Lakshman Patel RJIT
318
views
nielit2017oct-assistanta-it
digital-logic
sequential-circuit
flip-flop
0
votes
3
answers
39
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 33
The number of columns in a state table for a sequential circuit with $’m’$ flip flops and $’n’$ input is $m+n$ $m+2n$ $2m+n$ $2m+2n$
Lakshman Patel RJIT
asked
in
Digital Logic
Apr 1, 2020
by
Lakshman Patel RJIT
635
views
nielit2017oct-assistanta-it
digital-logic
sequential-circuit
flip-flop
0
votes
2
answers
40
NIELIT 2017 OCT Scientific Assistant A (CS) - Section C: 8
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip flops Clock input of one flip-flop
Lakshman Patel RJIT
asked
in
Digital Logic
Apr 1, 2020
by
Lakshman Patel RJIT
365
views
nielit2017oct-assistanta-cs
digital-logic
sequential-circuit
flip-flop
2
votes
1
answer
41
NIELIT 2016 MAR Scientist B - Section C: 4
In a ripple counter using edge triggered $JK$ flip-flops, the pulse input is applied to the clock input of all flip-flops clock input of one flip-flop $J$ and $K$ inputs of all flip-flops $J$ and $K$ inputs of one flip flop
Lakshman Patel RJIT
asked
in
Digital Logic
Mar 31, 2020
by
Lakshman Patel RJIT
1.5k
views
nielit2016mar-scientistb
digital-logic
sequential-circuit
flip-flop
2
votes
2
answers
42
NIELIT 2016 DEC Scientist B (IT) - Section B: 35
What will be the final output of D flip-Flop if the input string is $0010011100$? $1$ $0$ Don’t Care None of the above
Lakshman Patel RJIT
asked
in
Digital Logic
Mar 31, 2020
by
Lakshman Patel RJIT
1.4k
views
nielit2016dec-scientistb-it
digital-logic
sequential-circuit
flip-flop
0
votes
2
answers
43
UGC NET CSE | January 2017 | Part 2 | Question: 8
A binary $3$-bit down counter uses $J$-$K$ flip-flops, $FF_{i}$ with inputs $J_{i}$, $K_{i}$ and outputs $Q_{i}$, $i$ = $0, 1, 2$ respectively. The minimized expression for the input from following is : $J_{0} = K_{0} = 0$ $J_{0} = K_{0} = 1$ ... $J_{2} = K_{2} =\overline{Q}_{1} \overline{Q}_{0}$ I, III, V I, IV, VI II, III, V II, IV, VI
go_editor
asked
in
Digital Logic
Mar 24, 2020
by
go_editor
518
views
ugcnetjan2017ii
digital-logic
flip-flop
3
votes
1
answer
44
ISRO2020-80
A new flipflop with inputs $X$ and $Y$ ... $(X\wedge \overline{Q })\vee (Y \wedge Q)$ $(X\wedge \overline{Q })\vee (\overline{Y } \wedge Q)$
Satbir
asked
in
Digital Logic
Jan 13, 2020
by
Satbir
1.5k
views
isro-2020
digital-logic
sequential-circuit
flip-flop
normal
1
vote
1
answer
45
Made Easy Test Series:Flip-Flop
A Finite State Machine(FSM) is implemented using the D-FFs A and B with logic gates as shown below. The four possible states of FSM are $Q_{A}Q_{B}=00,01,10,11$. Assume that $X_{in}$ is held at constant logic level throughout the operation of FSM. ... states if $X_{in}=0$ How do we check $X_{in}$ here? Can we check it arbitrarily, or checked with prev states??
srestha
asked
in
Digital Logic
May 16, 2019
by
srestha
908
views
digital-logic
flip-flop
made-easy-test-series
0
votes
1
answer
46
Made Easy Test Series: Digital Logic- Master Slave FF
$1)$ Master-Slave FF is designed to avoid race around condition $2)$ Master-Slave FF is used to store $2$ bit information Which of the following statement is correct? What is meaning of $2-bit $ information??
srestha
asked
in
Digital Logic
May 15, 2019
by
srestha
1.3k
views
digital-logic
made-easy-test-series
flip-flop
0
votes
0
answers
47
Morris Mano Edition 3 Exercise 9 Question 9 (Page No. 394)
For the asynchronous sequential circuit shown in the figure: Derive the boolean functions for the outputs of two SR latches $Y _1 and Y _2$. Note that the S input of the second latch is $x _1’y _1’$. Derive the transition table and output map of the circuit.
ajaysoni1924
asked
in
Digital Logic
Apr 7, 2019
by
ajaysoni1924
634
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
latch
flip-flop
0
votes
0
answers
48
Morris Mano Edition 3 Exercise 9 Question 8 (Page No. 394)
Convert the circuit of the figure to the asynchronous sequential circuit by removing the clock-pulse(CP) and changes the flip-flops to the SR latches. Derive the transition table and output map of the modified circuit.
ajaysoni1924
asked
in
Digital Logic
Apr 7, 2019
by
ajaysoni1924
252
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
flip-flop
0
votes
0
answers
49
Morris Mano Edition 3 Exercise 9 Question 7 (Page No. 394)
Analyze the T flip-flop shown in the figure. Obtain the transition table and show that the circuit is unstable when both T and CP are equal to 1.
ajaysoni1924
asked
in
Digital Logic
Apr 7, 2019
by
ajaysoni1924
205
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
flip-flop
1
vote
0
answers
50
Morris Mano Edition 3 Exercise 6 Question 22 (Page No. 255)
A sequential circuit has three flip-flops, A, B, C; one input, x; one output, y; The state diagram is shown in the figure. The circuit is to be designed by treating the unused state as don't care conditions. The final circuit ... analyzed to ensure that it is self-correcting. Use D flip-flop in the design. USe JK flip-flops in the design .
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
1.1k
views
digital-logic
morris-mano
sequential-circuit
flip-flop
synchronous-asynchronous-circuits
0
votes
0
answers
51
Morris Mano Edition 3 Exercise 6 Question 21 (Page No. 255)
Design a sequential circuit with two JK flip-flops, A and B and two inputs, E and x. If E = 0 the circuit remains in the same state regardless of the value of x. When E = 1and x = 1, the circuit goes through the transactions from ... = 1 and x = 0 the circuit goes through the transactions from 00 to 11 to 10 to 01 back to 00, and repeats.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
249
views
digital-logic
morris-mano
sequential-circuit
flip-flop
synchronous-asynchronous-circuits
0
votes
0
answers
52
Morris Mano Edition 3 Exercise 6 Question 20 (Page No. 255)
Design a sequential circuit with two D flip-flops A and B and one input, x. When x = 0 the state of the circuit remains the same. When x =1 circuit goes through the state transition from 00 to 01 to 1 to 10 back to 00 and, repeats.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
206
views
digital-logic
morris-mano
sequential-circuit
flip-flop
synchronous-asynchronous-circuits
0
votes
0
answers
53
Morris Mano Edition 3 Exercise 6 Question 19 (Page No. 254)
Convert a D flip-flop to JK flip-flop by including input gates to the D flip-flop. The gates need for the input of the D flip-flop can be determined by means of the sequential circuit design procedure. The sequential circuit to be considered will have one D flip-flop and two inputs, J and K.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
660
views
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
flip-flop
0
votes
0
answers
54
Morris Mano Edition 3 Exercise 6 Question 18 (Page No. 254)
Analyze the circuit in the following figure and show that it is equivalent to T flip-flop.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
697
views
digital-logic
morris-mano
sequential-circuit
flip-flop
synchronous-asynchronous-circuits
0
votes
0
answers
55
Morris Mano Edition 3 Exercise 6 Question 12 (Page No. 254)
A sequential circuit has two JK flip-flop, A and B, two inputs, x and y; and one output, z; The flip-flop input functions and the circuit output function are as follows: $JA= bx + b'y'$ $KA= B'xy'$ ... draw the logic diagram of the circuit. tabulate the state table. Derive the next-state equations for A and B.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
281
views
digital-logic
flip-flop
sequential-circuit
0
votes
0
answers
56
Morris Mano Edition 3 Exercise 6 Question 11 (Page No. 253)
A sequential circuit has two JK flip-flops one input, x, and one output y. The logic diagram of the circuit is shown in the figure. Derive the state table and state diagram. .
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
495
views
digital-logic
sequential-circuit
flip-flop
0
votes
0
answers
57
Morris Mano Edition 3 Exercise 6 Question 10 (Page No. 253)
A JN flip-flop has two inputs J and N, input J behaves like J input of the JK flipflop and input N behaves like the complement of K input of JK flip-flop.(that is N = k') Tabulate the characteristic table of the ... flop. Tabulate the Excitation table of the flip-flop. Show that by connecting two inputs together, one obtains a D flip-flop.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
611
views
digital-logic
morris-mano
sequential-circuit
flip-flop
0
votes
0
answers
58
Morris Mano Edition 3 Exercise 6 Question 9 (Page No. 253)
Derive the state diagram and state table of the sequential circuit shown in the figure. Explain the function that the circuit performs.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
730
views
digital-logic
morris-mano
sequential-circuit
flip-flop
0
votes
0
answers
59
Morris Mano Edition 3 Exercise 6 Question 8 (Page No. 252)
A sequential circuit has one flip-flop, Q; two inputs x and y; and one output, S. It consists of a full adder circuit connected to a D flip-flop as shown in the figure. Derive the state table and state diagram of the circuit.
ajaysoni1924
asked
in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
1.4k
views
digital-logic
morris-mano
flip-flop
sequential-circuit
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