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Recent questions tagged flip-flop
3
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61
Morris Mano Edition 3 Exercise 6 Question 7 (Page No. 252)
A sequential circuit has three D flip-flop, A, B, C and one input x. It is described by the following flip-flop input functions $DA = (B’C + BC’)x + (BC + B’C’)x’$ $DB = A$ $DC = B$ derive a state table for the circuit. Draw two state diagram: one for x = 0 and other for x = 1.
ajaysoni1924
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Digital Logic
Apr 4, 2019
by
ajaysoni1924
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digital-logic
morris-mano
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flip-flop
0
votes
0
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62
Morris Mano Edition 3 Exercise 6 Question 6 (Page No. 252)
A sequential circuit with two D flip-flops, A and B; two input x and y; one output z; it is specified by the following next-state and output equations: $A(t+1) = x’y + xA$ $B(t+1) = x’B + xA$ $Z = B$ Draw the logic diagram of the circuit. Dervie the state table. Drive the state diagram.
ajaysoni1924
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in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
216
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digital-logic
morris-mano
sequential-circuit
flip-flop
0
votes
0
answers
63
Morris Mano Edition 3 Exercise 6 Question 5 (Page No. 252)
The D-type positive edge triggered flip-flop of the figure is modified by including an asynchronous clear input in the circuit. The Asynchronous clear input is connected to the third input in gate 2 and also to the third input in ... that when asynchronous clear input is at logic 1, it has no effect on the normal operation of the circuit.
ajaysoni1924
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in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
464
views
digital-logic
morris-mano
flip-flop
sequential-circuit
0
votes
0
answers
64
Morris Mano Edition 3 Exercise 6 Question 4 (Page No. 252)
Draw the logic diagram of a master-slave D flip-flop. Use NAND gates
ajaysoni1924
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in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
160
views
digital-logic
morris-mano
sequential-circuit
flip-flop
0
votes
0
answers
65
Morris Mano Edition 3 Exercise 6 Question 3 (Page No. 252)
The D FLip-flop can be constructed with the four NAND gates only. This can be done by removing gate number 5 from the circuit and, instead, connecting the output of gate number 3 the input of gate number 4. Draw the Modified circuit and show that it operates in the same way as the original circuit operates .
ajaysoni1924
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in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
521
views
digital-logic
morris-mano
flip-flop
sequential-circuit
1
vote
0
answers
66
Morris Mano Edition 3 Exercise 6 Question 2 (Page No. 251)
Construct the D flip-flop that has the same characteristics as the one shown in the figure, but instead of using NAND gates use NOR gates only.
ajaysoni1924
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Digital Logic
Apr 4, 2019
by
ajaysoni1924
749
views
digital-logic
morris-mano
sequential-circuit
flip-flop
0
votes
0
answers
67
Morris Mano Edition 3 Exercise 6 Question 1 (Page No. 251)
Construct a D flipflop that have the same charactorstics as the one shown in the figure, but instead of using NAND gates use NOR and AND gates only. (Remember that one input NOR gate is equivalent to an inverter.
ajaysoni1924
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in
Digital Logic
Apr 4, 2019
by
ajaysoni1924
634
views
digital-logic
morris-mano
sequential-circuit
flip-flop
0
votes
0
answers
68
Self Doubt
What is control input and control output ? Is in SR output changes with control input and control output?
srestha
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in
Digital Logic
Apr 1, 2019
by
srestha
142
views
digital-logic
flip-flop
0
votes
0
answers
69
flip flop msb lsb
What should be default order of msb lsb in flip flops if msb lsb flip flop not given for a counter
bts1jimin
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in
Digital Logic
Jan 21, 2019
by
bts1jimin
528
views
digital-logic
flip-flop
0
votes
1
answer
70
flip flop : find mod of counter having presets as shown
bts1jimin
asked
in
Digital Logic
Jan 20, 2019
by
bts1jimin
1.1k
views
digital-logic
flip-flop
1
vote
1
answer
71
Applied Course | Mock GATE | Test 1 | Question: 50
To implement D Flip-Flop using JK-Flip flop we need NOT gate $2 \times 1$ mux XOR gate Any of the above
Applied Course
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in
Digital Logic
Jan 16, 2019
by
Applied Course
341
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applied-course-2019-mock1
digital-logic
sequential-circuit
flip-flop
0
votes
0
answers
72
MadeEasy Test Series: Digital Logic - Digital Counter
jatin khachane 1
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in
Digital Logic
Jan 11, 2019
by
jatin khachane 1
439
views
made-easy-test-series
digital-logic
flip-flop
digital-counter
0
votes
1
answer
73
MadeEasy Full Length Test 2019: Digital Logic - Flip Flop
The answer I got is 3 but it’s given as 5 and in the solution they are mentioning that the no. of flip flops here are defined by the sequence not the no. of states??
Sambhrant Maurya
asked
in
Digital Logic
Jan 6, 2019
by
Sambhrant Maurya
340
views
digital-logic
sequential-circuit
flip-flop
made-easy-test-series
2
votes
0
answers
74
Digital Logic made easy
Consider the circuit given below: MSB and LSB of mod 10 ripple counter act as clock to ripple down and up counter respectively. Initially all the counters were cleared and output of comparator was A=B. The clock pulse is applied. Find the minimum no of clock pulses required to make A=B again.
Sambhrant Maurya
asked
in
Digital Logic
Jan 5, 2019
by
Sambhrant Maurya
1.8k
views
digital-logic
ripple-counter-operation
sequential-circuit
flip-flop
1
vote
1
answer
75
GATE 2001 ECE
The digital block in the figure is realized using two positive edge triggered flip flops. Assume that for t<t0, Q1=Q2=0. The correct realization is given by which of the following figures?
Sambhrant Maurya
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in
Digital Logic
Jan 5, 2019
by
Sambhrant Maurya
2.5k
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digital-logic
sequential-circuit
flip-flop
0
votes
2
answers
76
Digital Logic madeeasy
The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 kHz. The frequency of the signal available at Q is? 5 Khz 10 Khz 1 Khz 0.5 Khz
Sambhrant Maurya
asked
in
Digital Logic
Jan 4, 2019
by
Sambhrant Maurya
3.5k
views
digital-logic
flip-flop
sequential-circuit
2
votes
1
answer
77
Digital Logic: GATE 2013 EE
The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is ‘0’, then the frequency of the output waveform Q in kHz is 0.25 0.5 1 2
Sambhrant Maurya
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in
Digital Logic
Jan 4, 2019
by
Sambhrant Maurya
2.8k
views
gate2013-dl-ee
flip-flop
digital-logic
0
votes
0
answers
78
Self Doubt on Counters
If in question it is given to find no. of counting states of a counter, does it mean that we need to find Mod of the counter or just the no. of distinct states that the counter can have?
Subham Nagar
asked
in
Digital Logic
Jan 2, 2019
by
Subham Nagar
135
views
digital-counter
flip-flop
0
votes
0
answers
79
MadeEasy Test Series: Digital Logic - Flip Flop
Magma
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in
Digital Logic
Jan 2, 2019
by
Magma
235
views
made-easy-test-series
flip-flop
digital-logic
1
vote
0
answers
80
MadeEasy Test Series: Digital Logic - Flip Flop
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN and GREEN to RED. In each cycle RED is turned for 100 seconds, YELLOW is turned for 40 seconds and GREEN is turned for 80 seconds. The traffic has to be implemented using FSM. The only input to ... >0 >1 → ..->7 3 different states → no of flip flops required = 2 4+ 2 = 6 FF required
Magma
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in
Digital Logic
Jan 2, 2019
by
Magma
796
views
made-easy-test-series
flip-flop
digital-logic
0
votes
0
answers
81
MadeEasy Workbook: Digital Logic - Flip Flop
Solve this
Jyoti Kumari97
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in
Digital Logic
Dec 30, 2018
by
Jyoti Kumari97
239
views
digital-logic
made-easy-booklet
flip-flop
1
vote
0
answers
82
Made Easy Test Series: Digital Logic - Flip Flop
Consider a pulse triggered master slave JK flip-flop with inputs J and K as shown below: The input to the LED is connected to the output $\overline Q$ of the master slave flip-flop. The duration for which the LED will be ON in the time duration of T is ________ sec.
Gupta731
asked
in
Digital Logic
Dec 27, 2018
by
Gupta731
672
views
made-easy-test-series
digital-logic
flip-flop
0
votes
0
answers
83
MadeEasy Subject Test 2019: Digital Logic - Flip Flop
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN and GREEN to RED. In each cycle RED is turned for 100 seconds, YELLOW is turned for 40 seconds and GREEN is turned for 80 seconds. The traffic has to be implemented using ... to this FSM is a clock of 10 second period. The minimum number of flip-flops required to implement this FSM is?
Parth Shah
asked
in
Digital Logic
Dec 22, 2018
by
Parth Shah
1.0k
views
made-easy-test-series
digital-logic
flip-flop
1
vote
0
answers
84
Gateforum Test Series: Digital Logic - Flip Flop
Gupta731
asked
in
Digital Logic
Dec 20, 2018
by
Gupta731
341
views
gateforum-test-series
digital-logic
flip-flop
0
votes
0
answers
85
MadeEasy Subject Test 2019: Digital Logic - Flip Flop
The input to the LED is connected to the output $\overline{Q}$ of the master slave flip-flop. The duration for which the LED will be ON in the time duration of T is _____ sec.
Mk Utkarsh
asked
in
Digital Logic
Dec 14, 2018
by
Mk Utkarsh
587
views
made-easy-test-series
digital-logic
flip-flop
0
votes
1
answer
86
MadeEasy Test Series: Digital Logic - Flip Flop
suneetha
asked
in
Digital Logic
Dec 5, 2018
by
suneetha
319
views
made-easy-test-series
digital-logic
flip-flop
0
votes
0
answers
87
Minimum number of Flip Flops required
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN, GREEN to RED. In each cycle RED is turned on for 100 seconds,YELLOW is turned on for 40 seconds and GREEN is turned on for 80 seconds. The traffic signal has to be implemented ... only input to FSM is clock of 10 seconds period.The minimum number of Flip Flops required to implement this FSM is .
Na462
asked
in
Digital Logic
Dec 2, 2018
by
Na462
1.1k
views
flip-flop
digital-logic
digital-counter
0
votes
2
answers
88
GATE-ECE-2017
answer is D but I'm getting A. pls tell where am I going wrong?
aditi19
asked
in
Digital Logic
Nov 20, 2018
by
aditi19
427
views
digital-logic
sequential-circuit
flip-flop
digital-counter
finite-automata
0
votes
2
answers
89
Flip Flop Conversion
A new two input Flip Flop is designed as shown. Table shows the characteristic table of AB flip flop.The Combination Logic is :- A. B. C. D.
Na462
asked
in
Digital Logic
Oct 10, 2018
by
Na462
1.1k
views
digital-logic
flip-flop
digital-circuits
0
votes
0
answers
90
Digital electronics
why does in sr latch with NOR gate r is taken with Q and s is taken with Q' and with NAND gate the reverse is taken i.e changing the position of Q and Q'
kd.....
asked
in
Digital Logic
Sep 30, 2018
by
kd.....
103
views
digital-logic
flip-flop
latch
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