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Recent questions tagged flip-flop
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91
Morris Mano Edition 3 Exercise 6 Question 5 (Page No. 252)
The D-type positive edge triggered flip-flop of the figure is modified by including an asynchronous clear input in the circuit. The Asynchronous clear input is connected to the third input in gate 2 and also to the third input in ... that when asynchronous clear input is at logic 1, it has no effect on the normal operation of the circuit.
The D-type positive edge triggered flip-flop of the figure is modified by including an asynchronous clear input in the circuit. The Asynchronous clear input is connected...
ajaysoni1924
835
views
ajaysoni1924
asked
Apr 4, 2019
Digital Logic
digital-logic
morris-mano
flip-flop
sequential-circuit
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0
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0
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92
Morris Mano Edition 3 Exercise 6 Question 4 (Page No. 252)
Draw the logic diagram of a master-slave D flip-flop. Use NAND gates
Draw the logic diagram of a master-slave D flip-flop. Use NAND gates
ajaysoni1924
243
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ajaysoni1924
asked
Apr 4, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
flip-flop
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1
votes
0
answers
93
Morris Mano Edition 3 Exercise 6 Question 3 (Page No. 252)
The D FLip-flop can be constructed with the four NAND gates only. This can be done by removing gate number 5 from the circuit and, instead, connecting the output of gate number 3 the input of gate number 4. Draw the Modified circuit and show that it operates in the same way as the original circuit operates .
The D FLip-flop can be constructed with the four NAND gates only. This can be done by removing gate number 5 from the circuit and, instead, connecting the output of gate ...
ajaysoni1924
794
views
ajaysoni1924
asked
Apr 4, 2019
Digital Logic
digital-logic
morris-mano
flip-flop
sequential-circuit
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2
votes
0
answers
94
Morris Mano Edition 3 Exercise 6 Question 2 (Page No. 251)
Construct the D flip-flop that has the same characteristics as the one shown in the figure, but instead of using NAND gates use NOR gates only.
Construct the D flip-flop that has the same characteristics as the one shown in the figure, but instead of using NAND gates use NOR gates only.
ajaysoni1924
1.1k
views
ajaysoni1924
asked
Apr 4, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
flip-flop
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0
votes
0
answers
95
Morris Mano Edition 3 Exercise 6 Question 1 (Page No. 251)
Construct a D flipflop that have the same charactorstics as the one shown in the figure, but instead of using NAND gates use NOR and AND gates only. (Remember that one input NOR gate is equivalent to an inverter.
Construct a D flipflop that have the same charactorstics as the one shown in the figure, but instead of using NAND gates use NOR and AND gates only. (Remember that one i...
ajaysoni1924
975
views
ajaysoni1924
asked
Apr 4, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
flip-flop
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0
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0
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96
Self Doubt
What is control input and control output ? Is in SR output changes with control input and control output?
What is control input and control output ?Is in SR output changes with control input and control output?
srestha
330
views
srestha
asked
Apr 1, 2019
Digital Logic
digital-logic
flip-flop
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0
votes
0
answers
97
flip flop msb lsb
What should be default order of msb lsb in flip flops if msb lsb flip flop not given for a counter
What should be default order of msb lsb in flip flops if msb lsb flip flop not given for a counter
bts1jimin
705
views
bts1jimin
asked
Jan 21, 2019
Digital Logic
digital-logic
flip-flop
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0
votes
1
answer
98
flip flop : find mod of counter having presets as shown
bts1jimin
1.6k
views
bts1jimin
asked
Jan 20, 2019
Digital Logic
digital-logic
flip-flop
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1
votes
1
answer
99
Applied Course | Mock GATE | Test 1 | Question: 50
To implement D Flip-Flop using JK-Flip flop we need NOT gate $2 \times 1$ mux XOR gate Any of the above
To implement D Flip-Flop using JK-Flip flop we needNOT gate$2 \times 1$ muxXOR gateAny of the above
Applied Course
475
views
Applied Course
asked
Jan 16, 2019
Digital Logic
applied-course-2019-mock1
digital-logic
sequential-circuit
flip-flop
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0
votes
0
answers
100
MadeEasy Test Series: Digital Logic - Digital Counter
jatin khachane 1
740
views
jatin khachane 1
asked
Jan 11, 2019
Digital Logic
made-easy-test-series
digital-logic
flip-flop
digital-counter
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0
votes
1
answer
101
MadeEasy Full Length Test 2019: Digital Logic - Flip Flop
The answer I got is 3 but it’s given as 5 and in the solution they are mentioning that the no. of flip flops here are defined by the sequence not the no. of states??
The answer I got is 3 but it’s given as 5 and in the solution they are mentioning that the no. of flip flops here are defined by the sequence not the no. of states??
Sambhrant Maurya
451
views
Sambhrant Maurya
asked
Jan 6, 2019
Digital Logic
digital-logic
sequential-circuit
flip-flop
made-easy-test-series
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2
votes
0
answers
102
Digital Logic made easy
Consider the circuit given below: MSB and LSB of mod 10 ripple counter act as clock to ripple down and up counter respectively. Initially all the counters were cleared and output of comparator was A=B. The clock pulse is applied. Find the minimum no of clock pulses required to make A=B again.
Consider the circuit given below:MSB and LSB of mod 10 ripple counter act as clock to ripple down and up counter respectively. Initially all the counters were cleared and...
Sambhrant Maurya
2.6k
views
Sambhrant Maurya
asked
Jan 5, 2019
Digital Logic
digital-logic
ripple-counter-operation
sequential-circuit
flip-flop
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1
votes
1
answer
103
GATE 2001 ECE
The digital block in the figure is realized using two positive edge triggered flip flops. Assume that for t<t0, Q1=Q2=0. The correct realization is given by which of the following figures?
The digital block in the figure is realized using two positive edge triggered flip flops. Assume that for t<t0, Q1=Q2=0.The correct realization is given by which of the f...
Sambhrant Maurya
3.5k
views
Sambhrant Maurya
asked
Jan 5, 2019
Digital Logic
digital-logic
sequential-circuit
flip-flop
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1
votes
2
answers
104
Digital Logic madeeasy
The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 kHz. The frequency of the signal available at Q is? 5 Khz 10 Khz 1 Khz 0.5 Khz
The frequency of the clock signal applied to the rising edge triggered D flip-flop shown in figure is 10 kHz. The frequency of the signal available at Q is? 5 Khz10 Khz1 ...
Sambhrant Maurya
4.4k
views
Sambhrant Maurya
asked
Jan 4, 2019
Digital Logic
digital-logic
flip-flop
sequential-circuit
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2
votes
1
answer
105
Digital Logic: GATE 2013 EE
The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is ‘0’, then the frequency of the output waveform Q in kHz is 0.25 0.5 1 2
The clock frequency applied to the digital circuit shown in the figure below is 1 kHz. If the initial state of the output Q of the flip-flop is ‘0’, then the frequenc...
Sambhrant Maurya
3.8k
views
Sambhrant Maurya
asked
Jan 4, 2019
Digital Logic
gate2013-dl-ee
flip-flop
digital-logic
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0
votes
0
answers
106
Self Doubt on Counters
If in question it is given to find no. of counting states of a counter, does it mean that we need to find Mod of the counter or just the no. of distinct states that the counter can have?
If in question it is given to find no. of counting states of a counter, does it mean that we need to find Mod of the counter or just the no. of distinct states that the c...
Subham Nagar
193
views
Subham Nagar
asked
Jan 2, 2019
Digital Logic
digital-counter
flip-flop
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0
votes
0
answers
107
MadeEasy Test Series: Digital Logic - Flip Flop
Magma
347
views
Magma
asked
Jan 2, 2019
Digital Logic
made-easy-test-series
flip-flop
digital-logic
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1
votes
0
answers
108
MadeEasy Test Series: Digital Logic - Flip Flop
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN and GREEN to RED. In each cycle RED is turned for 100 seconds, YELLOW is turned for 40 seconds and GREEN is turned for 80 seconds. The traffic has to be implemented using FSM. The only input to ... >0 >1 → ..->7 3 different states → no of flip flops required = 2 4+ 2 = 6 FF required
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN and GREEN to RED. In each cycle RED is turned for 100 seconds, YELLOW is turned for 40 seconds and GREEN is tu...
Magma
1.4k
views
Magma
asked
Jan 2, 2019
Digital Logic
made-easy-test-series
flip-flop
digital-logic
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0
votes
0
answers
109
MadeEasy Workbook: Digital Logic - Flip Flop
Solve this
Solve this
Jyoti Kumari97
317
views
Jyoti Kumari97
asked
Dec 30, 2018
Digital Logic
digital-logic
made-easy-booklet
flip-flop
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1
votes
0
answers
110
Made Easy Test Series: Digital Logic - Flip Flop
Consider a pulse triggered master slave JK flip-flop with inputs J and K as shown below: The input to the LED is connected to the output $\overline Q$ of the master slave flip-flop. The duration for which the LED will be ON in the time duration of T is ________ sec.
Consider a pulse triggered master slave JK flip-flop with inputs J and K as shown below:The input to the LED is connected to the output $\overline Q$ of the master slave ...
Gupta731
941
views
Gupta731
asked
Dec 27, 2018
Digital Logic
made-easy-test-series
digital-logic
flip-flop
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0
votes
0
answers
111
MadeEasy Subject Test 2019: Digital Logic - Flip Flop
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN and GREEN to RED. In each cycle RED is turned for 100 seconds, YELLOW is turned for 40 seconds and GREEN is turned for 80 seconds. The traffic has to be implemented using ... to this FSM is a clock of 10 second period. The minimum number of flip-flops required to implement this FSM is?
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN and GREEN to RED. In each cycle RED is turned for 100 seconds, YELLOW is turned for 40 seconds and GREEN is tu...
Parth Shah
1.3k
views
Parth Shah
asked
Dec 21, 2018
Digital Logic
made-easy-test-series
digital-logic
flip-flop
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1
votes
0
answers
112
Gateforum Test Series: Digital Logic - Flip Flop
Gupta731
473
views
Gupta731
asked
Dec 20, 2018
Digital Logic
gateforum-test-series
digital-logic
flip-flop
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0
votes
0
answers
113
MadeEasy Subject Test 2019: Digital Logic - Flip Flop
The input to the LED is connected to the output $\overline{Q}$ of the master slave flip-flop. The duration for which the LED will be ON in the time duration of T is _____ sec.
The input to the LED is connected to the output $\overline{Q}$ of the master slave flip-flop. The duration for which the LED will be ON in the time duration of T is _____...
Mk Utkarsh
814
views
Mk Utkarsh
asked
Dec 14, 2018
Digital Logic
made-easy-test-series
digital-logic
flip-flop
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0
votes
1
answer
114
MadeEasy Test Series: Digital Logic - Flip Flop
suneetha
461
views
suneetha
asked
Dec 5, 2018
Digital Logic
made-easy-test-series
digital-logic
flip-flop
+
–
0
votes
0
answers
115
Minimum number of Flip Flops required
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN, GREEN to RED. In each cycle RED is turned on for 100 seconds,YELLOW is turned on for 40 seconds and GREEN is turned on for 80 seconds. The traffic signal has to be implemented ... only input to FSM is clock of 10 seconds period.The minimum number of Flip Flops required to implement this FSM is .
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN, GREEN to RED. In each cycle RED is turned on for 100 seconds,YELLOW is turned on for 40 seconds and GREEN is ...
Na462
1.5k
views
Na462
asked
Dec 2, 2018
Digital Logic
flip-flop
digital-logic
digital-counter
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–
0
votes
2
answers
116
GATE-ECE-2017
answer is D but I'm getting A. pls tell where am I going wrong?
answer is D but I'm getting A. pls tell where am I going wrong?
aditi19
621
views
aditi19
asked
Nov 20, 2018
Digital Logic
digital-logic
sequential-circuit
flip-flop
digital-counter
finite-automata
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0
votes
2
answers
117
Flip Flop Conversion
A new two input Flip Flop is designed as shown. Table shows the characteristic table of AB flip flop.The Combination Logic is :- A. B. C. D.
A new two input Flip Flop is designed as shown. Table shows the characteristic table of AB flip flop.The Combination Logic is :- A. B. C. D.
Na462
2.1k
views
Na462
asked
Oct 10, 2018
Digital Logic
digital-logic
flip-flop
digital-circuits
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–
0
votes
0
answers
118
Digital electronics
why does in sr latch with NOR gate r is taken with Q and s is taken with Q' and with NAND gate the reverse is taken i.e changing the position of Q and Q'
why does in sr latch with NOR gate r is taken with Q and s is taken with Q' and with NAND gate the reverse is taken i.e changing the position of Q and Q'
kd.....
225
views
kd.....
asked
Sep 30, 2018
Digital Logic
digital-logic
flip-flop
latch
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–
0
votes
0
answers
119
Minimum number of flip-flops needed
minimal number of d flip-flops required for first seven Fibonacci numbers ...? how to solve these types of questions please elaborate like this type of questions https://gateoverflow.in/246867/me-test-series
minimal number of d flip-flops required for first seven Fibonacci numbers ...?how to solve these types of questions please elaborate like this type of questionshttps://ga...
Dharmendra Lodhi
2.2k
views
Dharmendra Lodhi
asked
Sep 27, 2018
Digital Logic
digital-counter
flip-flop
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–
0
votes
1
answer
120
No of flip flops required
If there are total 21 different states in a system and there is one external input, then how many flip flops are required in case of : ripple counter ring counter johnson counter
If there are total 21 different states in a system and there is one external input, then how many flip flops are required in case of :ripple counterring counterjohnson co...
Balaji Jegan
554
views
Balaji Jegan
asked
Sep 16, 2018
Digital Logic
self-doubt
flip-flop
+
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