menu
search
Log In

GO Book for GATECSE 2022

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true

Subjects


GATE Overflow
Recent questions tagged gate1991

Network Sites

 GO Mechanical
 GO Electrical
 GO Electronics
 GO Civil
 CSE Doubts

Recent questions tagged gate1991

1 vote
2 answers
1
CO & architecture
The arithmetic expression : (a + b) * c - d / e * * f is to be evaluated on a two-address machine, where each operands, the number of registers required to evaluate this expression is ______. The number of memory access of operand is __________.
The arithmetic expression : (a + b) * c - d / e * * f is to be evaluated on a two-address machine, where each operands, the number of registers required to evaluate this expression is ______. The number of memory access of operand is __________.
asked Nov 26, 2018 in CO and Architecture Satbir 600 views
7 votes
3 answers
2
gate1991
Indicate all the true statements from the following: (a) A programming language not supporting either recursion or pointer type does not need the support of dynamic memory allocation. (b) Although C does not support call by name parameter passing, the effect can be correctly simulated in C.
Indicate all the true statements from the following: (a) A programming language not supporting either recursion or pointer type does not need the support of dynamic memory allocation. (b) Although C does not support call by name parameter passing, the effect can be correctly simulated in C.
asked Apr 8, 2018 in Programming Vishal Rana 2.1k views
0 votes
0 answers
3
GATE1991-07b
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. Assume that the lower ... $8$ bits of an instruction constitute the operand field. Draw the logic schematic of the hardwired controller including the data path.
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. Assume that the lower order $8$ bits of an instruction constitute the operand field. Draw the logic schematic of the hardwired controller including the data path.
asked Apr 24, 2016 in CO and Architecture jothee 438 views
16 votes
1 answer
4
GATE1991-10c
Consider the following grammar for arithmetic expressions using binary operators $-$ and $/$ which are not associative $E \rightarrow E -T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) Does the ... to the given production rules and adding at most one more production rule. Convert the grammar obtained above into one that is not left recursive.
Consider the following grammar for arithmetic expressions using binary operators $-$ and $/$ which are not associative $E \rightarrow E -T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) Does the grammar ... to the given production rules and adding at most one more production rule. Convert the grammar obtained above into one that is not left recursive.
asked Apr 24, 2016 in Compiler Design jothee 1.4k views
12 votes
2 answers
5
GATE1991-10b
Consider the following grammar for arithmetic expressions using binary operators $-$ and $/$ which are not associative $E \rightarrow E -T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) ... expressions with redundant parentheses. Do this with minimum number of changes to the given production rules and adding at most one more production rule.
Consider the following grammar for arithmetic expressions using binary operators $-$ and $/$ which are not associative $E \rightarrow E -T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) Does ... generate expressions with redundant parentheses. Do this with minimum number of changes to the given production rules and adding at most one more production rule.
asked Apr 24, 2016 in Compiler Design jothee 1.9k views
19 votes
2 answers
6
GATE1991-09b
For the following code, indicate the output if static scope rules dynamic scope rules are used var a,b : integer; procedure P; a := 5; b := 10; end {P}; procedure Q; var a, b : integer; P; end {Q}; begin a := 1; b := 2; Q; Write ('a = ', a, 'b = ', b); end
For the following code, indicate the output if static scope rules dynamic scope rules are used var a,b : integer; procedure P; a := 5; b := 10; end {P}; procedure Q; var a, b : integer; P; end {Q}; begin a := 1; b := 2; Q; Write ('a = ', a, 'b = ', b); end
asked Apr 24, 2016 in Compiler Design jothee 2.3k views
23 votes
1 answer
7
GATE1991-14,c
Consider the binary tree in the figure below: Outline a procedure in Pseudo-code to delete an arbitrary node from such a binary tree with $n$ nodes that preserves the structures. What is the worst-case-time-complexity of your procedure?
Consider the binary tree in the figure below: Outline a procedure in Pseudo-code to delete an arbitrary node from such a binary tree with $n$ nodes that preserves the structures. What is the worst-case-time-complexity of your procedure?
asked Apr 18, 2016 in DS jothee 1.4k views
14 votes
2 answers
8
GATE1991-14,b
Consider the binary tree in the figure below: Give different steps for deleting the node with key $5$ so that the structure is preserved.
Consider the binary tree in the figure below: Give different steps for deleting the node with key $5$ so that the structure is preserved.
asked Apr 18, 2016 in DS jothee 1.5k views
6 votes
2 answers
9
GATE1991-11,b
Consider the following scheme for implementing a critical section in a situation with three processes $P_i, P_j$ and $P_k$. Pi; repeat flag[i] := true; while flag [j] or flag[k] do case turn of j: if flag [j] then begin flag [i] := ... a situation in which a waiting process can never enter the critical section? If so, explain and suggest modifications to the code to solve this problem
Consider the following scheme for implementing a critical section in a situation with three processes $P_i, P_j$ and $P_k$. Pi; repeat flag[i] := true; while flag [j] or flag[k] do case turn of j: if flag [j] then begin flag [i] := false; ... there a situation in which a waiting process can never enter the critical section? If so, explain and suggest modifications to the code to solve this problem
asked Apr 18, 2016 in Operating System jothee 894 views
5 votes
2 answers
10
GATE1991-12,b
Suppose a database consist of the following relations: SUPPLIER (SCODE,SNAME,CITY). PART (PCODE,PNAME,PDESC,CITY). PROJECTS (PRCODE,PRNAME,PRCITY). SPPR (SCODE,PCODE,PRCODE,QTY). Write algebraic solution to the following : Get SCODE values for suppliers who supply to both projects PR1 and PR2. Get PRCODE values for projects supplied by at least one supplier not in the same city.
Suppose a database consist of the following relations: SUPPLIER (SCODE,SNAME,CITY). PART (PCODE,PNAME,PDESC,CITY). PROJECTS (PRCODE,PRNAME,PRCITY). SPPR (SCODE,PCODE,PRCODE,QTY). Write algebraic solution to the following : Get SCODE values for suppliers who supply to both projects PR1 and PR2. Get PRCODE values for projects supplied by at least one supplier not in the same city.
asked Apr 18, 2016 in Databases jothee 1k views
29 votes
4 answers
11
GATE1991-15,b
Consider the following first order formula: ... Does it have finite models? Is it satisfiable? If so, give a countable model for it.
Consider the following first order formula: ... Does it have finite models? Is it satisfiable? If so, give a countable model for it.
asked Nov 16, 2015 in Mathematical Logic ibia 3k views
16 votes
5 answers
12
GATE1991-17,a
Show that the Turing machines, which have a read only input tape and constant size work tape, recognize precisely the class of regular languages.
Show that the Turing machines, which have a read only input tape and constant size work tape, recognize precisely the class of regular languages.
asked Nov 15, 2015 in Theory of Computation Arjun 2.9k views
36 votes
3 answers
13
GATE1991-16-b
Show that all vertices in an undirected finite graph cannot have distinct degrees, if the graph has at least two vertices.
Show that all vertices in an undirected finite graph cannot have distinct degrees, if the graph has at least two vertices.
asked Nov 15, 2015 in Graph Theory Arjun 2.2k views
5 votes
0 answers
14
GATE1991-6,b
Design a 1024 bit serial-in/serial-out unidirectional shift register using a 1K $\times$ 1 bit RAM with a data input $D_{in}$, data output $D_{out}$ and control input $\text{READ}/\overline{\text{WRITE}}$. You may assume the availability of standard SSI and MSI components such as gates, registers and counters.
Design a 1024 bit serial-in/serial-out unidirectional shift register using a 1K $\times$ 1 bit RAM with a data input $D_{in}$, data output $D_{out}$ and control input $\text{READ}/\overline{\text{WRITE}}$. You may assume the availability of standard SSI and MSI components such as gates, registers and counters.
asked Nov 14, 2015 in Digital Logic ibia 409 views
49 votes
4 answers
15
GATE1991-5-c
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10$ $\text{ns}$. Also assume that the setup time for the $JK$ inputs of the flip flops is negligible.
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10$ $\text{ns}$. Also assume that the setup time for the $JK$ inputs of the flip flops is negligible.
asked Nov 14, 2015 in Digital Logic ibia 10.2k views
16 votes
2 answers
16
GATE1991-5-b
Find the minimum sum of products form of the logic function $ f(A,B,C,D) = \Sigma m(0,2,8,10,15)+ \Sigma d(3,11,12,14)$ where $m$ and $d$ represent minterm and don't care term respectively.
Find the minimum sum of products form of the logic function $ f(A,B,C,D) = \Sigma m(0,2,8,10,15)+ \Sigma d(3,11,12,14)$ where $m$ and $d$ represent minterm and don't care term respectively.
asked Nov 14, 2015 in Digital Logic ibia 1.4k views
4 votes
2 answers
17
GATE1991-01,xi
The arithmetic expression $(a+b) * c- d/e ** l$ is to be evaluated on a two address machine, where each operand is either a register or a memory location. With a minimum number of memory accesses of operands.the number of registers required to evaluate this expression is ______. The number of memory accesses of operands is ____________
The arithmetic expression $(a+b) * c- d/e ** l$ is to be evaluated on a two address machine, where each operand is either a register or a memory location. With a minimum number of memory accesses of operands.the number of registers required to evaluate this expression is ______. The number of memory accesses of operands is ____________
asked Nov 14, 2015 in Compiler Design ibia 805 views
33 votes
8 answers
18
GATE1991-17,b
Let $L$ be the language of all binary strings in which the third symbol from the right is a $1$. Give a non-deterministic finite automaton that recognizes $L$. How many states does the minimized equivalent deterministic finite automaton have? Justify your answer briefly?
Let $L$ be the language of all binary strings in which the third symbol from the right is a $1$. Give a non-deterministic finite automaton that recognizes $L$. How many states does the minimized equivalent deterministic finite automaton have? Justify your answer briefly?
asked Sep 13, 2014 in Theory of Computation Kathleen 5.4k views
43 votes
2 answers
19
GATE1991-16,a
Find the number of binary strings $w$ of length $2n$ with an equal number of $1's$ and $0's$ and the property that every prefix of $w$ has at least as many $0's$ as $1's.$
Find the number of binary strings $w$ of length $2n$ with an equal number of $1's$ and $0's$ and the property that every prefix of $w$ has at least as many $0's$ as $1's.$
asked Sep 13, 2014 in Combinatory Kathleen 3.2k views
13 votes
5 answers
20
GATE1991-15,a
Show that the product of the least common multiple and the greatest common divisor of two positive integers $a$ and $b$ is $a\times b$.
Show that the product of the least common multiple and the greatest common divisor of two positive integers $a$ and $b$ is $a\times b$.
asked Sep 13, 2014 in Set Theory & Algebra Kathleen 936 views
20 votes
4 answers
21
GATE1991-14,a
Consider the binary tree in the figure below: (a). What structure is represented by the binary tree?
Consider the binary tree in the figure below: (a). What structure is represented by the binary tree?
asked Sep 13, 2014 in DS Kathleen 2.2k views
18 votes
5 answers
22
GATE1991-13
Give an optimal algorithm in pseudo-code for sorting a sequence of $n$ numbers which has only $k$ distinct numbers ($k$ is not known a Priori). Give a brief analysis for the time-complexity of your algorithm.
Give an optimal algorithm in pseudo-code for sorting a sequence of $n$ numbers which has only $k$ distinct numbers ($k$ is not known a Priori). Give a brief analysis for the time-complexity of your algorithm.
asked Sep 13, 2014 in Algorithms Kathleen 3.1k views
21 votes
6 answers
23
GATE1991-12-a
Suppose a database consist of the following relations: SUPPLIER (SCODE,SNAME,CITY). PART (PCODE,PNAME,PDESC,CITY). PROJECTS (PRCODE,PRNAME,PRCITY). SPPR (SCODE,PCODE,PRCODE,QTY). Write SQL programs corresponding to the following queries: Print PCODE values for parts supplied ... part to a project in the second city, but do not print the triples in which the two CITY values are same.
Suppose a database consist of the following relations: SUPPLIER (SCODE,SNAME,CITY). PART (PCODE,PNAME,PDESC,CITY). PROJECTS (PRCODE,PRNAME,PRCITY). SPPR (SCODE,PCODE,PRCODE,QTY). Write SQL programs corresponding to the following queries: Print PCODE values for parts supplied to ... specified part to a project in the second city, but do not print the triples in which the two CITY values are same.
asked Sep 13, 2014 in Databases Kathleen 1.7k views
5 votes
2 answers
24
GATE1991-11,a
Consider the following scheme for implementing a critical section in a situation with three processes $P_i, P_j$ and $P_k$. Pi; repeat flag[i] := true; while flag [j] or flag[k] do case turn of j: if flag [j] then begin flag [i] := false; ... turn := j; flag [i] := false non-critical section until false; Does the scheme ensure mutual exclusion in the critical section? Briefly explain.
Consider the following scheme for implementing a critical section in a situation with three processes $P_i, P_j$ and $P_k$. Pi; repeat flag[i] := true; while flag [j] or flag[k] do case turn of j: if flag [j] then begin flag [i] := false; while turn ... turn := j; flag [i] := false non-critical section until false; Does the scheme ensure mutual exclusion in the critical section? Briefly explain.
asked Sep 13, 2014 in Operating System Kathleen 1.7k views
16 votes
2 answers
25
GATE1991-10a
Consider the following grammar for arithmetic expressions using binary operators $-$ and $/$ which are not associative $E \rightarrow E -T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) Is the grammar unambiguous? Is so, what is the relative precedence between $-$ and $/$? If not, give an unambiguous grammar that gives $/$ precedence over $-$.
Consider the following grammar for arithmetic expressions using binary operators $-$ and $/$ which are not associative $E \rightarrow E -T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) Is the grammar unambiguous? Is so, what is the relative precedence between $-$ and $/$? If not, give an unambiguous grammar that gives $/$ precedence over $-$.
asked Sep 13, 2014 in Compiler Design Kathleen 2.3k views
22 votes
3 answers
26
GATE1991-09a
Consider the following pseudo-code (all data items are of type integer): procedure P(a, b, c); a := 2; c := a + b; end {P} begin x := 1; y := 5; z := 100; P(x, x*y, z); Write ('x = ', x, 'z = ', z); end Determine its output, if the parameters are passed to the Procedure P by value reference name
Consider the following pseudo-code (all data items are of type integer): procedure P(a, b, c); a := 2; c := a + b; end {P} begin x := 1; y := 5; z := 100; P(x, x*y, z); Write ('x = ', x, 'z = ', z); end Determine its output, if the parameters are passed to the Procedure P by value reference name
asked Sep 13, 2014 in Compiler Design Kathleen 1.9k views
1 vote
0 answers
28
GATE1991-07a
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. Assume that the ... bits of an instruction constitute the operand field. Give the register transfer sequence for realizing the above instruction fetch cycle.
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instruction-length. The effective address of an indexed instruction should be derived in the fetch cycle itself. Assume that the lower order $8$ bits of an instruction constitute the operand field. Give the register transfer sequence for realizing the above instruction fetch cycle.
asked Sep 13, 2014 in CO and Architecture Kathleen 397 views
3 votes
2 answers
29
GATE1991-06,a
Using D flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines: Clock $\text{CLK}$ Three parallel data inputs $A, B, C$ Serial input $S$ Control input $\text{load} / \overline{\text{SHIFT}}$.
Using D flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines: Clock $\text{CLK}$ Three parallel data inputs $A, B, C$ Serial input $S$ Control input $\text{load} / \overline{\text{SHIFT}}$.
asked Sep 13, 2014 in Digital Logic Kathleen 512 views
22 votes
1 answer
30
GATE1991-5-a
Analyse the circuit in Fig below and complete the following table ${\begin{array}{|c|c|c|}\hline \textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline 0&0\\\ 0&1 \\ 1&0 \\ 1&1 \\ \hline \end{array}}$
Analyse the circuit in Fig below and complete the following table ${\begin{array}{|c|c|c|}\hline \textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline 0&0\\\ 0&1 \\ 1&0 \\ 1&1 \\ \hline \end{array}}$
asked Sep 13, 2014 in Digital Logic Kathleen 2.3k views
Page:
Dark theme
Muffin by Hélio Chun
Thanks to Q2A
...