The Gateway to Computer Science Excellence
For all GATE CSE Questions
Toggle navigation
Facebook Login
or
Email or Username
Password
Remember
Login
Register

I forgot my password
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
Prev
Blogs
New Blog
Exams
First time here? Checkout the
FAQ
!
x
×
Close
Use the google search bar on side panel. It searches through all previous GATE/other questions. For hardcopy of previous year questions please see
here
Recent questions tagged gate1991
+5
votes
3
answers
1
gate1991
Indicate all the true statements from the following: (a) A programming language not supporting either recursion or pointer type does not need the support of dynamic memory allocation. (b) Although C does not support call by name parameter passing, the effect can be correctly simulated in C.
asked
Apr 8, 2018
in
Programming
by
Vishal Rana
Junior
(
601
points)

804
views
gate1991
programminginc
0
votes
0
answers
2
GATE199107b
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instructionlength. The effective address of an indexed instruction should be derived in the fetch cycle itself. Assume that the lower ... $8$ bits of an instruction constitute the operand field. Draw the logic schematic of the hardwired controller including the data path.
asked
Apr 24, 2016
in
CO and Architecture
by
jothee
Veteran
(
99.6k
points)

343
views
gate1991
coandarchitecture
controlunit
hardwiredcontroller
normal
unsolved
+11
votes
1
answer
3
GATE199110c
Consider the following grammar for arithmetic expressions using binary operators $$ and $/$ which are not associative $E \rightarrow E T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) Does the ... to the given production rules and adding at most one more production rule. Convert the grammar obtained above into one that is not left recursive.
asked
Apr 24, 2016
in
Compiler Design
by
jothee
Veteran
(
99.6k
points)

726
views
gate1991
grammar
compilerdesign
normal
descriptive
+9
votes
2
answers
4
GATE199110b
Consider the following grammar for arithmetic expressions using binary operators $$ and $/$ which are not associative $E \rightarrow E T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) ... expressions with redundant parentheses. Do this with minimum number of changes to the given production rules and adding at most one more production rule.
asked
Apr 24, 2016
in
Compiler Design
by
jothee
Veteran
(
99.6k
points)

971
views
gate1991
grammar
compilerdesign
normal
descriptive
+14
votes
2
answers
5
GATE199109b
For the following code, indicate the output if static scope rules dynamic scope rules are used var a,b : integer; procedure P; a := 5; b := 10; end {P}; procedure Q; var a, b : integer; P; end {Q}; begin a := 1; b := 2; Q; Write ('a = ', a, 'b = ', b); end
asked
Apr 24, 2016
in
Compiler Design
by
jothee
Veteran
(
99.6k
points)

1.1k
views
gate1991
runtimeenvironments
normal
compilerdesign
parameterpassing
+20
votes
1
answer
6
GATE199114,c
Consider the binary tree in the figure below: Outline a procedure in Pseudocode to delete an arbitrary node from such a binary tree with $n$ nodes that preserves the structures. What is the worstcasetimecomplexity of your procedure?
asked
Apr 18, 2016
in
DS
by
jothee
Veteran
(
99.6k
points)

742
views
gate1991
normal
datastructure
binarytree
timecomplexity
+12
votes
2
answers
7
GATE199114,b
Consider the binary tree in the figure below: Give different steps for deleting the node with key $5$ so that the structure is preserved.
asked
Apr 18, 2016
in
DS
by
jothee
Veteran
(
99.6k
points)

666
views
gate1991
datastructure
binarytree
normal
+1
vote
1
answer
8
GATE199111,b
Consider the following scheme for implementing a critical section in a situation with three processes $P_i, P_j$ and $P_k$. Pi; repeat flag[i] := true; while flag [j] or flag[k] do case turn of j: if flag [j] then begin flag [i] := ... a situation in which a waiting process can never enter the critical section? If so, explain and suggest modifications to the code to solve this problem
asked
Apr 18, 2016
in
Operating System
by
jothee
Veteran
(
99.6k
points)

430
views
gate1991
processsynchronization
normal
operatingsystem
+2
votes
1
answer
9
GATE199112,b
Suppose a database consist of the following relations: SUPPLIER (SCODE,SNAME,CITY). PART (PCODE,PNAME,PDESC,CITY). PROJECTS (PRCODE,PRNAME,PRCITY). SPPR (SCODE,PCODE,PRCODE,QTY). Write algebraic solution to the following : Get SCODE values for suppliers who supply to both projects PR1 and PR2. Get PRCODE values for projects supplied by at least one supplier not in the same city.
asked
Apr 18, 2016
in
Databases
by
jothee
Veteran
(
99.6k
points)

441
views
sql
gate1991
normal
databases
+23
votes
2
answers
10
GATE199115,b
Consider the following first order formula: ... Does it have finite models? Is it satisfiable? If so, give a countable model for it.
asked
Nov 16, 2015
in
Mathematical Logic
by
ibia
Active
(
3.4k
points)

1.6k
views
gate1991
firstorderlogic
descriptive
+14
votes
4
answers
11
GATE199117,a
Show that the Turing machines, which have a read only input tape and constant size work tape, recognize precisely the class of regular languages.
asked
Nov 15, 2015
in
Theory of Computation
by
Arjun
Veteran
(
418k
points)

936
views
gate1991
theoryofcomputation
descriptive
identifyclasslanguage
+27
votes
3
answers
12
GATE199116b
Show that all vertices in an undirected finite graph cannot have distinct degrees, if the graph has at least two vertices.
asked
Nov 15, 2015
in
Graph Theory
by
Arjun
Veteran
(
418k
points)

1.1k
views
gate1991
graphtheory
degreeofgraph
descriptive
+5
votes
0
answers
13
GATE19916,b
Design a 1024 bit serialin/serialout unidirectional shift register using a 1K $\times$ 1 bit RAM with a data input $D_{in}$, data output $D_{out}$ and control input $\text{READ}/\overline{\text{WRITE}}$. You may assume the availability of standard SSI and MSI components such as gates, registers and counters.
asked
Nov 14, 2015
in
Digital Logic
by
ibia
Active
(
3.4k
points)

308
views
gate1991
digitallogic
logic
nongate
+35
votes
4
answers
14
GATE19915c
Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10$ $\text{ns}$. Also assume that the setup time for the $JK$ inputs of the flip flops is negligible.
asked
Nov 14, 2015
in
Digital Logic
by
ibia
Active
(
3.4k
points)

4.9k
views
gate1991
digitallogic
flipflop
+13
votes
2
answers
15
GATE19915b
Find the minimum sum of products form of the logic function $ f(A,B,C,D) = \Sigma m(0,2,8,10,15)+ \Sigma d(3,11,12,14)$ where $m$ and $d$ represent minterm and don't care term respectively.
asked
Nov 14, 2015
in
Digital Logic
by
ibia
Active
(
3.4k
points)

606
views
gate1991
digitallogic
minsumofproductsform
+3
votes
1
answer
16
GATE199101,xi
The arithmetic expression $(a+b) * c d/e ** l$ is to be evaluated on a two address machine, where each operand is either a register or a memory location. With a minimum number of memory accesses of operands.the number of registers required to evaluate this expression is ______. The number of memory accesses of operands is ____________
asked
Nov 14, 2015
in
Compiler Design
by
ibia
Active
(
3.4k
points)

413
views
gate1991
compilerdesign
registerallocation
outofsyllabusnow
+21
votes
6
answers
17
GATE199117,b
Let $L$ be the language of all binary strings in which the third symbol from the right is a $1$. Give a nondeterministic finite automaton that recognizes $L$. How many states does the minimized equivalent deterministic finite automaton have? Justify your answer briefly?
asked
Sep 13, 2014
in
Theory of Computation
by
Kathleen
Veteran
(
52.1k
points)

2.4k
views
gate1991
theoryofcomputation
finiteautomata
normal
+30
votes
1
answer
18
GATE199116,a
Find the number of binary strings $w$ of length $2n$ with an equal number of $1's$ and $0's$ and the property that every prefix of $w$ has at least as many $0's$ as $1's.$
asked
Sep 13, 2014
in
Combinatory
by
Kathleen
Veteran
(
52.1k
points)

1.3k
views
gate1991
permutationandcombination
normal
descriptive
catalannumber
+11
votes
5
answers
19
GATE199115,a
Show that the product of the least common multiple and the greatest common divisor of two positive integers $a$ and $b$ is $a\times b$.
asked
Sep 13, 2014
in
Set Theory & Algebra
by
Kathleen
Veteran
(
52.1k
points)

553
views
gate1991
settheory&algebra
normal
numbertheory
proof
descriptive
+15
votes
4
answers
20
GATE199114,a
Consider the binary tree in the figure below: (a). What structure is represented by the binary tree?
asked
Sep 13, 2014
in
DS
by
Kathleen
Veteran
(
52.1k
points)

1.1k
views
gate1991
datastructure
binarytree
timecomplexity
normal
+13
votes
3
answers
21
GATE199113
Give an optimal algorithm in pseudocode for sorting a sequence of $n$ numbers which has only $k$ distinct numbers ($k$ is not known a Priori). Give a brief analysis for the timecomplexity of your algorithm.
asked
Sep 13, 2014
in
Algorithms
by
Kathleen
Veteran
(
52.1k
points)

1.4k
views
gate1991
sorting
timecomplexity
algorithms
difficult
+17
votes
5
answers
22
GATE199112a
Suppose a database consist of the following relations: SUPPLIER (SCODE,SNAME,CITY). PART (PCODE,PNAME,PDESC,CITY). PROJECTS (PRCODE,PRNAME,PRCITY). SPPR (SCODE,PCODE,PRCODE,QTY). Write SQL programs corresponding to the following queries: Print PCODE values for parts supplied ... part to a project in the second city, but do not print the triples in which the two CITY values are same.
asked
Sep 13, 2014
in
Databases
by
Kathleen
Veteran
(
52.1k
points)

956
views
gate1991
databases
sql
normal
+1
vote
2
answers
23
GATE199111,a
Consider the following scheme for implementing a critical section in a situation with three processes $P_i, P_j$ and $P_k$. Pi; repeat flag[i] := true; while flag [j] or flag[k] do case turn of j: if flag [j] then begin flag [i] := false; ... turn := j; flag [i] := false noncritical section until false; Does the scheme ensure mutual exclusion in the critical section? Briefly explain.
asked
Sep 13, 2014
in
Operating System
by
Kathleen
Veteran
(
52.1k
points)

806
views
gate1991
processsynchronization
normal
operatingsystem
+15
votes
2
answers
24
GATE199110a
Consider the following grammar for arithmetic expressions using binary operators $$ and $/$ which are not associative $E \rightarrow E T\mid T$ $T \rightarrow T/F\mid F$ $F \rightarrow (E) \mid id$ ($E$ is the start symbol) Is the grammar unambiguous? Is so, what is the relative precedence between $$ and $/$? If not, give an unambiguous grammar that gives $/$ precedence over $$.
asked
Sep 13, 2014
in
Compiler Design
by
Kathleen
Veteran
(
52.1k
points)

1.2k
views
gate1991
grammar
compilerdesign
normal
descriptive
+18
votes
3
answers
25
GATE199109a
Consider the following pseudocode (all data items are of type integer): procedure P(a, b, c); a := 2; c := a + b; end {P} begin x := 1; y := 5; z := 100; P(x, x*y, z); Write ('x = ', x, 'z = ', z); end Determine its output, if the parameters are passed to the Procedure P by value reference name
asked
Sep 13, 2014
in
Compiler Design
by
Kathleen
Veteran
(
52.1k
points)

904
views
gate1991
compilerdesign
parameterpassing
normal
runtimeenvironments
+1
vote
0
answers
26
GATE199108,a,b
asked
Sep 13, 2014
in
CO and Architecture
by
Kathleen
Veteran
(
52.1k
points)

211
views
gate1991
coandarchitecture
outofsyllabusnow
normal
+1
vote
0
answers
27
GATE199107a
It is required to design a hardwired controller to handle the fetch cycle of a single address CPU with a $16$ bit instructionlength. The effective address of an indexed instruction should be derived in the fetch cycle itself. Assume that the ... bits of an instruction constitute the operand field. Give the register transfer sequence for realizing the above instruction fetch cycle.
asked
Sep 13, 2014
in
CO and Architecture
by
Kathleen
Veteran
(
52.1k
points)

294
views
gate1991
coandarchitecture
controlunit
hardwiredcontroller
normal
unsolved
+2
votes
1
answer
28
GATE199106,a
Using D flipflop gates, design a parallelin/serialout shift register that shifts data from left to right with the following input lines: Clock $\text{CLK}$ Three parallel data inputs $A, B, C$ Serial input $S$ Control input $\text{load} / \overline{\text{SHIFT}}$.
asked
Sep 13, 2014
in
Digital Logic
by
Kathleen
Veteran
(
52.1k
points)

328
views
gate1991
digitallogic
difficult
unsolved
+15
votes
1
answer
29
GATE19915a
Analyse the circuit in Fig below and complete the following table ${\begin{array}{ccc}\hline \textbf{a}& \textbf{b}& \bf{ Q_n} \\\hline 0&0\\\ 0&1 \\ 1&0 \\ 1&1 \\ \hline \end{array}}$
asked
Sep 13, 2014
in
Digital Logic
by
Kathleen
Veteran
(
52.1k
points)

1.1k
views
gate1991
digitallogic
normal
circuitoutput
+4
votes
0
answers
30
GATE199104,i,ii,iii,iv
asked
Sep 12, 2014
in
Non GATE
by
Kathleen
Veteran
(
52.1k
points)

201
views
gate1991
pascal
outofsyllabusnow
Page:
1
2
3
next »
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
GATE 2020 Application Form Opened!
My GATE Preparation Journey
ISI MTECH CS 2019 INTERVIEW EXPERIENCE
IIT HYDERABAD MTECH TA INTERVIEW EXPERIENCE
How to prepare for GATE with a fulltime job??
Follow @csegate
Recent questions tagged gate1991
Recent Blog Comments
will pdfs be uploaded ?
6th...
Sir
4th...
49,984
questions
55,135
answers
190,487
comments
85,110
users